The excimer-laser annealed (ELA) polycrystalline silicon (p-Si or polysilicon) thin film, which influences more than 100-billion-dollar display market, is the backplane material of the modern advanced LCD and OLED products. The microstructure (i.e. ELA microstructure) and surface morphology of an ELA p-Si thin film are the two main factors determining the material properties, and they significantly affect the performance of the subsequently fabricated thin film transistors (TFTs). The microstructure is the result of a rather complex crystallization process during the ELA which is characterized as far-from-equilibrium, multiple-pulse-per-area and processing-parameter dependent. Studies of the ELA microstructure and the surface morphology closely related to the device performance as well as the microstructure evolution during the ELA process are long-termly demanded by both the scientific research and the industrial applications, but unfortunately have not been thoroughly performed in the past. The main device-performance-related characteristics of the ELA microstructure are generally considered to be the grain size and the presence of the dense grain boundaries. In the work of this thesis, an image-processing-based program (referred to as the GB extraction program) is developed to extract the grain boundary map (GB map) out of the transmission electron microscope (TEM) images of the ELA microstructure. The grain sizes are straightforwardly calculated from the GB map and statistically analyzed. More importantly, based on the GB maps, we propose and perform a rigorous scheme that we call the local-microstructure analysis (LMA) to quantitatively and systematically analyze the spatial distribution of the grain boundaries. The “local area” is mainly defined by the geometry and the location of a TFT. The successful extraction of the GB map and the subsequent LMA are permitted by our unique TEM skills to produce high-resolution TEM micrographs containing statistically significant number of grains for sensible quantitative analysis. The LMA unprecedentedly enables quantitative and rigorous analysis of spatial characteristics of the microstructure, especially the device geometry- and location-related characteristics. Additionally, we present and highlight the benefits of the LMA approach over the traditional statistical grain-size analysis of the ELA microstructure. From the grain-size analysis, we find that grain size across a statistically significant number of grains generally follows the same distribution as in the stochastic grain growth scenario at the beginning of the ELA process when the laser pulse (i.e. shot) number is small. As the shot number increases, the overall grain size monotonically increases while the distribution profile becomes broader. When the scan number reaches the ELA threshold (several tens of laser shots), the distribution profile substantially deviates from the stochastic profile and shows two sharp peaks in grain size around 300nm and 450nm, which is consistent with the previously proposed theory of energy coupling and nonuniform energy deposition during ELA. From the LMA, local nonuniformity of grain boundary density (GB density) at the device length scales and regions of high grain boundary periodicity are identified. More importantly, we find that the local nonuniformity is much more pronounced when p-Si film exhibits some level of spatial ordering, but less pronounced for a random grain arrangement. It is worth noting that the devices of different sizes and orientation have different sensitivity to the local nonuniformity of the ELA-generated p-Si thin film. In addition, based on the analysis results, the connection between the microstructure evolution and the partial melting and resolidification process of the Si film is discussed. Aside from the microstructure, the surface morphology of the ELA films, featuring pronounced surface protrusions, is characterized via an atomic force microscope (AFM). Attempts to planarize those surface protrusions detrimental to the subsequent device performance are conducted. In the attempts, the as-is (oxide-capped) ELA films and the BHF-treated ELA films are subjected to single shots of excimer irradiation. When the results are compared, an anisotropic melting phenomenon of the p-Si grains is identified, which appears to be strongly affected by the presence of the surface oxide capping layer. Conceptual models are developed and numerical simulations are employed to explain the observation of the anisotropic melting phenomenon and the effect of the surface oxide layer. Eventually, 41.8% reduction of root mean square (RMS) surface roughness is achieved for BHF-treated ELA films. The results gained in the systematic analysis of the ELA microstructure and the attempt of surface planarization further our understanding about (1) the device performance-related material microstructure of the ELA p-Si thin films, (2) the microstructure evolution occurring during multiple shots of the ELA process, and (3) the fundamental phase transformations in the far-from-equilibrium melt-mediated excimer-laser annealing processing of p-Si thin films. Such understanding could help engineers when designing the microelectronic devices and the ELA manufacturing process, as well as provide scientific researchers with insights on the melting and solidification of general polycrystalline materials, thus profoundly contributing to both the related scientific society and the technological community. The GB extraction program and the LMA scheme developed and demonstrated in the thesis, as another contribution to the related research filed, could also be generalized to the microstructural study of other polycrystalline materials where grain geometry and arrangement are of concern.

La photonique sur silicium connaît depuis plusieurs années un fort développement avec la démonstration d’importants résultats concernant les interconnexions optiques. En effet, l’explosion du trafic de données au sein des centres de données a nécessité de trouver une solution annexe aux interconnexions métalliques afin de supporter de très hauts débits de transmission, tout en assurant une faible consommation énergétique et un coût raisonnable. Les applications de la photonique se situent d’une part dans le domaine des communications à longue distance entre équipements dont les standards actuels visent un débit de 400 Gb/s, et d’autre part dans le domaine des calculateurs à haute performance afin de réaliser les interconnexions courte distance entre un processeur et une banque de mémoires.STMicroelectronics s’est lancé depuis 2012 dans le développement d’une plateforme photonique sur silicium sur wafers de 300mm. Les principaux objectifs sont : la conception des composants optiques passifs et actifs pour réaliser un transceiver élémentaire à un débit de 20 Gb/s, l’intégration accrue des dispositifs électro-optiques afin de constituer un interposeur photonique, la capacité à gérer plusieurs longueurs d’onde.Dans ce contexte, le sujet de cette thèse porte sur la mise au point d’un circuit de qualification proposant l’intégration d’un transmetteur électro-optique à l’échelle de la puce.Cette solution tire bénéfice de l’architecture de l’assemblage en trois dimensions des éléments constitutifs au sein de l’interposeur et permet de traiter l’hétérogénéité des composants électriques et optiques.Dans ces travaux, nous proposons dans un premier temps d’étudier le modulateur optique. Celui-ci repose sur l’utilisation d’un anneau résonant dont la bande passante est optimisée afin de permettre des débits jusqu’à 50 Gb/s. Dans un second temps, nous décrivons la conception du driver électrique en technologie CMOS 55nm et expliquons le compromis mis en jeu entre la vitesse et la puissance consommée par le transmetteur. Les deux dispositifs sont fabriqués sur des plateformes distinctes, puis caractérisés et analysés par rapport à leur modèle respectif. Puis, nous réalisons une première intégration du transmetteur complet via un assemblage wire-bonding, ce qui nous permet de valider son fonctionnement et d’identifier les difficultés d’une telle co-intégration. Enfin, la dernière partie de la thèse est consacrée à la préparation d’un démonstrateur intégrant, dans un assemblage 3D à base de micro-piliers en cuivre, un lien électro-optique capable de transmettre 16 canaux à 20 Gb/s. Le multiplexage en longueurs d’onde déployé dans ce lien devrait permettre d’atteindre un débit total de 320 Gb/s. De plus, l’étude énergétique du système permet de s’assurer que l’interconnexion finale respectera les contraintes de consommation de puissance. / Stimulated by a series of important breakthrough, silicon photonics has been experiencing a significant development for several years. Indeed, due to exponential growth of data traffic inside datacenters, an alternative solution to metallic interconnects has been proposed to address very high transmission rates while ensuring a low energy consumption and a reasonable cost. Promising applications are in the field of both long- and short-distance optical communications. Long-range interconnects between datacenter equipment currently target an aggregate throughput of 400 Gb/s while short-reach interconnects are involved in high performance computers between a processor and a memory bank.STMicroelectronics has been developing a silicon photonic platform on 300 mm wafers since 2012. The main objectives are: the design of passive and active optical components to achieve an elementary 20 Gb/s transceiver, the increased integration of electro-optic devices to form a photonic interposer, the ability to manage several wavelengths.In this context, this PhD report deals with a testchip development at wafer level, proposing the integration of anelectro-optic transmitter. This solution benefits from the three dimensions assembly architecture of the dies within the photonic interposer and can handle the heterogeneity of electrical and optical components.This work first proposes to study the optical modulator which is based on a ring resonator. The ring bandwidth is optimized to operate up to 50 Gb/s. Secondly, the 55nm CMOS electrical driver design is described and the trade-off between transmitter speed and power consumption is highlighted. Both devices are fabricated on distinct technological platforms, then characterized and analyzed with respect to their respective models. A first integration of the complete transmitter is assembled through wire-bonding method, which enables to validate the transmitter operation. Finally, the last part of the report is devoted to the preparation of a 3D demonstrator based on micro-copper pillars assembly. The demonstrator integrates a wavelength division multiplexed link with 16 channels, which is expected to achieve a total throughput of 320 Gb/s. In addition, the system study enables to ensure that the final interconnect will respect power consumption constraints.

L’intégration de plusieurs capteurs inertiels au sein d’un même dispositif de type MEMS afin de pouvoir estimer plusieurs degrés de liberté devient un enjeu important pour le marché de l’électronique grand public à cause de l’augmentation et de la popularité croissante des applications embarquées. Aujourd’hui, les efforts d'intégration se concentrent autour de la réduction de la taille, du coût et de la puissance consommée. Dans ce contexte, la co-intégration d’un accéléromètre trois-axes avec un gyromètre trois-axes est cohérente avec la quête conjointe de ces trois objectifs. Toutefois, cette co-intégration doit s’opérer dans une même cavité basse pression afin de préserver un facteur de qualité élevé nécessaire au bon fonctionnement du gyromètre. Dans cette optique, un nouveau système de contrôle, qui utilise le principe de l’amortissement électrostatique, a été conçu pour permettre l’utilisation d’un accéléromètre sous amorti naturellement. Le principe utilisé pour contrôler l’accéléromètre est d’appliquer dans la contre-réaction une force électrostatique générée à partir de l’estimation de la vitesse du MEMS. Cette technique permet d’augmenter le facteur d’amortissement et de diminuer le temps d’établissement de l’accéléromètre. L’architecture proposée met en oeuvre une méthode novatrice pour détecter et contrôler le mouvement d’un accéléromètre capacitif en technologie MEMS selon trois degrés de liberté : x, y et z. L'accélération externe appliquée au capteur peut être lue en utilisant la variation de capacité qui apparaît lorsque la masse se déplace. Lors de la phase de mesure, quand une tension est appliquée sur les électrodes du MEMS, une variation de charge est appliquée à l’entrée de l’amplificateur de charge (Charge-to-Voltage : C2V). La particularité de cette architecture est que le C2V est partagé entre les trois axes, ce qui permet une réduction de surface et de puissance consommée. Cependant, étant donné que le circuit ainsi que l’électrode mobile (commune aux trois axes du MEMS) sont partagés, on ne peut mesurer qu’un seul axe à lafois. Ainsi, pendant la phase d'amortissement, une tension de commande, calculée pendant les phases de mesure précédentes, est appliquée sur les électrodes d'excitation du MEMS. Cette tension de commande représente la différence entre deux échantillons successifs de la tension de sortie du C2V et elle est mémorisée et appliquée trois fois sur les électrodes d’excitation pendantla même période d’échantillonnage. Afin d’étudier la faisabilité de cette technique, des modèles mathématiques, Matlab-Simulink et VerilogA ont été développés. Le principe de fonctionnement basé sur l’amortissement électrostatique simultané a été validé grâce à ces modèles. Deux approches consécutives ont été considérées pour valider expérimentalement cette nouvelle technique : dans un premier temps l’implémentation du circuit en éléments discrets associé à un accéléromètre sous vide est présentée. En perspective, un accéléromètre sera intégré dans la même cavité qu’un gyromètre, les capteurs étant instrumentés à l’aide de circuits CMOS intégrés. Dans cette cadre, la conception en technologie CMOS 0.18μm de l’interface analogique d’amortissement est présentée et validée par simulation dans le manuscrit. / Recently, consumer electronics industry has known a spectacular growth that would have not been possible without pushing the integration barrier further and further. Micro Electro Mechanical Systems (MEMS) inertial sensors (e.g. accelerometers, gyroscopes) provide high performance, low power, low die cost solutions and are, nowadays, embedded in most consumer applications. In addition, the sensors fusion has become a new trend and combo sensors are gaining growing popularity since the co-integration of a three-axis MEMS accelerometer and a three-axis MEMS gyroscope provides complete navigation information. The resulting device is an Inertial measurement unit (IMU) able to sense multiple Degrees of Freedom (DoF). Nevertheless, the performances of the accelerometers and the gyroscopes are conditioned by the MEMS cavity pressure: the accelerometer is usually a damped system functioning under an atmospheric pressure while the gyroscope is a highly resonant system. Thus, to conceive a combo sensor, aunique low cavity pressure is required. The integration of both transducers within the same low pressure cavity necessitates a method to control and reduce the ringing phenomena by increasing the damping factor of the MEMS accelerometer. Consequently, the aim of the thesis is the design of an analog front-end interface able to sense and control an underdamped three-axis MEMSaccelerometer. This work proposes a novel closed-loop accelerometer interface achieving low power consumption The design challenge consists in finding a trade-off between the sampling frequency, the settling time and the circuit complexity since the sensor excitation plates are multiplexed between the measurement and the damping phases. In this context, a patenteddamping sequence (simultaneous damping) has been conceived to improve the damping efficiency over the state of the art approach performances (successive damping). To investigate the feasibility of the novel electrostatic damping control architecture, several mathematical models have been developed and the settling time method is used to assess the damping efficiency. Moreover, a new method that uses the multirate signal processing theory and allows the system stability study has been developed. This very method is used to conclude on the loop stability for a certain sampling frequency and loop gain value. Next, a 0.18μm CMOS implementation of the entire accelerometer signal chain is designed and validated.

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Porous metal oxide materials, particularly those comprised of silica or titania, find use in many applications such as low-k dielectric materials for microelectronics as well as chemical sensors, micro/nanofluidic devices, and catalyst substrates. For this dissertation, the focus will be on the processing of porous metal oxide materials covering two subjects: hierarchical porosity exhibited over two discrete length scales and incorporation of functional nanomaterials. To generate the porous silica materials, the technique of supercritical carbon dioxide infusion (scCO2) processing was heavily relied upon. Briefly, the scCO2 infusion processing utilizes phase selective chemistries within a pre-organized amphiphilic block copolymer template using scCO2 as the reaction medium to selectively hydrolyze and condense silica precursors to yield mesoporous materials. To further develop the scCO2 infusion processing technique, hierarchically porous silica materials were generated on unique substrates. Hierarchically structured silica nanochannels were created using a combination of scCO2 infusion processing and nanoimprint lithography (NIL) patterned sacrificial polymer templates to yield mesopores and airgap structures respectively. Hierarchically porous silica materials were also generated on alternative substrates, in the form of cellulose filter paper, which were used to host the amphiphilic block copolymer template to yield tri-modal porosity silica materials. To extend the applicability of mesoporous silica generated from scCO2 infusion processing, functional nanomaterials, in the form of pre-synthesized gold nanoparticles, fullerene derivatives, and polyhedral oligomeric silsequioxanes (POSS) were embedded within the mesoporous silica to produce unique composite materials. The functional nanomaterials were able to impart specific properties, typically only affored to the functional nanomaterials, upon the mesoporous silica thin film with an example being enhanced thermal and hydrothermal properties of mesoporous silica doped with POSS molecules. To continue research with functional nanomaterials, nanoparticle composite materials, comprised of crystalline metal oxide nanoparticles and binder/filler materials, either organic or inorganic, were also evaluated as novel NIL resist materials. Patterning of the nanoparticle composite materials, specifically, but not limited to, titanium dioxide based materials, into two dimensional, arbitrarily shaped, sub-micron features was readily achieved on either rigid or flexible substrates. True three-dimensional structures, based on nanoparticle composite materials, were fabricated by utilizing release layers and pre-patterned substrates.

The aggressive reduction of feature size in silicon (Si)-based complimentary metal-oxide-semiconductor (CMOS) technology has resulted in an exponential increase in computing power. Stemming from increases in device density and substantial progress in materials science and transistor design, the integrated circuit has seen continual performance improvements and simultaneous reductions in operating power (VDD). Nevertheless, existing Si-based metal-oxide-semiconductor field-effect transistors (MOSFETs) are rapidly approaching the physical limits of their scaling potential. New material innovations, such as binary group IV or ternary III-V compound semiconductors, and novel device architectures, such as the tunnel field-effect transistor (TFET), are projected to continue transistor miniaturization beyond the Si CMOS era. Unlike conventional MOSFET technology, TFETs operate on the band-to-band tunneling injection of carriers from source to channel, thereby resulting in steep switching characteristics. Furthermore, narrow bandgap semiconductors, such as germanium (Ge) and InxGa1-xAs, enhance the ON-state current and improve the switching behavior of TFET devices, thus making these materials attractive candidates for further study. Moreover, epitaxial growth of Ge on InxGa1-xAs results in tensile stress (ε) within the Ge thin-film, thereby giving device engineers the ability to tune its material properties (e.g., mobility, bandgap) via strain engineering and in so doing enhance device performance. For these reasons, this research systematically investigates the material, optical, electronic transport, and heterointerfacial properties of ε-Ge/InxGa1-xAs heterostructures grown on GaAs and Si substrates. Additionally, the influence of strain on MOS interfaces with Ge is examined, with specific application toward low-defect density ε-Ge MOS device design. Finally, vertical ε-Ge/InxGa1-xAs tunneling junctions are fabricated and characterized for the first time, demonstrating their viability for the continued development of next-generation low-power nanoelectronic devices utilizing the Ge/InxGa1-xAs material system. / Doctor of Philosophy / The aggressive scaling of transistor size in silicon-based complimentary metal-oxide-semiconductor technology has resulted in an exponential increase in integrated circuit (IC) computing power. Simultaneously, advances in materials science, transistor design, IC architecture, and microelectronics fabrication technologies have resulted in reduced IC operating power requirements. As a consequence, state-of-the-art microelectronic devices have computational capabilities exceeding those of the earliest super computers at a fraction of the demand in energy. Moreover, the low-cost, high-volume manufacturing of these microelectronic devices has resulted in their nigh-ubiquitous proliferation throughout all aspects of modern life. From social engagement to supply chain logistics, a vast web of interconnected microelectronic devices (i.e., the "Internet of Things") forms the information technology bedrock upon which 21st century society has been built. Hence, as progress in microelectronics and related fields continues to evolve, so too does their impact on an increasingly dependent world. Moore's Law, or the doubling of IC transistor density every two years, is the colloquialism used to describe the rapid advancement of the microelectronics industry over the past five decades. As mentioned earlier, parallel improvements in semiconductor technologies have spearheaded great technological change. Nevertheless, Moore's Law is rapidly approaching the physical limits of transistor scaling. Consequently, in order to continue improving IC (and therefore microelectronic device) performance, new innovations in materials and fabrication science, and transistor and IC designs are required. To that end, this research systematically investigates the material, optical, and electrical properties of novel semiconductor material systems combining elemental (e.g., Germanium) and compound (e.g., Gallium Arsenide) semiconductors. Additionally, alternative transistor design concepts are explored that leverage the unique properties of the aforementioned materials, with specific application to low-power microelectronics. Therefore, through a holistic approach towards semiconductor materials, devices, and circuit co-design, this work demonstrates, for the first time, novel transistor architectures suitable for the continued development of next-generation low-power, high-performance microelectronic devices.

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<p>With the emergence of 5G/mm-Wave communication, there is a growing need for novel front-end electromechanical devices in filtering and carrier generation applications. CMOS-MEMS resonators fabricated using state-of-the-art Integrated Circuit (IC) manufacturing processes provide a significant advantage for power, area and cost savings. In this work, a comprehensive physics-based compact model capable of capturing the non-linear behaviour and other non-idealities has been developed for MEMS resonators seamlessly integrated in CMOS. As the first large signal model for CMOS-embedded resonators, it enables holistic design of MEMS components with advanced CMOS circuits as well as system-level performance evaluation within the framework of modern IC design tools. Global Foundries 14nm FinFET (GF14LPP) Resonant Body Transistors (fRBT) operating at 11.8 GHz are demonstrated and benchmarked against this large-signal electromechanical model. </p> <p><br></p> <p>Additionally, there is a growing interest in CMOS-integrable ferroelectric materials such as Hafnium Dioxide (HfO2) and Aluminum Scandium Nitride (AlScN) for next-generation memory and computation, as well as electromechanical transduction in CMOS-MEMS devices. This work also explores the performance of 700 MHz Ferroelectric Capacitor-based resonators in the Texas Instruments HPE035 process under high-power operating conditions. Identification of previously unreported characteristics, together with the first nonlinear large signal model for integrated ferroelectric resonators, provides insights on the design of frequency references and acoustic filters using ferroelectric transducers. </p> <p><br></p> <p>Extending the range of unreleased CMOS-MEMS resonators to lower frequency using novel design, we also investigate embedded transducers in chip-scale devices for physical sensing. We have simulated and modeled the transducer coupling for low-frequency propagating modes and benchmarked their projected performance against state-of-the-art conventional MEMS sensors. A new approach to phononic crystal (PnC) Interdigitated Transducers (IDTs) is presented emulating the acoustic dispersion in conventional ICs. Unloaded quality factors up to 15,000 have been measured in $\sim$80 MHz resonators, demonstrating their capacity for resonant rotation sensing. We present a unique methodology to amplify and collimate acoustic waves using CMOS-design-rule-compliant Graded Index (GRIN) Phononic IDTs. Ultimately, the CMOS-MEMS techniques presented in this work for both RF applications and physical sensing can facilitate additional functionality in standard CMOS and emerging 3D heterogeneously integrated (3DHI) ICs with minor or no modifications to manufacturing and packaging. This enables new paradigms in next-generation communications, internet of things (IoT), and hardware security.</p>

The research presented here investigates the effects of laser trimming on the state of stress in alumina Al₂O₃ hybrid microelectronics substrates. Evaluation of stress was performed using x-ray diffraction residual stress analysis and dynamic strain measurements using strain gages before and after laser trimming. X-ray diffraction measurements were carried out in both the longitudinal and transverse directions on the front and back sides of the substrates. The dynamic strain measurements were performed in situ with strain gages attached to the bottom of the substrates while the substrates were trimmed with a 400 watt YAG laser. The substrates were characterized using optical microscopy, scanning electron microscopy / energy dispersive x-ray analysis (SEM/EDAX), electron probe microanalysis (EPMA) and electron spectroscopy for chemical analysis (ESCA). The results from these characterization steps gave results for fractography (optical), surface and bulk composition (SEM/EDAX), chemical composition (ESCA) and phase analysis (EPMA). Results show that laser trimming produces stress gradients which are generally tensile in nature and could have deleterious effects on the mechanical integrity of the substrates if used in hybrid microelectronic applications. Furthermore the stress distribution across the substrates was found to be uniformly distributed showing no peak stresses near the heat affected zone (HAZ) boundary. Phase analysis determined that the substrates contained a magnesium aluminum spinel phase (MgAl₂O₄) and that the glass and pore phases are randomly distributed in the substrates. This could have some overall effect on the state of residual stress in the substrates after they have been laser trimmed. / Master of Science