As the microelectronic industry moves toward stacking of dies to achieve greater performance and smaller footprint, there are several reliability concerns when assembling the stacked dies on current organic substrates. These concerns include excessive warpage, interconnect cracking, die cracking, and others. Silicon interposers are being developed to assemble the stacked dies, and then the silicon interposers are assembled on organic substrates. Although such an approach could address stacked-die to interposer reliability concerns, there are still reliability concerns between the silicon interposer and the organic substrate. This work examines the use of diced glass panel as an interposer, as glass provides intermediate coefficient of thermal expansion between silicon and organics, good mechanical rigidity, large-area panel processing for low cost, planarity, and better electrical properties. However, glass is brittle and low in thermal conductivity, and there is very little work in existing literature to examine glass as a potential interposer material. Starting with a 150 x 150 mm glass panel with a thickness of 100 µm, this work has built alternating layers of dielectric and copper on both sides of the panel. The panels have gone through typical cleanroom processes such as lithography, electroplating, etc. Upon fabrication, the panels are diced into individual substrates of 25 x 25 mm and a 10 x 10 mm flip chip with a solder bump pitch of 75 um is then reflow attached to the glass substrate followed by underfill dispensing and curing. The warpage of the flip-chip assembly is measured. In parallel to the experiments, numerical models have been developed. These models account for viscoplastic behavior of the solder. The models also mimic material addition and etching through element “birth-and-death” approach. The warpage from the models has been compared against experimental measurements for glass substrates with flip chip assembly. It is seen that the glass substrates provide significantly lower warpage compared to organic substrates, and thus could be a potential candidate for future 3D systems.

Le domaine du diagnostic moléculaire connait un essor impressionnant depuis plusieurs dizaines d'années. Différents outils d'analyse d'interactions moléculaires sont présents sur le marché. La plupart d'entre eux sont basés sur des tests immunologiques utilisant la fluorescence comme technique de lecture. Or, l'utilisation de techniques de détection avec marquage comme la fluorescence augmente le coût d'une analyse et peut dénaturer un échantillon. Dans cette perspective, une technique de lecture optique sans marquage, qui est une alternative à la fluorescence, a été développée. Le principe de lecture est basé sur le suivi des modifications du spectre de diffraction de réseaux périodiques, composés de molécules sondes, lors d'interactions avec différentes solutions à analyser. Cette thèse CIFRE est le fruit d'une collaboration entre le LAAS CNRS et la société Innopsys, spécialisée dans la commercialisation d'outils de lecture optique. Elle porte sur le développement d'une plateforme dédiée à l'analyse biomoléculaire (ADN, protéines) au travers de l'utilisation de biopuces multiplexées et d'un instrument de lecture optique sans marquage automatisée. Nous montrons que cette technologie de biodétection sans marquage nécessite le développement d'une chimie de surface permettant l'organisation de molécules sondes en réseaux de lignes périodiques, tout en minimisant l'adsorption non-spécifique entre les lignes. Nous présentons l'optimisation d'un procédé de bi-fonctionnalisation de surface, qui met en jeu un dépôt multiplexé par microcontact printing sur des couches de polymères passivantes. Ces surfaces structurées à l'échelle moléculaire ont permis la détection d'interactions protéines/protéines sans marquage et le concept semble également transférable pour la détection d'hybridation de courtes séquences d'ADN.

The semiconductor industry has decreased silicon-based device feature sizes dramatically over the last two decades for improved performance. However, current technology has approached the limit of achievable enhancement via this method. Therefore, other techniques, including introducing stress into the silicon structure, are being used to further advance device performance. While these methods produce successful results, there is not a proven reliable method for stress and strain measurements on the nanometer scale characteristic of these devices. The ability to correlate local strain values with processing parameters and device performance would allow for more rapid improvements and better process control. In this research, x-ray diffraction and convergent beam electron diffraction have been utilized to quantify the strain behavior of simple and complex strained silicon-based systems. While the stress relaxation caused by thinning of the strained structures to electron transparency complicates these measurements, it has been quantified and shows reasonable agreement with expected values. The relaxation values have been incorporated into the strain determination from relative shifts in the higher order Laue zone lines visible in convergent beam electron diffraction patterns. The local strain values determined using three incident electron beam directions with different degrees of tilt relative to the device structure have been compared and exhibit excellent agreement.

En raison de la miniaturisation des dispositifs pour semi-conducteurs, le caractère aléatoire de la distribution de dopants dans un dispositif devient un paramètre critique pour les performances de ce dernier. Le but de ce travail est de valider une stratégie de dopage du silicium par un positionnement contrôlé de molécules, alternatif aux implantations, afin de limiter la variabilité de la tension de seuil. Nous avons choisi de contrôler la densité des sites et le positionnement des dopants en combinant le contrôle de la densité des sites d'ancrage et l'utilisation de molécules à fort encombrement stérique. Ceci a été réalisé en étudiant dans un premier temps le greffage de bore sur les silanols de silice amorphe partiellement traitée en température, à partir de molécules porteuses présentant des ligands de différentes tailles et des symétries ; le modèle de greffage a pu être déterminé en utilisant différentes techniques analytiques (IR-DRIFT, multi-core SSRMN et analyses élémentaires). L’élimination des ligands par un traitement thermique a permis de réaliser la fixation du Bore sur la silice avec un rendement supérieur à 96%. Cette méthode a été transférée avec succès à des wafers de silicium recouverts de silice native. Le recuit à haute température permettant la redistribution du bore dans le silicium a été ensuite validée par l’analyse VPD-ICPMS de l’oxyde greffé couplées aux mesures de profil de dopant dans le silicium obtenues par TofSIMS. Ce traitement a conduit à définir un procédé optimal par greffage sur silice mince, donnant des concentrations de dopant dans le silicium équivalentes à celles rapportées par la littérature sur silicium désoxydé, et sans passivation additionnelle de silice pour éviter la volatilisation du Bore greffé. En effet, la taille des ligands permet de contrôler la volatilisation du bore pendant recuit. Les analyses électriques par spectroscopie à effet tunnel ont confirmé l’activation électrique du dopant apporté par greffage et diffusé dans le silicium / With the everlasting shrinking of semiconductor devices, the randomness of dopant distribution within a device becomes more likely to critically impact the performance of the latter. The aim of this work is to validate a silicon doping strategy through a controlled positioning of molecules in place of conventional implantations in order to limit the variability of the threshold tension. In contrast to previous works, doping atoms were directly grafted onto a thin silica layer and not onto a bare silicon surface. Here, we chose to control both site density and positioning by combining the control of site anchoring density and the use of sterically hindered molecules to yield a finely structured doped surface. This was carried out by first optimizing this approach by studying the grafting of boron compounds with ligands of various sizes and symmetries on the surface silanols of non - porous amorphous silica partially treated at high temperatures (700 °C) as a model system. This allowed obtaining a fully characterization of surface species through combined analytical techniques (IR-DRIFT, solidstate multi-core NMR and elemental analyses). The ligands were then eliminated by a thermal treatment, yielding surface boronic acids characterized by IR-DRIFT and NMR with optimal density (> 96%, 6.7*1013 B.cm-²). This technology was then successfully transferred to silicon wafers covered with native silica as evidenced by ICPMS analyses of the grafted oxide layer removed in HF droplet (VPD). Subsequent high temperature annealing step without capping in order to trigger diffusion of boron was then validated on silicon wafers using ICPMS in HF-dipped oxide and in silicon by TofSIMS profile measurements. Such treatment led to a dopant concentration in the silicon matrix equivalent to that reported in the literature (e.g. direct grafting on silicon and cap during annealing). Electrical analyses by tunnel spectroscopy showed the efficiency of the annealing step and confirmed the dopant amount in the surface layer of the silicon wafer

Esta dissertação propõe uma metodologia de projeto de osciladores distribuídos controlados por tensão - DVCO - com realimentação reversa em freqüência de microondas. Estes constituem uma nova classe de osciladores recentemente proposta, a qual é obtida através da realimentação reversa de amplificadores distribuídos e tem como principal vantagem a possibilidade de sintonia em faixa ultra-larga de freqüência. São apresentados os fundamentos teóricos de operação do circuito e é proposta uma extensão da análise linear apresentada na literatura, considerando linhas de transmissão artificiais m-derivadas, a qual permite prever as transcondutâncias mínimas necessárias dos transistores e a freqüência inicial de oscilação. O método de projeto proposto é direcionado a DVCOs com realimentação reversa empregando transistores de efeito de campo dos tipos MESFET (Metal Semiconductor Field Effect Transistor) e PHEMT (Pseudomorfic High Electron Mobility Transistor), bem como ao uso de tecnologia de circuitos híbridos de microondas - MICs, e circuitos integrados monolíticos de microondas - MMICs. A metodologia proposta definiu critérios para implementar a topologia deste circuito através de componentes reais, considerando-se os parasitas associados aos mesmos. Para validação do procedimento de projeto, concebeu-se e simulou-se através do programa ADS da Agilent um oscilador intitulado DVCO 3 GHz, cuja faixa de freqüência especificada estende-se de 1 a 3 GHz e a potência mínima de saída especificada é de 10 dBm. Um protótipo foi construído em circuito híbrido e seus resultados experimentais foram comparados aos simulados. A freqüência de oscilação medida foi de 1,04 GHz a 3,05 GHz e a potência obtida esteve entre 9,8 e 14,3 dBm, apresentando boa concordância com as simulações. O ruído de fase foi medido entre 100 kHz e 1 MHz de distância da portadora, observando-se uma inclinação proporcional a 1/f3. Verificou-se que a diminuição da corrente de polarização Ids dos transistores, através da redução de sua tensão de polarização de porta-fonte Vgs, melhorou o ruído de fase. Na condição de polarização de menor ruído de fase, observaram-se valores entre -84 e -93 dBc/Hz a 100 kHz da portadora. / In this dissertation, a design methodology applied to microwave reverse feedback distributed voltage controlled oscillators - DVCO - is proposed. This circuit constitutes a new class of oscillators, obtained from reverse feeding back of the distributed amplifier. The main advantage of this topology is its capacity to achieve ultra-wideband frequency tuning. Circuit theoretical background is presented and an extension of the linear analysis presented in the literature is proposed. It allows predicting transistor minimum transconductances and the oscillation initial frequency, considering m-derived artificial transmission lines. The proposed design method is applicable to reverse feedback DVCOs employing field effect transistors MESFET (Metal Semiconductor Field Effect Transistor) and PHEMT (Pseudomorfic High Electron Mobility Transistor), as well as using MIC (Microwave Integrated Circuits) and MMIC (Monolithic Microwave Integrated Circuits) technology. The proposed methodology defined criterion to employ real components, considering the component parasitics. In order to validate the design method, an oscillator named DVCO 3 GHz was designed and simulated through software Agilent ADS, with specified band from 1 up to 3 GHz and minimum output power of 10 dBm. A prototype was implemented in hybrid circuit technology and the measurements were compared to the simulation results. The measured oscillation frequency varied from 1,04 GHz up to 3,05 GHz and the output power was 9,8 to 14,3 dBm, presenting good agreement with simulations. Phase noise was measured in the range between 100 kHz and 1 MHz shift from carrier; in which it was observed a 1/f3 slope. It was verified that decreasing the transistor bias current Ids through decreasing its gate bias voltage Vgs reduced phase noise. In the biasing condition for lowest phase noise, values between -84 and -93 dBc/Hz at 100 kHz off-set from carrier were measured.

De nos jours, les concepteurs de dispositifs cryptographiques doivent non seulement mettre en œuvre des algorithmes robustes, mais ils doivent également s'assurer qu'il n'y ait pas de fuites d'informations à travers plusieurs canaux latéraux lors de l'exécution d'un algorithme. En effet, si ce n'est pas le cas, les implémentations cryptographiques, tant symétriques qu'asymétriques, seront vulnérables aux attaques par canaux auxiliaires. Pour les algorithmes à clé publique tels que le RSA, l'opération principale que doit être rendue robuste est l'exponentiation modulaire sur un anneau fini. Les principales solutions (contremesures) permettant de rendre robuste l'exponentiation modulaire à ces attaques par canaux auxiliaires sont basées sur la randomisation des données traitées. La randomisation de l'exposant et celle des messages sont en effet des techniques particulièrement efficaces pour contrecarrer les attaques par collision et par analyse des corrélations verticales. Toutefois, ces solutions éculées montrent leurs limites par rapport aux attaques dites horizontales qui n'exploitent qu'une exponentiation. Dans ce contexte, ce document relate le travail de conception, tant matériel que logiciel, d'un chiffreur RSA basé sur les systèmes modulaires de représentation des nombres (RNS). Ce chiffreur incorpore différentes contremesures définies à divers niveaux d'abstraction. L'évaluation de sa robustesse aux attaques par canaux cachés tant horizontales que verticales a démontré sa pertinence. / Not only designers of cryptographic devices have to implement the algorithmsefficiently, they also have to ensure that sensible information that leaks throughseveral side-channels (time, temperature, power consumption, electromagneticemanations, etc.) during the execution of an algorithm, remains unexploitedby an attacker. If not sufficiently protected, both symmetric and asymmetriccryptographic implementations are vulnerable to these so-called side-channelattacks (SCA). For public-key algorithms such as RSA, the main operation to bearmoured consists of a multi-digit exponentiation over a finite ring.Countermeasures to defeat most of side-channel attacks onexponentiations are based on randomization of processed data. The exponentand the message blinding are particular techniques to thwartsimple, collisions, differential and correlation analyses. Attacks based ona single (trace) execution of exponentiations, like horizontal correlationanalysis and profiled template attacks, have shown to be efficient againstmost of popular countermeasures.This work proposes a hardware and software implementations of RSA based on Residue Number System (RNS). Different countermeasures are implemented on different abstraction levels. Then, chosen-message and correlation attacks, based on both multi-trace and single-trace attacks are applied to evaluate the robustness of adopted countermeasures. Finally, we propose an improved single-execution attack based on unsupervised learning and multi-resolution analysis using the wavelet transform.

FPGAs (Field Programmable Gate Arrays) dinamicamente reconfiguráveis (DR-FPGAs) são soluções promissoras para muitos sistemas embarcados devido a potencial redução de área de silício. Metodologias de projeto e ferramentas CAD relacionadas são ainda muito limitadas para auxiliarem os projetistas a encontrarem soluções dinamicamente reconfiguráveis para diferentes aplicações. Este trabalho propõe uma metodologia de projeto que combina modelos de alto nível em SystemC, técnicas de projeto de baixo nível e a metodologia de projeto modular da XILINX. SystemC foi utilizada para representar o comportamento de alto nível não temporizado e não-RTL, bem como o baixo nível RTL-DCS (Chaveamento Dinâmico de Circuitos). Um estudo de caso da Banda Base de um Controlador Bluetooth foi desenvolvido. Duas partições temporais foram testadas em nove diferentes DR-FPGAs. A exploração espacial mostrou que 33% das soluções investigadas atenderam a restrição da especificação de 625µs de tempo do quadro do pacote Bluetooth, deixando diferentes parcelas de recursos livres que podem ser explorados para acomodar outros módulos IP de sistemas mais complexos no mesmo dispositivo. / Dynamically Reconfigurable Field Programmable Gate Arrays (DR-FPGAs) are promising solutions for many embedded systems due to the potential silicon area reduction. Design methodologies and related CAD tools are still very limited to assist designers to encounter dynamically reconfigurable solutions for different applications. This work proposes a design methodology that combines high level SystemC models and design techniques with the low level modular design proposed by Xilinx. SystemC has been used to represent the high level untimed non-RTL behavior as well as the low level RTL-DCS (Dynamic Circuit Switching). A Bluetooth Baseband unit case study was performed. Two temporal-functional partitions were evaluated on nine different target DR-FPGAs. The design space exploration showed that 33% of the investigated solutions complied with the 625µs Bluetooth packet time frame specification leaving different amounts if free resources that may be explored to accommodate other IP modules of more complex systems on the same device.

Este trabalho apresenta um método de fabricação de micropontas de silício que já contém os contatos elétricos integrados à sua estrutura. O processo de fabricação das microestruturas é o foco desta pesquisa e nossa motivação futura é desenvolver dispositivos para emissão eletrônica por efeito de campo (Field Emission Devices - FED. O método em questão baseia-se: (i) no underetch anisotrópico, que ocorre em substratos de silício (100) quando orientados de maneira conveniente, em solução de KOH; (ii) na utilização de filme de oxinitreto de silício (SiOxNy), que visa o mascaramento no processo de corrosão durante a formação das micropontas e também, o suporte mecânico para as trilhas metálicas que formam o eletrodo de polarização. Tal material, obtido por Deposição Química a Vapor assistida por Plasma (Plasma Enhanced Chemical Vapour Deposition - PECVD), apresenta baixo stress interno e tem a função de isolar eletricamente os eletrodos do substrato de Si. Esse filme de SiOxNy viabilizou a obtenção de trilhas autosustentadas, planas e lisas, com dimensões de até 6 milímetros. Através de técnicas convencionais de fotolitografia construímos contatos elétricos de cromo auto-alinhados sobre as micropontas. Metodologicamente definimos e caracterizamos, por meio de microscopia óptica, diferentes etapas da formação das micropontas, determinamos suas respectivas taxas de corrosão e consequentemente o tempo total de sua formação, em função das dimensões iniciais da máscara. As estruturas foram fabricadas na forma de matrizes com 50, 98, 112 e 113 micropontas. O espaçamento entre elas varia de 130 a 450 ?m. O diâmetro do ápice e a altura são de aproximadamente 1 e 54 ?m respectivamente. A principal vantagem deste método de fabricação é a eliminação da necessidade de utilização de microposicionadores externos e de acionamento manual, para a integração de contatos elétricos à estrutura. Finalmente, o êxito deste método deveu-se essencialmente às propriedades exclusivas do filme de SiOxNy. / This work presents a fabrication method of silicon microtips with integrated electrical contacts into the structure. Our motivation is the future development of field emission devices - FED, however our focus in this research is the microstructure fabrication process. This method is based on: (i) anisotropic under-etch method that occurs in the silicon substrate (100), when it is oriented in convenient crystallographic direction, using KOH solution; (ii) the employment of silicon oxinitride films (SiOxNy) which aims to mask the corrosion process during the formation of the microtips, and also to give mechanically support for the metallic tracks of their electrodes. Such material, which is obtained by Plasma Enhanced Chemical Vapour Deposition - PECVD, exhibits internal low stress and was used to obtain electric insulation between the electrodes and the Si substrate. These SiOxNy films made possible the achievement of flat and smooth selfsustained tracks, whose dimensions can reach 6 millimeters. Through conventional photolitographic techniques, we built chromium self-aligned electrical contacts on those microtips. Methodologically, we define and characterize different stages of microtips formation, by means of optical microscopy, and we determine their respective etch rates. And consequently the entire formation time in function of the initial mask dimensions. Those structures had been manufactured in the shape of matrices with 50, 98, 112 and 113 microtips which distance between each other can vary from 130 to 450 ?m. Its diameter in the microtip apex and its height are about 1 and 54 ?m respectively. The main advantage of this fabrication method is the lack of the requirement of manual external micropositioners for the integration of electrical contacts to structure itself. Finally, this method succeeds due essentially to the SiOxNy exclusive film properties.

Este estudo tem por objetivo o desenvolvimento de uma metodologia de fabricação de sistemas Lab On Chip, úteis no estudo de processos celulares, a partir da adaptação de tecnologias próprias da microeletrônica. Foram exploradas todas as etapas envolvidas na fabricação de sistemas Lab On Chip em Poli-Di-Metil-Siloxano e desenvolvidos protocolos de fabricação de moldes, técnicas de moldagem e processos de ativação de PDMS com plasma de oxigênio para sua solda química sobre diferentes materiais, obtendo uniões irreversíveis que permitem a integração com outras tecnologias como a microeletrônica em silício e o encapsulamento com cerâmica verde, completando uma metodologia que permite a prototipagem de dispositivos micro-fluídicos de multicamadas com um nível de sofisticação comparável ao estado da arte. Foi desenvolvido o protótipo de um equipamento ótico para litografia por projeção que permite a fabricação de máscaras óticas com resolução de 5 m e oferece a possibilidade de litografia em escala de cinzas para gerar canais e estruturas com relevos arbitrários. Foram adicionalmente abordados três problemas de biofísica celular, para os quais foram propostos novos dispositivos para separação de células móveis de acordo às suas velocidades lineares, dispositivos para crescimento confinado de bactérias e dispositivos para manipulação da curvatura de membranas celulares. / The objective of this study is the development of a methodology for the fabrication of Lab On Chip systems, useful for the analysis of cellular processes, through the adaptation of technologies from microelectronics. All the steps involved with the fabrication of Lab on Chip system in Poly-Di-Methil-Siloxane (PDMS) were explored, developing protocols for mold fabrication, molding techniques and processes for oxygen plasma activation of PDMS for its bonding to different materials, achieving irreversible bonds that enable the integration with other technologies such as silicon microelectronics and green tape packaging. All this techniques constitute a methodology that allows the prototyping of multilayer microfluidic devices comparable with state of the art devices. It was developed the prototype of optical equipment for projection lithography capable of mask fabrication with 5 m resolution, and which offers also the capability of gray scale lithography for the generation of free form microchannels. Additionally three different problems in cellular biophysics where boarded, proposing new devices for the separation of motile cells according to their linear speeds in liquids, new devices for constrained bacterial growth and for curvature manipulation of cell membranes.

Este trabalho apresenta um método de fabricação de micropontas de silício que já contém os contatos elétricos integrados à sua estrutura. O processo de fabricação das microestruturas é o foco desta pesquisa e nossa motivação futura é desenvolver dispositivos para emissão eletrônica por efeito de campo (Field Emission Devices - FED. O método em questão baseia-se: (i) no underetch anisotrópico, que ocorre em substratos de silício (100) quando orientados de maneira conveniente, em solução de KOH; (ii) na utilização de filme de oxinitreto de silício (SiOxNy), que visa o mascaramento no processo de corrosão durante a formação das micropontas e também, o suporte mecânico para as trilhas metálicas que formam o eletrodo de polarização. Tal material, obtido por Deposição Química a Vapor assistida por Plasma (Plasma Enhanced Chemical Vapour Deposition - PECVD), apresenta baixo stress interno e tem a função de isolar eletricamente os eletrodos do substrato de Si. Esse filme de SiOxNy viabilizou a obtenção de trilhas autosustentadas, planas e lisas, com dimensões de até 6 milímetros. Através de técnicas convencionais de fotolitografia construímos contatos elétricos de cromo auto-alinhados sobre as micropontas. Metodologicamente definimos e caracterizamos, por meio de microscopia óptica, diferentes etapas da formação das micropontas, determinamos suas respectivas taxas de corrosão e consequentemente o tempo total de sua formação, em função das dimensões iniciais da máscara. As estruturas foram fabricadas na forma de matrizes com 50, 98, 112 e 113 micropontas. O espaçamento entre elas varia de 130 a 450 ?m. O diâmetro do ápice e a altura são de aproximadamente 1 e 54 ?m respectivamente. A principal vantagem deste método de fabricação é a eliminação da necessidade de utilização de microposicionadores externos e de acionamento manual, para a integração de contatos elétricos à estrutura. Finalmente, o êxito deste método deveu-se essencialmente às propriedades exclusivas do filme de SiOxNy. / This work presents a fabrication method of silicon microtips with integrated electrical contacts into the structure. Our motivation is the future development of field emission devices - FED, however our focus in this research is the microstructure fabrication process. This method is based on: (i) anisotropic under-etch method that occurs in the silicon substrate (100), when it is oriented in convenient crystallographic direction, using KOH solution; (ii) the employment of silicon oxinitride films (SiOxNy) which aims to mask the corrosion process during the formation of the microtips, and also to give mechanically support for the metallic tracks of their electrodes. Such material, which is obtained by Plasma Enhanced Chemical Vapour Deposition - PECVD, exhibits internal low stress and was used to obtain electric insulation between the electrodes and the Si substrate. These SiOxNy films made possible the achievement of flat and smooth selfsustained tracks, whose dimensions can reach 6 millimeters. Through conventional photolitographic techniques, we built chromium self-aligned electrical contacts on those microtips. Methodologically, we define and characterize different stages of microtips formation, by means of optical microscopy, and we determine their respective etch rates. And consequently the entire formation time in function of the initial mask dimensions. Those structures had been manufactured in the shape of matrices with 50, 98, 112 and 113 microtips which distance between each other can vary from 130 to 450 ?m. Its diameter in the microtip apex and its height are about 1 and 54 ?m respectively. The main advantage of this fabrication method is the lack of the requirement of manual external micropositioners for the integration of electrical contacts to structure itself. Finally, this method succeeds due essentially to the SiOxNy exclusive film properties.