Thesis (Ph.D)--Electrical and Computer Engineering, Georgia Institute of Technology, 2010. / Committee Chair: Prof. Ali Adibi; Committee Member: Prof. Joseph Perry; Committee Member: Prof. Stephen Ralph; Committee Member: Prof. Thomas Gaylord. Part of the SMARTech Electronic Thesis and Dissertation Collection.

Thesis (Ph.D)--Mechanical Engineering, Georgia Institute of Technology, 2010. / Committee Chair: Samuel Graham; Committee Member: Donald Dorsey; Committee Member: Douglas Yoder; Committee Member: Michael Leamy; Committee Member: Sankar Nair; Committee Member: Zhuomin Zhang. Part of the SMARTech Electronic Thesis and Dissertation Collection.

Thesis (Ph. D.)--University of California, Santa Cruz, 1988. / Typescript. "1707." Includes bibliographical references (leaves 387-405).

Thesis (M.S.)--Rochester Institute of Technology, 2005. / Typescript. Includes bibliographical references (leaves 89-94).

Thesis (M.S.)--Rochester Institute of Technology, 2006. / Typescript. Includes bibliographical references.

Thesis (Ph. D.)--Oregon State University, 2007. / Printout. Includes bibliographical references. Also available on the World Wide Web.

Thesis (M.S.)--Virginia Polytechnic Institute and State University, 1994. / Vita. Abstract. Includes bibliographical references (leaves 121-126). Also available via the Internet.

abstract: The increased use of commercial complementary metal-oxide-semiconductor (CMOS) technologies in harsh radiation environments has resulted in a new approach to radiation effects mitigation. This approach utilizes simulation to support the design of integrated circuits (ICs) to meet targeted tolerance specifications. Modeling the deleterious impact of ionizing radiation on ICs fabricated in advanced CMOS technologies requires understanding and analyzing the basic mechanisms that result in buildup of radiation-induced defects in specific sensitive regions. Extensive experimental studies have demonstrated that the sensitive regions are shallow trench isolation (STI) oxides. Nevertheless, very little work has been done to model the physical mechanisms that result in the buildup of radiation-induced defects and the radiation response of devices fabricated in these technologies. A comprehensive study of the physical mechanisms contributing to the buildup of radiation-induced oxide trapped charges and the generation of interface traps in advanced CMOS devices is presented in this dissertation. The basic mechanisms contributing to the buildup of radiation-induced defects are explored using a physical model that utilizes kinetic equations that captures total ionizing dose (TID) and dose rate effects in silicon dioxide (SiO2). These mechanisms are formulated into analytical models that calculate oxide trapped charge density (Not) and interface trap density (Nit) in sensitive regions of deep-submicron devices. Experiments performed on field-oxide-field-effect-transistors (FOXFETs) and metal-oxide-semiconductor (MOS) capacitors permit investigating TID effects and provide a comparison for the radiation response of advanced CMOS devices. When used in conjunction with closed-form expressions for surface potential, the analytical models enable an accurate description of radiation-induced degradation of transistor electrical characteristics. In this dissertation, the incorporation of TID effects in advanced CMOS devices into surface potential based compact models is also presented. The incorporation of TID effects into surface potential based compact models is accomplished through modifications of the corresponding surface potential equations (SPE), allowing the inclusion of radiation-induced defects (i.e., Not and Nit) into the calculations of surface potential. Verification of the compact modeling approach is achieved via comparison with experimental data obtained from FOXFETs fabricated in a 90 nm low-standby power commercial bulk CMOS technology and numerical simulations of fully-depleted (FD) silicon-on-insulator (SOI) n-channel transistors. / Dissertation/Thesis / Ph.D. Electrical Engineering 2011

L'utilisation de dispositifs thermoélectriques à base de films minces en SiGe est envisagée dans de nombreuses applications comme la micro-génération de puissance ou le refroidissement localisé de composants microélectroniques. Le SiGe possède en effet un net avantage en terme d'integrabilite mais souffre cependant d'un déficit en terme de performances. Dans le cadre de cette thèse, nous nous sommes intéressés à la nanostructuration de ce matériau en super-réseau de boîtes quantiques (SRBQ), celle-ci devant permettre une forte augmentation de son facteur de mérite, rendue possible par une forte altération du transport thermique à l'échelle nanométrique. La réalisation, par un outil CVD de type industriel, à 750 °C, de SRBQ monocristallins lourdement dopés est présentée à partir d'analyses morphologiques (AFM), structurales (MEB, MET) et chimiques (SIMS). Des phénomènes de forts échanges Si-Ge pendant la croissance sont notamment mis en évidence et corrélés avec des mesures de conductivité thermique qui ne démontrent pas un effet significatif des boîtes sur le transport thermique. L'élaboration de structures polycristallines originales est également présentée. Enfin, la question cruciale de la détermination du facteur de mérite est abordée, notamment concernant les problèmes d'incertitudes de mesure. Une / Use of SiGe thin film thermoelectric devices is planed in many applications such as power microgeneration or local cooling of microelectronic components. One main advantage of SiGe relies on its ability to be monolithically integrated in ICs. However, SiGe is affected by a low coefficient of performance. Within the framework of this thesis, we focused on the nanostructuration of this material in the form of quantum dot superlattices (QDSL), which is expected to allow a strong increase of its figure-of-merit, by altering thermal transport at the nanometer scale. The growth of heavily doped monocrystalline QDSL in an industrial CVD tool at 750°C is presented from morphological (AFM), structural (SEM, TEM) and chemical (SIMS) analysis. Strong Si-Ge intermixing phenomenons are notably brought out and correlated with thermal conductivity measurements that do not demonstrate a significant effect of dots on thermal transport. The growth of original polycrystalline structures is also presented. Eventually, the crucial question of the figure-of-merit determination is addressed in particular with regard to the measurement uncertainty problem. One solution consisting in measuring simultaneously several electrical, thermal and thermoelectric parameters on a same sample is put forward and concretely implemented by the simultaneous fabrication of adapted test devices.

Este trabalho será focado no problema de posicionamento de células lógicas em circuitos integrados. Neste problema necessitamos organizar as portas lógicas reduzindo o comprimento dos fios que as conectam da melhor forma possível. Para entender o problema e as soluções existentes é descrita uma explanação sobre técnicas e algoritmos que são utilizados atualmente ou que são historicamente importantes, de forma a conduzir o texto para as técnicas apresentadas neste trabalho. As técnicas que serão apresentadas neste trabalho têm objetivos individualmente diferentes, porém conduzem a novos resultados e perspectivas em posicionamento. Todas as técnicas são baseadas na modificação e análise do grafo do posicionamento. Neste trabalho serão apresentadas quatro técnicas para melhorar a solução do problema de posicionamento. O primeiro trabalho a ser apresentado será a Critical Star que aplicado alguns nodos e arestas extras no grafo original para reduzir os caminhos críticos. A segunda técnica é a Logical Core I, ela traz um novo método de análise da dificuldade de posicionar um circuito VLSI. A terceira técnica, que tem forte conexão com a segunda, é a Logical Core II, mais focada em tempo de execução da técnica, ela gera um vetor com todas as dificuldades de posicionar cada célula no circuito. As duas técnicas aumentam o conhecimento do posicionador a respeito do problema e com isso vão de encontro a um ponto muito importante e ainda pouco abordado, a evolução da controlabilidade no posicionamento. A quarta técnica que será apresentada é a Logical Cluster. É uma técnica baseada na Logical Core II, e foi desenvolvida para otimizar os posicionadores já existentes no estado da arte. A técnica é muito eficiente e reduz o tempo de execução do posicionamento e muitas vezes reduz o comprimento de fio. / This work is focused on placement problem of VLSI circuits. The goal is organize the logic gates reducing the total wirelength that connect them. A non-effective placement assignment will not only affect the circuit performance but might also make it non-manufacturable by producing excessive wirelength. Then the next step in the assembly line, the routing problem could be insolvable. In this work will be presents four differents techniques. The techniques are based on changing the graph to improve the placement results. The first one is the Critical Star that applies some extra nodes and edges to reduce the critical paths. The second algorithm is the Logical Core I which brings a new method to analyze the circuit hardness to place a circuit. The third algorithm is called Logical Core II and the focus is generate a vector with hardness to place each cell in the circuit, and increasing the placer information about the problem. The Logical Core I and II, both improving the possibility to compare the hardnesses, in different abstraction levels, and improve the placement controllability. The fourth algorithm is a fast algorithm, based on use the Logical Core II, it creates an effective clustering technique to improve the state-of-art placers results. Reducing the runtime and sometimes improving the wirelength results.