Abstract In New Zealand there are currently no regular external audits to verify the full treatment chain in radiotherapy. This thesis reports on a project to devise such an audit procedure suitable to assess the accuracy of the delivery of prescribed radiotherapy doses to patients over the full treatment process. The National Radiation Laboratory (NRL), regulatory authority, will use the method developed to conduct biennial audits of all radiotherapy centres. A commercial chest phantom with a MOSFET dosimetry system was provided for this project. The MOSFETs were commissioned and their characteristics determined, namely reproducibility, energy dependence and angular dependence. The MOSFETs were also tested in a clinical environment with the phantom. Measurements were carried out to test the MOSFET capabilities in both lung and soft tissue in the phantom. Two plans were devised for the audit process, a straightforward one with two parallel opposed beams and a more complex one involving lung tissue and wedges. These plans were designed to test the entire treatment planning and delivery process. It was found that each MOSFET detector needed to be individually calibrated. Reproducibility was found to have an average standard deviation of 2% on standard sensitivity and 1.2% on high sensitivity. The angular dependence of the detectors showed that when the MOSFET was rotated by 90 degrees to the beam axis a drop in response of 3% was observed with 6 MV. The energy dependence factor was constant within uncertainty for all MOSFETs. Overall, the MOSFET and phantom dosimetry system was determined to be suitable for the audit. The measurements with phantom showed that doses in high dose regions could be determined accurately. The greatest variation from the Treatment Planning system dose to the measured dose was 6%. The trial runs of the audit in two New Zealand radiotherapy centres showed that the procedure created is able to find discrepancies within the desired 5%, recommended by the ICRU, in the prescribed dose to the phantom.

Nanocrystals embedded zirconium-doped hafnium oxide (ZrHfO) high-k gate dielectric films have been studied for the applications of the future metal oxide semiconductor field effect transistor (MOSFET) and nonvolatile memory. ZrHfO has excellent gate dielectric properties and can be prepared into MOS structure with a low equivalent oxide thickness (EOT). Ruthenium (Ru) modification effects on the ZrHfO high-k MOS capacitor have been investigated. The bulk and interfacial properties changed with the inclusion of Ru nanoparticles. The permittivity of the ZrHfO film was increased while the energy depth of traps involved in the current transport was lowered. However, the barrier height of titanium nitride (TiN)/ZrHfO was not affected by the Ru nanoparticles. These results can be important to the novel metal gate/high-k/Si MOS structure. The Ru-modified ZrHfO gate dielectric film showed a large breakdown voltage and a long lifetime. The conventional polycrystalline Si (poly-Si) charge trapping layer can be replaced by the novel floating gate structure composed of discrete nanodots embedded in the high-k film. By replacing the SiO2 layer with the ZrHfO film, promising memory functions, e.g., low programming voltage and long charge retention time, can be expected. In this study, the ZrHfO high-k MOS capacitors that separately contain nanocrystalline ruthenium oxide (nc-RuO), indium tin oxide (nc-ITO), and zinc oxide (nc-ZnO) have been successfully fabricated by the sputtering deposition method followed with the rapid thermal annealing process. Material and electrical properties of these kinds of memory devices have been investigated using analysis tools such as XPS, XRD, and HRTEM; electrical characterizations such as C-V, J-V, CVS, and frequency-dependent measurements. All capacitors showed an obvious memory window contributed by the charge trapping effect. The formation of the interface at the nc-RuO/ZrHfO and nc-ITO/ZrHfO contact regions was confirmed by the XPS spectra. Charges were deeply trapped to the bulk nanocrystal sites. However, a portion of holes were loosely trapped at the nanocrystal/ZrHfO interface. Charges trapped to the different sites lead to different detrapping characteristics. For further improving the memory functions, the dual-layer nc-ITO and -ZnO embedded ZrHfO gate dielectric stacks have been fabricated. The dual-layer embedded structure contains two vertically-separated nanocrystal layers with a higher density than the single-layer embedded structure. The critical memory functions, e.g., memory window, programming efficiency, and charge retention can be improved by using the dual-layer nanocrystals embedded floating gate structure. This kind of gate dielectric stack is vital for the next-generation nonvolatile memory applications.

In this study, the thin titanium oxide (TiO2) film deposited on InP substrate was prepared by atomic layer deposition (ALD), which was used as gate oxide of InP Schottky barrier MOSFET. First, aluminum oxide (Al2O3) by ALD can be used as improvement in oxide of TiO2. Al2O3 of ALD has self-cleaning which can improve interface between oxide and substrate, the leakage current densities can reach 3.1 ¡Ñ 10-9 and 3.3 ¡Ñ 10-7 A/cm2. The Schottky barrier height(£XBp) of Al/InP with (NH4)2S treatment is 0.968 eV, which is higher than that of Al/InP without (NH4)2S treatment (0.806eV). The (NH4)2S solution is a moderate etchant to reduce surface oxides on InP. Therefore, Schottky barrier will not be influenced by Fermi level pinning. The electrical characteristics of Schottky barrier MOSFET with TiO2 as gate oxide were measured in this report. The drain current is 1.73£gA. The drain current increases rapidly when drain voltage is over 1V, it indicates that breakdown field of TiO2 thin film is not high enough. Due to advantages of ALD-Al2O3, such as self-cleaning ability and high breakdown field, the TiO2/Al2O3 prepared by ALD structure was used to improve the problem mentioned above. The electrical characteristics are much improved compared with a single TiO2 film, and drain current can reach 1.37 £gA. The rapid increase of drain current with the increased drain voltage is not observed. The transconductance and mobility are 4.45 ¡Ñ 10-7 S/£gm and 202.3 mm2/V-s, respectively, and a good sub-threshold behavior is obtained. Compared with other researches, we can find that Schottky barrier in on-state is higher than that of silicide sample. It indicates the InP Schottky barrier MOSFET characteristics are limited by high Schottky barrier.

MOSFET-C filters is popular in analog filters, the major reason is the simplicity. They are easily implemented with opamps and have similar architectures to active RC filters [1], this saves much of the design time. The frequency response of analog continuous time filters is determined by resistors, capacitors, inductors or transconductors. However, the process variation, temperature drift and aging, make the integrated RC time constants vary about 30 percent [2]~[3]. We proposed a switched-capacitor tuning circuit , which can be used in MOSFET-C Filter and the novel tuning circuit doesn¡¦t need off chip capacitor. The novel circuit has following advantages (1). Small chip size. (2). Simplicity (3). Low reference clock frequency.

Thèse doctorat : Dispositifs de l'Electronique Intégrée : Villeurbanne, INSA : 2005. / Titre provant de l'écran-titre. Bibliogr. p. 183-197.

Novel logic and memory device concepts are proposed and analyzed. For the latter purpose the commercial technology computer aided design (TCAD) simulators Taurus and Sentaurus Device by Synopsys are used. These simulators allow ready definition of complex device geometries. Moreover, while not all device physics models are state-of-the-art, the wide variety of device physics considered is advantageous here when not all of the critical device physics is known a priori. The initial device concept analyzed was a one transistor (1T), one capacitor (1C) – pseudo-static random access memory (SRAM). Simulations indicate that tri-gate pass-transistors will offer better gate control and reduced leakage, and tri-gate capacitors will offer increased capacitance, making the overall device performance comparable to SRAM. The second device analyzed was a quantum dot non-volatile memory. In principle, such memories become more reliable for a given tunnel oxide thickness by localizing any leaks to individual dots. However, simulations illustrate limits on dot packing density to retain this advantage due to inter-dot tunneling. The final device, proposed and extensively analyzed here, is a novel tunnel field-effect transistor (TFET), the “hetero-barrier TFET” (HetTFET). In complementary metal-oxide-semiconductor (CMOS) logic, while switching power decreases with voltages, standby power increases due to thermionic emission of charge carriers over the source-to-channel barrier in the constituent metal-oxide-semiconductor field-effect transistors (MOSFETs). As a result, CMOS voltage and, thus, power scaling is approaching an impasse. Because TFETs are not subject to thermionic emission, they are being considering as a replacement for MOSFETs. Various materials systems and device geometries have been considered. However, even in simulation, balancing switching and standby power at low voltages while still providing sufficient transconductance for rapid switching has not proven straightforward. HetTFETs are intended to achieve high on-to-off current ratios via a threshold defined by the onset of band overlap, and high ON-state transconductances via tunneling through thin barriers defined by crystal growth, rather than relying on gate-controlled barrier narrowing in whole or part for either purpose as with other designs. Simulations of n and p-channel HetTFETs suggest the possibility of current CMOS-like performance at much lower voltages. / text

Abstract In New Zealand there are currently no regular external audits to verify the full treatment chain in radiotherapy. This thesis reports on a project to devise such an audit procedure suitable to assess the accuracy of the delivery of prescribed radiotherapy doses to patients over the full treatment process. The National Radiation Laboratory (NRL), regulatory authority, will use the method developed to conduct biennial audits of all radiotherapy centres. A commercial chest phantom with a MOSFET dosimetry system was provided for this project. The MOSFETs were commissioned and their characteristics determined, namely reproducibility, energy dependence and angular dependence. The MOSFETs were also tested in a clinical environment with the phantom. Measurements were carried out to test the MOSFET capabilities in both lung and soft tissue in the phantom. Two plans were devised for the audit process, a straightforward one with two parallel opposed beams and a more complex one involving lung tissue and wedges. These plans were designed to test the entire treatment planning and delivery process. It was found that each MOSFET detector needed to be individually calibrated. Reproducibility was found to have an average standard deviation of 2% on standard sensitivity and 1.2% on high sensitivity. The angular dependence of the detectors showed that when the MOSFET was rotated by 90 degrees to the beam axis a drop in response of 3% was observed with 6 MV. The energy dependence factor was constant within uncertainty for all MOSFETs. Overall, the MOSFET and phantom dosimetry system was determined to be suitable for the audit. The measurements with phantom showed that doses in high dose regions could be determined accurately. The greatest variation from the Treatment Planning system dose to the measured dose was 6%. The trial runs of the audit in two New Zealand radiotherapy centres showed that the procedure created is able to find discrepancies within the desired 5%, recommended by the ICRU, in the prescribed dose to the phantom.

Th. 3e cycle--Génie électrique--Nancy--I.N.P.L., 1984.

abstract: The existing compact models can reproduce the characteristics of MOSFETs in the temperature range of -40oC to 125oC. Some applications require circuits to operate over a wide temperature range consisting of temperatures below the specified range of existing compact models, requiring wide temperature range compact models for the design of such circuits. In order to develop wide temperature range compact models, fourteen different geometries of n-channel and p-channel MOSFETs manufactured in a 0.18μm mixed-signal process were electrically characterized over a temperature range of 40 K to 298 K. Electrical characterization included ID-VG and ID-VD under different drain, body and gate biases respectively. The effects of low-temperature operation on the performance of 0.18μm MOSFETs have been studied and discussed in terms of sub-threshold characteristics, threshold voltage, the effect of the body bias and linearity of the device. As it is well understood, the subthreshold slope, the threshold voltage, drive currents of the MOSFETs increase when the temperature of the MOSFETs is lowered, which makes it advantageous to operate the MOSFETs at low-temperatures. However the internal linearity gm1/gm3 of the MOSFETs degrades as the temperature of the MOSFETs is lowered, and the performance of the MOSFETs can be affected by the interface traps that exist in higher density close to conduction band and valence band energy levels, as the Fermi-level moves closer to bandgap edges when MOSFETs are operated at cryogenic temperatures. / Dissertation/Thesis / M.S. Electrical Engineering 2010

abstract: Semiconductor devices are generally analyzed with relatively simple equations or with detailed computer simulations. Most text-books use these simple equations and show device diagrams that are frequently very simplified and occasionally incorrect. For example, the carrier densities near the pinch-off point in MOSFETs and JFETs and the minority carrier density in the base near the reverse-biased base-collector junction are frequently assumed to be zero or near zero. Also the channel thickness at the pinch-off point is often shown to approach zero. None of these assumptions can be correct. The research in thesis addresses these points. I simulated the carrier densities, potentials, electric fields etc. of MOSFETs, BJTs and JFETs at and near the pinch-off regions to determine exactly what happens there. I also simulated the behavior of the quasi-Fermi levels. For MOSFETs, the channel thickness expands slightly before the pinch-off point and then spreads out quickly in a triangular shape and the space-charge region under the channel actually shrinks as the potential increases from source to drain. For BJTs, with collector-base junction reverse biased, most minority carriers diffuse through the base from emitter to collector very fast, but the minority carrier concentration at the collector-base space-charge region is not zero. For JFETs, the boundaries of the space-charge region are difficult to determine, the channel does not disappear after pinch off, the shape of channel is always tapered, and the carrier concentration in the channel decreases progressively. After simulating traditional sized devices, I also simulated typical nano-scaled devices and show that they behave similarly to large devices. These simulation results provide a more complete understanding of device physics and device operation in those regions usually not addressed in semiconductor device physics books. / Dissertation/Thesis / M.S. Electrical Engineering 2011