In recent years, multi-core processors and multi-processor networks have grown in popularity as a solution to the limits on increasing clock speed, rising power consumption, and the nanometer manufacturing processes. Multi-core processors and multi-processor networks are seen as the next step in the advancement of computational capabilities by way of concurrent processing. However, parallel software design is difficult due to the immaturity of scalable architectures and software development environments for multi-core hardware. How should processors effectively and quickly pass information, with as little overhead as possible? What kind of communication architecture is best suited for parallelism? How can large-scale architectures be quickly produced, verified and properly utilized by software? Using commercially available FPGA development boards, Xilinx tools and components, this thesis offers a light-weight solution to these questions for effective, low-overhead, low-latency multi-core communication and fast prototyping of multi-processor networks for scalable processor arrays. / Master of Science

This dissertation presents system and circuit development of the low-power multi-gigabit CMOS demodulator using analog and mixed demodulation techniques. In addition, critical building blocks of the low-power analog quadrature front-ends are designed and implemented using 90 nm CMOS with a targeted compatibility to the traditional demodulator architecture. It exhibits an IF-to-baseband conversion gain of 25 dB with 1.8 GHz of baseband bandwidth and a dynamic range of 23 dB while consuming only 46 mW from a 1 V supply voltage. Several different demodulators using analog signal processor (ASP) are implemented: (1) an ultra-low power non-coherent ASK demodulator is measured to demodulate a maximum speed of 3 Gbps while consuming 32 mW from 1.8 V supply; (2) a mere addition of 7.5 mW to the aforementioned analog quadrature front-end enables a maximum speed of 2.5 Gbps non-coherent ASK demodulation with an improved minimum sensitivity of -38 dBm; (3) a robust coherent BPSK demodulator is shown to achieve a maximum speed of 3.5 Gbps based on the same analog quadrature front-end with only additional 7 mW. Furthermore, an innovative seamless handover mechanism between ASP and PLL is designed and implemented to improve the frequency acquisition time of the coherent BPSK demodulator. These demodulator designs have been proven to be feasible and are integrated in a 60 GHz wireless receiver. The system has been realized in a product prototype and used to stream HD video as well as transfer large multi-media files at multi-gigabit speed.

Classical Molecular Dynamics simulation (MD) models the interactions of thousands to millions of particles through the iterative application of basic Physics. MD is one of the core methods in High Performance Computing (HPC). While MD is critical to many high-profile applications, e.g. drug discovery and design, it suffers from the strong scaling problem, that is, while large computer systems can efficiently model large ensembles of particles, it is extremely challenging for {\it any} computer system to increase the timescale, even for small ensembles. This strong scaling problem can be mitigated with low-latency, direct communication. Of all Commercial Off the Shelf (COTS) Integrated Circuits (ICs), Field Programmable Gate Arrays (FPGAs) are the computational component uniquely applicable here: they have unmatched parallel communication capability both within the chip and externally to couple clusters of FPGAs. This thesis focuses on the acceleration of the long range (LR) force, the part of MD most difficult to scale, by using FPGAs. This thesis first optimizes LR acceleration on a single-FPGA to eliminate the amount of on-chip communication required to complete a single LR computation iteration while maintaining as much parallelism as possible. This is achieved by designing around application specific memory architectures. Doing so introduces data movement issues overcome by pipelined, toroidal-shift multiplexing (MUXing) and pipelined staggering of memory access subsets. This design is then evaluated comprehensively and comparatively, deriving equations for performance and resource consumption and drawing metrics from previously developed LR hardware designs. Using this single-FPGA LR architecture as a base, FPGA network strategies to compute the LR portion of larger sized MD problems are then theorized and analyzed.

The objective of the research is to develop high-speed ADCs and mixed-signal demodulator for multi-gigabit communication systems using millimeter-wave frequency bands in standard CMOS technology. With rapid advancements in semiconductor technologies, mobile communication devices have become more versatile, portable, and inexpensive over the last few decades. However, plagued by the short lifetime of batteries, low power consumption has become an extremely important specification in developing mobile communication devices. The ever-expanding demand of consumers to access and share information ubiquitously at faster speeds requires higher throughputs, increased signal-processing functionalities at lower power and lower costs. In today’s technology, high-speed signal processing and data converters are incorporated in almost all modern multi-gigabit communication systems. They are key enabling technologies for scalable digital design and implementation of baseband signal processors. Ultimately, the merits of a high performance mixed-signal receiver, such as data rate, sensitivity, signal dynamic range, bit-error rate, and power consumption, are directly related to the quality of the embedded ADCs. Therefore, this dissertation focuses on the analysis and design of high-speed ADCs and a novel broadband mixed-signal demodulator with a fully-integrated DSP composed of low-cost CMOS circuitry. The proposed system features a novel dual-mode solution to demodulate multi-gigabit BPSK and ASK signals. This approach reduces the resolution requirement of high-speed ADCs, while dramatically reducing its power consumption for multi-gigabit wireless communication systems.

With rapid advances in semiconductor technologies and packaging schemes, wireless products have become more versatile, portable, inexpensive, and user friendly over last few decades. However, the ever-growing demand of consumers to share information efficiently at higher speeds requires higher data rates, increased functionality, lower cost, and more reliability. The 60-GHz-frequency band, with 7 GHz license-free bandwidth addresses, such demands, and promises a low-cost multi-Gbps wireless transmission with a power budget in the order of 100 mW. This dissertation presents the systematic development of key building blocks and integrated 60-GHz-receiver solutions. Two different approaches are investigated and implemented in this dissertation: (1) low-cost SiGe-based direct-conversion low-power receiver front-end utilizing gain-boosting techniques in the front-end low-noise amplifier, and (2) CMOS-based heterodyne receiver front-end suitable for high-performance single-chip 60 GHz transceiver solution. The ASK receiver chip, implemented using 0.18 ?m SiGe, presents a complete antenna-to-baseband multi-gigabit 60 GHz solution with the lowest reported power budget (25 pJ/bit) to date. The subharmonic direct conversion front-end, implemented using 0.18 ?m SiGe, presents excellent conversion properties with a 4 GHz DSB RF bandwidth. On the other hand, the CMOS heterodyne implementation of the 60 GHz front-end receiver, targeted towards a robust, single-chip, high-performance, low-power, and integrated 60 GHz transceiver solution, presents the most wideband receiver front-end reported to date. Finally, different multi-band and tunable millimeter-wave circuits are presented towards the future implementation of cognitive and multi-band millimeter-wave radio.