This thesis presents the development of a selective-etch fabrication process to create sub-10 nanometre metallic gaps and the subsequent use of the gaps to study the electronics of nanocrystals and molecules. A complete picture of the success of the process required both examination by scanning electron microscopy as well as probing the current response to an applied bias at low temperature. The empty gaps were fully characterised before self-assembling 7 nm CdSe nanocrystals onto the metal with the help of linker molecules. The I-V characteristics of the empty gaps showed a reduction of the tunnelling barrier height from the expected value (~5.1 eV, the work function of Au) when the results were fitted to the Simmons tunnelling model for a metal-insulator-metal system. Results indicate that after the barrier height is surpassed, a transition from direct to field-effect (Fowler-Nordheim) tunnelling occurs. After CdSe assembly, the collected I-V characteristics of the system at 77 K showed varied results. Many devices displayed conductance peaks at low voltages comparable to the results of the shadow evaporation process for 4.2 nm nanocrystals (also documented in this thesis). Several devices revealed switching between multiples of fundamental curves, suggesting conduction through multiples of nanocrystals.

Afin de poursuivre la réduction d'échelle des transistors MOS, l'industrie des semiconducteurs a su anticiper les limitations de la miniaturisation par l'introduction de nouveaux matériaux ou de nouvelles architectures. L'avènement des structures à triples grilles (FinFET) a permis de maitriser les effets canaux courts et poursuivre les efforts de miniaturisation (nœud technologique 14 nm en 2014). Le cas ultime pour le contrôle électrostatique de la grille sur le canal est donné par une grille entourant totalement le canal du dispositif. A cet effet, un transistor à nanofil à grille entourante est considéré comme la structure la plus adaptée pour les nœuds technologiques en dessous de 7 nm. Au cours de cette thèse, un procédé de réalisation large échelle de transistors MOSFET miniaturisés à base de nanofils verticaux en silicium a été développé. Tout d'abord, les nanofils verticaux ont été réalisés par une approche descendante via le transfert par gravure d'un masque de résine en Hydrogène Silsesquioxane (HSQ), réalisé par lithographie électronique à basse tension d'accélération. Une stratégie de dessin inédite dite "en étoile " a été développée pour définir des nanofils parfaitement circulaires. Les nanofils en Si sont obtenus par gravure plasma puis amincis par oxydation humide sacrificielle. Ce procédé permet d'obtenir des nanofils verticaux en Si avec des parois parfaitement anisotropes, une parfaite reproductibilité et un rendement maximal. L'implémentation des MOSFETs sur les réseaux nanofils a été effectuée par l'ingénierie successive de couches minces nanométriques (conductrices et diélectriques). Dans ce cadre, un procédé innovant de réalisation de couches d'isolations en HSQ par gravure chimique contrôlée a démontré une excellente planéité associée à une rugosité de surface inférieure à 2 nm. Enfin, un procédé utilisant la photolithographie UV conventionnelle a été développé pour réaliser le transistor de longueur de grille nanométrique. Ces dispositifs ont démontré d'excellentes performances électriques avec des courants de conduction supérieurs à 600 µA/µm et une excellente maîtrise des effets de canaux courts (pente sous le seuil de 95 mV/dec et DIBL à 25 mV/V) malgré l'extrême miniaturisation de la longueur de grille (15 nm). Enfin, nous présentons une première preuve de concept d'un inverseur CMOS à base de cette technologie à nanofils verticaux. / In order to further downscaling of the MOS transistors, the semiconductor industry has anticipated the limitations of miniaturization by the introduction of new materials and new architectures. The advent of triple gate structures (FinFET) allowed mastering the short channel effects and further miniaturization efforts (14 nm technology node in 2014). The ultimate case to the electrostatic control of the gate on the channel is given by a gate completely surrounding the device channel. For this purpose, Gate All Around (GAA) nanowire transistor is considered as the most suitable structure for technology nodes below 7 nm. In this thesis, a large scale process for the realization of miniaturized MOSFETs based on vertical silicon nanowires has been developed. Firstly, the vertical nanowires were made by a top down approach by the transfer by etching of hard mask made of Hydrogen silsesquioxane (HSQ) resist created at low voltage electron beam lithography. An original design strategy called "star" was developed to define perfectly circular nanowires. Si nanowires are obtained by plasma etching then thinned by sacrificial wet oxidation. This method allows obtaining vertical Si nanowires with perfectly anisotropic walls, a perfect reproducibility and a maximum yield. The implementation of the MOSFETs on the nanowire network was done by successive engineering of nanoscale thin films (conductive and dielectric). In this context, an innovative process for producing insulation layers in HSQ by controlled chemical etching showed excellent flatness associated with surface roughness of less than 2 nm. Finally, a method using conventional UV photolithography has been developed to achieve the nanometer gate length transistor. These devices have demonstrated excellent electrical performances with conduction currents superior than 600 µA/µm and excellent control of short channel effects (subthreshold slope of 95 mV/dec and DIBL of 25 mV/V) despite extreme miniaturization of the gate length (15 nm). Finally, we present a first proof of concept of a CMOS inverter based on vertical nanowires technology.

Single-walled carbon nanotubes (SWNTs) are ideal for use in nanoelectronic devices because of their high current density, mobility and subthreshold swing. However, assembly methods must be developed to reproducibly align all-semiconducting SWNTs at specific locations with individually addressable gates for future integrated circuits. We show high yield assembly of local-gated semiconducting SWNTs assembled via AC-dielectrophoresis (DEP). Using individual local gates and scaling the gate oxide shows faster switching behavior and lower power consumption. The devices were assembled by DEP between prefabricated Pd source and drain electrodes with a thin Al/Al2O3 gate in the middle, and the electrical characteristics were measured before anneal and after anneal. Detailed electron transport investigations on the devices show that 99% display good FET behavior, with an average threshold voltage of 1V, subthreshold swing as low as 140 mV/dec, and on/off current ratio as high as 8x105. Assembly yield can also be increased to 85% by considering devices where 2-5 SWNT bridge the gap between source and drain electrode. To examine the characteristics of devices bridged by more than one SWNT, similar electron transport measurements were taken for 35 devices with electrodes bridged by 2-3 SWNT and 13 devices connected by 4-5 SWNT. This high yield directed assembly of local-gated SWNT-FETs via DEP may facilitate large scale fabrication of CMOS compatible nanoelectronic devices.

<p>Since the discovery of graphene, two-dimensional (2D) materials have attracted broad interests for transistor applications due to their atomically thin nature. This thesis studies nano-transistors based on 2D materials for several novel applications, including tunneling transistors for low-power electronics and reconfigurable transistors for hardware security.</p><p>The first part of the thesis focuses on tunneling field-effect transistors (TFETs). Since the current injection in a conventional MOSFET depends on thermionic injection over a gate-controlled barrier, the subthreshold swing (SS) of MOSFET is fundamentally limited to 60 mV/dec at room temperature, hindering the supply voltage scaling of integrated circuits (ICs). Utilizing band-to-band tunneling (BTBT) as current injection mechanism, TFETs overcome the SS limit by filtering out the Fermi tail in the source and achieve steep-slope switching. However, existing demonstrations of TFETs are plagued by low on-currents and degraded SS, largely due to the large tunneling distances caused by non-scaled body thicknesses, making 2D materials a promising candidate as channel materials for TFETs. In this thesis, we demonstrate a prototype TFET based on black phosphorus (BP) adopting electrostatic doping that is tuned by multiple top-gates, which allows the device to be reconfigured into multiple operation modes. The band-to-band tunneling mechanism is further confirmed by source-doping-dependent and temperature-dependent measurements, and the performance improvement of BP TFETs with further body and oxide thicknesses scaling is projected by atomistic simulation. In addition, a vertical BP TFET with a large tunneling area is also demonstrated, and negative differential resistance (NDR) is observed in the device.</p><p>The second part of the thesis focuses on reconfigurable nano-transistors with tunable p- and n-type operations and the implementation of hardware security based on such transistors. Polymorphic gate has been proposed as a hardware security primitive to protect the intellectual property of ICs from reverse engineering, and its operation requires transistors that can be reconfigured between p-type and n-type. However, a traditional CMOS transistor relies on substitutional doping, and thus its polarity cannot be altered after the fabrication. By contrast, 2D nano-transistors can attain both electron and hole injections. In this thesis, we review the Schottky-barrier injection in 2D transistors and demonstrate the feasibility of achieving complementary p-type and n-type transistors using BP as channel material by adopting metal contacts with different work functions. In this design, however, the discrepancy in the p-FET and n-FET device structures makes it unsuitable for reconfigurable transistors. Therefore, we continue to modify the device design to enable reconfigurable p-type and n-type operations in the same BP transistor. Finally, a NAND/NOR polymorphic gate is experimentally demonstrated based on the reconfigurable BP transistors, showing the feasibility of using 2D materials to enable hardware security.</p><p>In the last part, we demonstrate an artificial sub-60 mV/dec switching in a metal-insulator-metal-insulator-semiconductor (MIMIS) transistor. Negative capacitance FETs (NC-FETs) have attracted wide interest as promising candidates for steep-slope devices. However, the detailed mechanisms of the observed steep-slope switching are under intense debate. We show that sub-60 mV/dec switching can be observed in a WS2 transistor with an MIMIS structure – without any ferroelectric component. Using a resistor-capacitor (RC) network model, we show that the observed steep-slope switching can be attributed to the internal gate voltage response to the chosen varying gate voltage scan rates. Our results indicate that the measurement-related artefacts can lead to observation of sub-60 mV/dec switching and that experimentalists need to critically assess their measurement setups.</p>

For graphene to be a viable platform for nanoscale devices, high quality growth and structures are necessary. This means structuring the SiC surface to prevent graphene from having to be patterned using standard microelectronic processes. Presented in this thesis are new processes aimed at improving the graphene as well as devices based on high quality graphene nanoribbons. Amorphous carbon (aC) corrals deposited prior to graphene growth are demonstrated to control SiC step-flow. SiC steps are shown to be aligned by the presence of the corrals and can increase SiC terrace widths. aC contacts deposited and crystallized during graphene growth are shown as a way to contact graphene without metal lift-off. Observation of the Quantum Hall Effect demonstrates the high quality of the graphene grown alongside the nanocrystalline graphite contacts. Continuing the ballistic transport measurements on sidewall graphene nanoribbons, the invasive probe effect is observed using an atomic force microscope (AFM) based technique that spatially maps the invasive probe effect. Cleaning experiments demonstrate the role of scattering due to resist residues and environmental adsorbates on graphene nanoribbons. Finally, switches based on junctions formed in the graphene nanoribbons are shown as a route toward graphene based devices.

The current trend towards miniaturization of modern consumer electronic devices significantly affects their design. The demand for efficient all-in-one appliances leads to smaller, yet more complex and powerful nanoelectronic devices. The increasing complexity in the design of such nanoscale Analog/Mixed-Signal Systems-on-Chip (AMS-SoCs) presents difficult challenges to designers. One promising design method used to mitigate the burden of this design effort is the use of metamodeling (surrogate) modeling techniques. Their use significantly reduces the time for computer simulation and design space exploration and optimization. This dissertation addresses several issues of metamodeling based nanoelectronic based AMS design exploration. A surrogate modeling technique which uses geostatistical based Kriging prediction methods in creating metamodels is proposed. Kriging prediction techniques take into account the correlation effects between input parameters for performance point prediction. We propose the use of Kriging to utilize this property for the accurate modeling of process variation effects of designs in the deep nanometer region. Different Kriging methods have been explored for this work such as simple and ordinary Kriging. We also propose another metamodeling technique Kriging-Bootstrapped Neural Network that combines the accuracy and process variation awareness of Kriging with artificial neural network models for ultra-fast and accurate process aware metamodeling design. The proposed methodologies combine Kriging metamodels with selected algorithms for ultra-fast layout optimization. The selected algorithms explored are: Gravitational Search Algorithm (GSA), Simulated Annealing Optimization (SAO), and Ant Colony Optimization (ACO). Experimental results demonstrate that the proposed Kriging metamodel based methodologies can perform the optimizations with minimal computational burden compared to traditional (SPICE-based) design flows.

Esta dissertação discute o desenvolvimento de modelos analíticos e numéricos para as características elétricas de transistores de fios quânticos. Sendo assim, realizou-se um estudo implementando uma sequência de formalismos e ferramentas computacionais para solução auto-consistente das equações de Schrödinger e Poisson para poços e fios quânticos. Com a utilização deste método numérico pode-se determinar os auto-estados os níveis de energias e as densidades eletrônicas de portadores livres, dentre outros parâmetros relevantes para dispositivos de fio quântico. Adicionalmente, realizou-se um estudo analítico das heteroestruturas semicondutoras de interesse para a área de dispositivos de dimensionalidade reduzida. Este estudo levou a obtenção de resultados referentes ao desenvolvimento de modelos teóricos para as características elétricas de dispositivos baseados no mecanismo de tunelamento ressonante. Os resultados obtidos para a característica corrente-tensão (I-V) nas heteroestruturas investigadas foram contrastados satisfatoriamente com os encontrados na literatura. Este ferramental analítico foi então aplicado para computar o coeficiente de transmissão eletrônico de um diodo de fio quântico com tunelamento ressonante. / This dissertation discusses the development of analytical and numerical models for the electrical characteristics of quantum wire transistors. A study is carried out, implementing a sequence of formalisms and computational tools for the self-consistent solution of the equations of Schrödinger and Poisson in quantum wells and quantum wires. By using this numerical formulation it is possible to determine the eigenstates, energy levels and free-carrier electronic density, among other relevant parameters for quantum wire devices. In addition, we also conducted an analytical study concerning semiconductor heetrostrucures of interest for reduced dimensionality devices applications. This study led to results regarding the development of theoretical models for the electrical characteristics of devices based on the resonant tunneling mechanism. The results obtained for the current-voltage (I-V) characteristics in the investigated heterostructures were satisfactorily compared to those available at the published literature and this analytical tool was then used to compute the electronic transmission coefficient in a resonant tunneling quantum wire diode.

This thesis introduces functional nanomaterials including superatoms and carbon nanotubes (CNTs) for new layered solids and molecular devices. Chapters 1-3 present how we incorporate superatoms into two-dimensional (2D) materials. Chapter 1 describes a new and simple approach to dope transition metal dichalcogenides (TMDCs) using the superatom Co6Se8(PEt3)6 as the electron dopant. Doping is an effective method to modulate the electrical properties of materials, and we demonstrate an electron-rich cluster can be used as a tunable and controllable surface dopant for semiconducting TMDCs via charge transfer. As a demonstration of the concept, we make a p-n junction by patterning on specific areas of TMDC films. Chapter 2 and Chapter 3 introduce new 2D materials by molecular design of superatoms. Traditional atomic van der Waals materials such as graphene, hexagonal boron-nitride, and TMDCs have received widespread attention due to the wealth of unusual physical and chemical behaviors that arise when charges, spins, and vibrations are confined to a plane. Though not as widespread as their atomic counterparts, molecule-based layered solids offer significant benefits; their structural flexibility will enable the development of materials with tunable properties. Chapter 2 describes a layered van der Waals solid self-assembled from a structure-directing building block and C60 fullerene. The resulting crystalline solid contains a corrugated monolayer of neutral fullerenes and can be mechanically exfoliated. Chapter 3 describes a new method to functionalize electroactive superatoms with groups that can direct their assembly into covalent and non-covalent multi-dimensional frameworks. We synthesized Co6Se8[PEt2(4-C6H4COOH)]6 and found that it forms two types of crystalline assemblies with Zn(NO3)2, one is a three-dimensional solid and the other consists of stacked layers of two-dimensional sheets. The dimensionality is controlled by subtle changes in reaction conditions. CNT-based field-effect transistor (FETs), in which a single molecule spans an oxidatively cut gap in the CNT, provide a versatile, ground-state platform with well-defined electrical contacts. For statistical studies of a variety of small molecule bridges, Chapter 4 presents a novel fabrication method to produce hundreds of FETs on one single carbon nanotube. A large number of devices allows us to study the stability and uniformity of CNT FET properties. Moreover, the new platform also enables a quantitative analysis of molecular devices. In particular, we used CNT FETs for studying DNA-mediated charge transport. DNA conductance was measured by connecting DNA molecules of varying lengths to lithographically cut CNT FETs.

Due to its truly two dimensional (2D) character and its particular lattice, single layer graphene (SLG) possesses exceptional properties: it is semimetallic, transparent, strong yet flexible ... Complementary features such as the insulating character of hexagonal boron nitride (h-BN) and semiconducting properties of transition metal dichalcogenides (TMDs) enable the whole spectrum of electronic devices to be built with combinations of these 2D materials. Due to this and the ease of exfoliation with a sticky tape, a vast amount of research was sparked. The mechanical exfoliation method, however, is only suitable for novel or proof-of-concept devices. The trend nowadays in electronics is towards transparent, lightweight, flexible, embedded smart devices and sensors in everyday objects such as windows and mirrors, garments, windshields, car seats, parachutes...These demands are already met inherently by these new materials, thus the challenges remaining are within their synthesis, deposition and processing, where more scalable ways of production and device fabrication need to be developed. This thesis explores innovative approaches using established techniques that aim to bridge the gap between proof-of-concept devices and real applications of 2D materials in future commercial level technologies. Methods to create graphene and engineer its properties are employed with a special focus on scalability and adaptability towards the industry. These graphene materials have been processed using pioneering schemes to create different optoelectronic devices and sensors. The techniques employed here for synthesis, transfer and deposition, device processing and characterization of graphene and derivatives, are suitable for their use in large manufacturing and mass-production. Depending on the application envisaged, different materials are used and optimize in order to balance good performance, cost-effectiveness and suitability/scalability of the process for the specific target the device was designed for.

This work examines the deposition of metallic and semiconductor elements onto self-assembled DNA templates for the fabrication of nanodevices. Biological molecules like DNA can self-assemble into a variety of complex 2-D and 3-D architectures without the need for expensive patterning tools. In addition, self-assembled DNA templates can be designed to controllably place functional nanomaterials with molecular precision. These characteristics make DNA an attractive template for fabricating electronic circuits from biological molecules. However, electrically conductive structures are required for electronic applications. While metallized DNA nanostructures have been demonstrated, the ability to make thin, continuous wires that are electrically conductive still represents a formidable challenge. DNA-templated wires have generally been granular in appearance with a resistivity approximately two to three orders of magnitude higher than that of the bulk material. An improved method for the metallization of DNA origami is examined in this work that addresses these challenges of size, morphology and conductivity of the metallized structure. Specifically, we demonstrated a metallization process that uses gold nanorod seeds followed by anisotropic electroless (autocatalytic) plating to provide improved morphology and greater control of the final metallized width of conducting metal lines. Importantly, growth during electroless deposition occurs preferentially in the length direction at a rate that is approximately four times the growth rate in the width direction, which enables fabrication of narrow, continuous wires. The electrical properties of 49 nanowires with widths ranging from 13 nm to 29 nm were characterized, and resistivity values as low as 8.9 x 10-7 Ω-m were measured, which represent some of the smallest nanowires and the lowest resistivity values reported in the literature. The metallization procedure developed on smaller templates was also successfully applied to metallize bigger DNA templates of tens of micrometers in length. In addition, a polymer-assisted annealing process was discovered to possibly improve the resistivity of DNA metal nanowires. Following metallization of bigger DNA origami structures, controlled placement of gold nanorods on a DNA breadboard (~100 x 100 nm2) to make rectangular, square and T-shaped metallic structures was also demonstrated. For site-specific placement of nanorods to a DNA template, we modified the surface of the gold nanorods with single-stranded DNA. The rods were then attached to DNA templates via complementary base-pairing between the DNA on the nanorods and the attachment strands engineered into the DNA "breadboard" template. Gaps between the nanorods were then filled controllably via anisotropic plating to make 10 nm diameter continuous metallic structures. Finally, controlled placement of metal (gold) - semiconductor (tellurium) materials on a single DNA origami template was demonstrated as another important step toward the fabrication of DNA-based electronic components. The combination of molecularly directed deposition and anisotropic metallization presented in this work represents important progress towards the creation of nanoelectronic devices from self-assembled biological templates.