L'allègement des structures est un enjeu économique important dans les domaines d'activités industrielles telles que l'automobile, l'aéronautique ou le naval, qui intègrent peu à peu les matériaux composites dans la fabrication des structures. Cet allègement s'accompagne d'un raidissement de la matière qui implique des problèmes de vibrations et d'isolation acoustique. Plusieurs méthodes de traitement existent pour diminuer les vibrations ou le bruit rayonné d'une paroi, mais ces méthodes ont l'inconvénient d'augmenter significativement la masse de la paroi. Afin de répondre à cette problématique, il est proposé dans cette thèse de modifier le comportement dynamique des structures à partir d'un réseau périodique de patchs piézoélectriques shuntés avec un circuit électrique dont il est possible de modifier l'impédance. En contrôlant ainsi le comportement dynamique des patchs piézoélectriques, il est possible de contrôler le comportement vibratoire de la structure et donc de traiter les problèmes de transmissions solidiennes ou de transmissions aériennes.La méthode de shunt choisie est la méthode dite de shunt à capacité négative qui permet de modifier la rigidité d'une structure. Cette méthode dite semi-passive présente plusieurs avantages : la mise en œuvre est simple, il est possible d'intégrer les patchs directement à l'intérieur de la paroi, elle consomme une faible quantité d'énergie électrique et sa mise en application est peu onéreuse. / Making the structure lighter is an important economic stake in the field of industrial activities such as automotive, aeronautic or naval, which gradually integrate composite materials in the manufacturing of structures. This reduction of the mass goes along with a stiffening of the matter implying acoustics and vibrations issues. Several methods exist to reduce vibrations or acoustic radiations of structures, but these methods increase the mass. In order to answer the problematic, we propose to change the dynamic behavior of structures with a periodic lattice of piezoelectric patches shunted with an electrical circuit whose the impedance can be controlled. Therefore, the control of the coupled behavior of the piezoelectric patches allows the control of vibrational wave's diffusion inside the structure and so to treat the structure-borne vibrations and airborne acoustics emission. The shunt method chosen is negative capacitance shunt which allows to modify the rigidity of a structure. This semi-passive method has several advantages: the implementation is simple, it is possible to integrate the patches directly inside the wall, it consumes a low amonte of electrical energy and its implementation is inexpensive.

<p>To sustain the upcoming paradigm shift in computations technology efficiently, innovative solutions at the lowest level of the computing hierarchy (the material and device level) are essential to delivering the required functionalities beyond what is available with current CMOS platforms. Motivated by this, in this dissertation, we explore ferroelectric-based devices for steep-slope logic and energy-efficient non-volatile-memory functionalities signifying the novel device attributes, possibilities for continual dimensional scaling with the much-needed enhancement in performance.</p> <p> </p> <p>Among various ferroelectric (FE) materials, Zr doped HfO₂ (HZO) has gained immense research attention in recent times by virtue of CMOS process compatibility and a considerable amount of ferroelectricity at room temperature. In this work, we investigate the Zr concentration-dependent crystal phase transition of Hf_1-xZ_xO₂ (HZO) and the corresponding evolution of dielectric, ferroelectric, and anti-ferroelectric characteristics. Providing the microscopic insights of strain-induced crystal phase transformations, we propose a physics-based model that shows good agreement with experimental results for 10 nm Hf_1-xZ_xO₂. Further, in a heterogeneous system, ferroelectric materials can exhibit negative capacitance (NC) behavior. Such NC effects may lead to differential amplification in local potential and can provide an enhanced charge and capacitance response for the whole system compared to their constituents. Such intriguing implications of NC phenomena have prompted the design and exploration of many ferroelectric-based electronic devices to not only achieve an improved performance but potentially also overcome some fundamental limits of standard transistors. However, the microscopic physical origin as well as the true nature of the NC effect, and direct experimental evidence remain elusive and debatable. To that end, in this work, we systematically investigate the underlying physical mechanism of the NC effect in the ferroelectric material. Based upon the fundamental physics of ferroelectric material, we investigate different assumptions, conditions, and distinct features of the quasi-static NC effect in the single-domain and multi-domain scenarios. While the quasi-static and hysteresis-free NC effect was initially propounded in the context of a single-domain scenario, we highlight that the similar effects can be observed in multi-domain FEs with soft domain-wall (DW) displacement. Furthermore, to obtain the soft-DW, the gradient energy coefficient of the FE material is required to be higher as well as the ferroelectric thickness is required to be lower than some critical values. Otherwise, the DW becomes hard, and their displacement would lead to hysteretic NC effects. In addition to the quasi-static NC, we discuss different mechanisms that can lead to the transient NC effects. Furthermore, we provide guidelines for new experiments that can potentially provide new insights on unveiling the real origin of NC phenomena.</p> <p> </p> <p>Utilizing such ferroelectric insulators at the gate stack of a transistor, ferroelectric-field-effect transistors (FeFETs) have been demonstrated to exhibit both non-volatile memory and steep-slope logic functionalities. To investigate such diverse attributes and to enable application drive optimization of FeFETs, we develop a phase-field simulation framework of FeFETs by self-consistently solving the time-dependent Ginzburg-Landau (TDGL) equation, Poisson’s equation, and non-equilibrium Green’s function (NEGF) based semiconductor charge-transport equation. Considering HZO as the FE layer, we first analyze the dependence of the multi-domain patterns on the HZO thickness (<i>T_FE</i>) and their critical role in dictating the steep-switching (both in the negative and positive capacitance regimes) and non-volatile characteristics of FeFETs. In particular, we analyze the <i>T_FE</i>-dependent formation of hard and soft domain-walls (DW). We show that, <i>T_FE</i> scaling first leads to an increase in the domain density in the hard DW-regime, followed by soft DW formation and finally polarization collapse. For hard-DWs, we describe the polarization switching mechanisms and how the domain density impacts key parameters such as coercive voltage, remanent polarization, effective permittivity and memory window. We also discuss the enhanced but positive permittivity effects in densely pattern multi-domain states in the absence of hard-DW displacement and its implication in non-hysteretic attributes of FeFETs. For soft-DWs, we present how DW-displacement can lead to effective negative capacitance in FeFETs, resulting in a steeper switching slope and superior scalability. In addition, we also develop a Preisach based circuit compatible model for FeFET (and antiferroelectric-FET) that captures the multi-domain polarization switching effects in the FE layer. </p> <p> </p> Unlike semiconductor insulators (e.g., HZO), there are ferroelectric materials that exhibit a considerably low bandgap (< 2eV) and hence, display semiconducting properties. In this regard, non-perovskite-based 2D ferroelectric -In₂Se₃ shows a bandgap of ~1.4eV and that suggests a combined ferroelectricity and semiconductivity in the same material system. As part of this work, we explore the modeling and operational principle of ferroelectric semiconductor metal junction (FeSMJ) based devices in the context of non-volatile memory (NVM) application. First, we analyze the semiconducting and ferroelectric properties of the α-In₂Se₃ van der Waals (vdW) stack via experimental characterization and first-principles simulations. Then, we develop a FeSMJ device simulation framework by self-consistently solving the Landau–Ginzburg–Devonshire equation, Poisson's equation, and charge-transport equations. Our simulation results show good agreement with the experimental characteristics of α-In₂Se₃-based FeSMJ suggesting that the FeS polarization-dependent modulation of Schottky barrier heights of FeSMJ plays a key role in providing the NVM functionality. Moreover, we show that the thickness scaling of FeS leads to a reduction in read/write voltage and an increase in distinguishability. Array-level analysis of FeSMJ NVM suggests a lower read-time and read-write energy with respect to the HfO₂-based ferroelectric insulator tunnel junction (FTJ) signifying its potential for energy-efficient and high-density NVM applications.

A need for high bandwidth operational amplifiers, or op-amps, exists for certain applications. This need requires research in the area of op-amp bandwidth extension. The proposed method of this thesis uses Negative Capacitance Generation (NCG), which involves using the Miller effect to generate an equivalent negative capacitance at a given node in a circuit, to extend the bandwidth of an op-amp. This is accomplished by first applying NCG to the second stage of an op-amp, in which the op-amp has been compensated using Single Capacitor Miller Compensation (SCMC). Next, the Miller capacitor used to compensate the op-amp can be reduced and thus, the bandwidth of the op-amp is extended. The proposed method employed a 100dB, classic two-stage op-amp with a 7.7MHz gain-bandwidth product (GBW). It was discovered that after applying NCG to several places in the op-amp besides the second stage that the GBW was roughly doubled. The GBW of the second stage was improved by a factor of 9.3. This discrepancy in GBW improvements was researched and certain barriers were discovered. Although the barriers were not eliminated, research in overcoming them and obtaining greater improvements in op-amp bandwidth is encouraging.

Submitted by Kilvya Braga (kilvyabraga@hotmail.com) on 2018-04-26T13:55:49Z No. of bitstreams: 1 ALAN GONÇALVES PAULO E SILVA - DISSERTAÇÃO (PPGEM) 2016.pdf: 4036442 bytes, checksum: 66c4a790f1155d8ce09ccc484d739542 (MD5) / Made available in DSpace on 2018-04-26T13:55:49Z (GMT). No. of bitstreams: 1 ALAN GONÇALVES PAULO E SILVA - DISSERTAÇÃO (PPGEM) 2016.pdf: 4036442 bytes, checksum: 66c4a790f1155d8ce09ccc484d739542 (MD5) Previous issue date: 2016-02-04 / Capes / A necessidade de controle ou supressão das vibrações surgiu devido aos seus efeitos danosos causados as pessoas, estruturas e elementos de máquinas. Com o passar dos anos, várias técnicas de controle foram criadas e se desenvolvem à medida que a tecnologia avança. Hoje, a utilização de materiais funcionais ou inteligentes, já é utilizada em larga escala em aplicações práticas e nas pesquisas acadêmicas dos maiores centros de tecnologia do mundo. Neste trabalho, temos como objetivo, realizar o controle de vibrações de uma estrutura com dois graus de liberdade do tipo pórtico, utilizando transdutores piezoelétricos associados a circuitos do tipo shunt de capacitância negativa com resistência elétrica em série. Para tal, utilizamos um circuito eletroeletrônico com componentes passivos (resistores, capacitores, indutores) associados a transdutores piezoelétricos QP10W, para produzirmos o circuito shunt de capacitância negativa, implementado através de Conversores de Impedância Negativa (NIC), utilizando amplificadores operacionais. As amplitudes de resposta do sistema nos domínios do tempo e frequência foram analisadas em vibração livre e em vibração forçada, utilizando os resistores que obtiveram o melhor desempenho na dissipação de energia da estrutura, que foram os de 100 Ω e de 150 kΩ. Obtivemos uma redução de 9,01 dB para o primeiro pico de frequência e de 6,95 dB para o segundo pico, em vibração livre. Para o caso de vibração forçada, obtivemos uma redução de 1,5 dB para o primeiro pico de frequência e de 2,19 dB para o segundo pico de frequência, cumprindo assim o objetivo do trabalho pretendido. / The need for control or suppression of vibrations arose due to its harmful effects caused at people, structures and machine elements. With the passage of years, various control techniques were created and develop as technology advance. Today, the use of functional or smart materials is already used on a large scale in practical applications and in academic research of the world's largest technology centers. In this work, our goal is to perform vibration control of a structure with two degrees of freedom portico type using piezoelectric transducers associated with the negative capacitance shunt circuits with electric resistance in series. To do this, we use an electroelectronics circuit with passive components (resistors, capacitors, inductors) associated with piezoelectric transducers QP10W, to produce the negative capacitance shunt circuit, implemented through Negative Impedance Converters (NIC) using operational amplifiers. Response amplitudes of the system in the domains of time and frequency were analyzed in free vibration and forced vibration using the resistors that had the best performance in energy dissipation structure, which were the 100 Ω and 150 kΩ. We obtained a reduction of 9.01 dB for the first peak frequency and 6.95 dB for the second peak in vibration free. In the case of forced vibration, we obtained a reduction of 1.5 dB for the first peak frequency and 2.19 dB for the second peak frequency, thus fulfilling the purpose of the intended work.

No description available.

<p align="justify">Many different active control techniques can be used to control the vibrations of a mechanical structure: they however require at least a sensitive signal amplifier (for the sensor), a power amplifier (for the actuator) and an analog or digital filter (for the controller). The use of all these electronic devices may be impractical in many applications and has motivated the use of the so-called shunt circuits, in which an electrical circuit is directly connected to a transducer embedded in the structure. The transducer acts as an energy converter: it transforms mechanical (vibrational) energy into electrical energy, which is in turn dissipated in the shunt circuit. No separate sensor is required, and only one, generally simple electronic circuit is used. The stability of the shunted structure is guaranteed if the electric circuit is passive, i.e., if it is made of passive components such as resistors and inductors.</p> <p align="justify">This thesis compares the performances of the electric shunt circuits with those of classical active control systems. It successively considers the use of piezoelectric transducers and that of electromagnetic (moving-coil) transducers.</p> <p align="justify">In a first part, the different damping techniques are applied on a benchmark truss structure equipped with a piezoelectric stack transducer. A unified formulation is found and experimentally verified for an active control law, the Integral Force Feedback (IFF), and for various passive shunt circuits (resistive and resistive-inductive). The use of an active shunt, namely the negative capacitance, is also investigated in detail. Two different implementations are discussed: they are shown to have very different stability limits and performances.</p> <p align="justify">In a second part, vibration isolation with electromagnetic (moving-coil) transducers is introduced. The effects of an inductive-resistive shunt circuit are studied in detail; an equivalent mechanical representation is found. The performances are compared with that of resonant shunts and with that of active isolation with IFF. Next, the construction of a six-axis isolator based on a Stewart Platform is presented: the key parameters and the main limitations of the system are highlighted.</p>

Capacitance-voltage-frequency measurements on n+-GaN/AlxGa1−xN UV/IR dual-band detectors are reported. The presence of shallow Si-donor, deep Si-donor, and C-donor/N-vacancy defect states were found to significantly alter the electrical characteristics of the detectors. The barrier Al fraction was found to change the position of the interface defect states relative to the Fermi level. The sample with Al fraction of 0.1 shows a distinct capacitance-step and hysteresis, which is attributed to C-donor/N-vacancy electron trap states located above the Fermi level (200 meV) at the heterointerface; whereas, the sample with Al fraction of 0.026 shows negative capacitance and dispersion, indicating C-donor/N-vacancy and deep Si-donor defect states located below the Fermi level (88 meV). When an i-GaN buffer layer was added to the structure, an anomalous high-frequency capacitance peak was observed and attributed to resonance scattering due to hybridization of localized Si-donor states in the band gap with conduction band states at the i-GaN/n+-GaN interface.

The nano-age has already begun, where typical feature dimensions are smaller than 100nm. The operating frequency is expected to increase up to 12 GHz, and a single chip will contain over 12 billion transistors in 2020, as given by the International Technology Roadmap for Semiconductors (ITRS) initiative. ITRS also predicts that the scaling of CMOS devices and process technology, as it is known today, will become much more difficult as the industry advances towards the 16nm technology node and further. This aggressive scaling of CMOS technology has pushed the devices to their physical limits. Design goals are governed by several factors other than power, performance and area such as process variations, radiation induced soft errors, and aging degradation mechanisms. These new design challenges have a strong impact on the parametric yield of nanometer digital circuits and also result in functional yield losses in variation-sensitive digital circuits such as Static Random Access Memory (SRAM) and flip-flops. Moreover, sub-threshold SRAM and flip-flops circuits, which are aggravated by the strong demand for lower power consumption, show larger sensitivity to these challenges which reduces their robustness and yield. Accordingly, it is not surprising that the ITRS considers variability and reliability as the most challenging obstacles for nanometer digital circuits robust design. Soft errors are considered one of the main reliability and robustness concerns in SRAM arrays in sub-100nm technologies due to low operating voltage, small node capacitance, and high packing density. The SRAM arrays soft errors immunity is also affected by process variations. We develop statistical design-oriented soft errors immunity variations models for super-threshold and sub-threshold SRAM cells accounting for die-to-die variations and within-die variations. This work provides new design insights and highlights the important design knobs that can be used to reduce the SRAM cells soft errors immunity variations. The developed models are scalable, bias dependent, and only require the knowledge of easily measurable parameters. This makes them useful in early design exploration, circuit optimization as well as technology prediction. The derived models are verified using Monte Carlo SPICE simulations, referring to an industrial hardware-calibrated 65nm CMOS technology. The demand for higher performance leads to very deep pipelining which means that hundreds of thousands of flip-flops are required to control the data flow under strict timing constraints. A violation of the timing constraints at a flip-flop can result in latching incorrect data causing the overall system to malfunction. In addition, the flip-flops power dissipation represents a considerable fraction of the total power dissipation. Sub-threshold flip-flops are considered the most energy efficient solution for low power applications in which, performance is of secondary importance. Accordingly, statistical gate sizing is conducted to different flip-flops topologies for timing yield improvement of super-threshold flip-flops and power yield improvement of sub-threshold flip-flops. Following that, a comparative analysis between these flip-flops topologies considering the required overhead for yield improvement is performed. This comparative analysis provides useful recommendations that help flip-flops designers on selecting the best flip-flops topology that satisfies their system specifications while taking the process variations impact and robustness requirements into account. Adaptive Body Bias (ABB) allows the tuning of the transistor threshold voltage, Vt, by controlling the transistor body voltage. A forward body bias reduces Vt, increasing the device speed at the expense of increased leakage power. Alternatively, a reverse body bias increases Vt, reducing the leakage power but slowing the device. Therefore, the impact of process variations is mitigated by speeding up slow and less leaky devices or slowing down devices that are fast and highly leaky. Practically, the implementation of the ABB is desirable to bias each device in a design independently, to mitigate within-die variations. However, supplying so many separate voltages inside a die results in a large area overhead. On the other hand, using the same body bias for all devices on the same die limits its capability to compensate for within-die variations. Thus, the granularity level of the ABB scheme is a trade-off between the within-die variations compensation capability and the associated area overhead. This work introduces new ABB circuits that exhibit lower area overhead by a factor of 143X than that of previous ABB circuits. In addition, these ABB circuits are resolution free since no digital-to-analog converters or analog-to-digital converters are required on their implementations. These ABB circuits are adopted to high performance critical paths, emulating a real microprocessor architecture, for process variations compensation and also adopted to SRAM arrays, for Negative Bias Temperature Instability (NBTI) aging and process variations compensation. The effectiveness of the new ABB circuits is verified by post layout simulation results and test chip measurements using triple-well 65nm CMOS technology. The highly capacitive nodes of wide fan-in dynamic circuits and SRAM bitlines limit the performance of these circuits. In addition, process variations mitigation by statistical gate sizing increases this capacitance further and fails in achieving the target yield improvement. We propose new negative capacitance circuits that reduce the overall parasitic capacitance of these highly capacitive nodes. These negative capacitance circuits are adopted to wide fan-in dynamic circuits for timing yield improvement up to 99.87% and to SRAM arrays for read access yield improvement up to 100%. The area and power overheads of these new negative capacitance circuits are amortized over the large die area of the microprocessor and the SRAM array. The effectiveness of the new negative capacitance circuits is verified by post layout simulation results and test chip measurements using 65nm CMOS technology.

The nano-age has already begun, where typical feature dimensions are smaller than 100nm. The operating frequency is expected to increase up to 12 GHz, and a single chip will contain over 12 billion transistors in 2020, as given by the International Technology Roadmap for Semiconductors (ITRS) initiative. ITRS also predicts that the scaling of CMOS devices and process technology, as it is known today, will become much more difficult as the industry advances towards the 16nm technology node and further. This aggressive scaling of CMOS technology has pushed the devices to their physical limits. Design goals are governed by several factors other than power, performance and area such as process variations, radiation induced soft errors, and aging degradation mechanisms. These new design challenges have a strong impact on the parametric yield of nanometer digital circuits and also result in functional yield losses in variation-sensitive digital circuits such as Static Random Access Memory (SRAM) and flip-flops. Moreover, sub-threshold SRAM and flip-flops circuits, which are aggravated by the strong demand for lower power consumption, show larger sensitivity to these challenges which reduces their robustness and yield. Accordingly, it is not surprising that the ITRS considers variability and reliability as the most challenging obstacles for nanometer digital circuits robust design. Soft errors are considered one of the main reliability and robustness concerns in SRAM arrays in sub-100nm technologies due to low operating voltage, small node capacitance, and high packing density. The SRAM arrays soft errors immunity is also affected by process variations. We develop statistical design-oriented soft errors immunity variations models for super-threshold and sub-threshold SRAM cells accounting for die-to-die variations and within-die variations. This work provides new design insights and highlights the important design knobs that can be used to reduce the SRAM cells soft errors immunity variations. The developed models are scalable, bias dependent, and only require the knowledge of easily measurable parameters. This makes them useful in early design exploration, circuit optimization as well as technology prediction. The derived models are verified using Monte Carlo SPICE simulations, referring to an industrial hardware-calibrated 65nm CMOS technology. The demand for higher performance leads to very deep pipelining which means that hundreds of thousands of flip-flops are required to control the data flow under strict timing constraints. A violation of the timing constraints at a flip-flop can result in latching incorrect data causing the overall system to malfunction. In addition, the flip-flops power dissipation represents a considerable fraction of the total power dissipation. Sub-threshold flip-flops are considered the most energy efficient solution for low power applications in which, performance is of secondary importance. Accordingly, statistical gate sizing is conducted to different flip-flops topologies for timing yield improvement of super-threshold flip-flops and power yield improvement of sub-threshold flip-flops. Following that, a comparative analysis between these flip-flops topologies considering the required overhead for yield improvement is performed. This comparative analysis provides useful recommendations that help flip-flops designers on selecting the best flip-flops topology that satisfies their system specifications while taking the process variations impact and robustness requirements into account. Adaptive Body Bias (ABB) allows the tuning of the transistor threshold voltage, Vt, by controlling the transistor body voltage. A forward body bias reduces Vt, increasing the device speed at the expense of increased leakage power. Alternatively, a reverse body bias increases Vt, reducing the leakage power but slowing the device. Therefore, the impact of process variations is mitigated by speeding up slow and less leaky devices or slowing down devices that are fast and highly leaky. Practically, the implementation of the ABB is desirable to bias each device in a design independently, to mitigate within-die variations. However, supplying so many separate voltages inside a die results in a large area overhead. On the other hand, using the same body bias for all devices on the same die limits its capability to compensate for within-die variations. Thus, the granularity level of the ABB scheme is a trade-off between the within-die variations compensation capability and the associated area overhead. This work introduces new ABB circuits that exhibit lower area overhead by a factor of 143X than that of previous ABB circuits. In addition, these ABB circuits are resolution free since no digital-to-analog converters or analog-to-digital converters are required on their implementations. These ABB circuits are adopted to high performance critical paths, emulating a real microprocessor architecture, for process variations compensation and also adopted to SRAM arrays, for Negative Bias Temperature Instability (NBTI) aging and process variations compensation. The effectiveness of the new ABB circuits is verified by post layout simulation results and test chip measurements using triple-well 65nm CMOS technology. The highly capacitive nodes of wide fan-in dynamic circuits and SRAM bitlines limit the performance of these circuits. In addition, process variations mitigation by statistical gate sizing increases this capacitance further and fails in achieving the target yield improvement. We propose new negative capacitance circuits that reduce the overall parasitic capacitance of these highly capacitive nodes. These negative capacitance circuits are adopted to wide fan-in dynamic circuits for timing yield improvement up to 99.87% and to SRAM arrays for read access yield improvement up to 100%. The area and power overheads of these new negative capacitance circuits are amortized over the large die area of the microprocessor and the SRAM array. The effectiveness of the new negative capacitance circuits is verified by post layout simulation results and test chip measurements using 65nm CMOS technology.

The properties of ferroelectric materials, which were discovered almost a century ago¹ , have led to a huge range of applications, such as digital information storage² , pyroelectric energy conversion³ and neuromorphic computing⁴⁻⁵ . Recently, it was shown that ferroelectrics can have negative capacitance⁶⁻¹¹, which could improve the energy efficiency of conventional electronics beyond fundamental limits¹²⁻¹⁴. In Landau–Ginzburg–Devonshire theory¹⁵⁻¹⁷, this negative capacitance is directly related to the doublewell shape of the ferroelectric polarization–energy landscape, which was thought for more than 70 years to be inaccessible to experiments¹⁸. Here we report electrical measurements of the intrinsic double-well energy landscape in a thin layer of ferroelectric Hf₀.₅Zr₀.₅O₂. To achieve this, we integrated the ferroelectric into a heterostructure capacitor with a second dielectric layer to prevent immediate screening of polarization charges during switching. These results show that negative capacitance has its origin in the energy barrier in a double-well landscape. Furthermore, we demonstrate that ferroelectric negative capacitance can be fast and hysteresis-free, which is important for prospective applications¹⁹. In addition, the Hf₀.₅Zr₀.₅O₂ used in this work is currently the most industry-relevant ferroelectric material, because both HfO₂ and ZrO₂ thin films are already used in everyday electronics²⁰. This could lead to fast adoption of negative capacitance effects in future products with markedly improved energy efficiency.