<p>Spiking Neural Networks (SNNs) have recently attracted significant research interest as the third generation of artificial neural networks that can enable low-power event-driven data analytics. We propose ANN-SNN conversion using “soft re-set” spiking neuron model, referred to as Residual Membrane Potential (RMP) spiking neuron, which retains the “resid- ual” membrane potential above threshold at the firing instants. In addition, we propose a time-based coding scheme, named Temporal-Switch-Coding (TSC), and a corresponding TSC spiking neuron model. Each input image pixel is presented using two spikes with opposite polarity and the timing between the two spiking instants is proportional to the pixel intensity. We demonstrate near loss-less ANN-SNN conversion using RMP neurons for VGG-16, ResNet-20, and ResNet-34 SNNs on challenging datasets including CIFAR-10, CIFAR-100, and ImageNet. With the help of TSC coding, it achieves 7-14.5× less inference latency, and 30-60× fewer addition operations and memory accesses per inference across datasets compared to the state of the art (SOTA) SNN models. In the second part of the thesis, we propose a new type of recurrent neural network (RNN) architecture, named Os- cillatory Fourier Neural Network (O-FNN). We demonstrate that O-FNN is mathematically equivalent to a simplified form of Discrete Fourier Transform applied onto periodical activa- tion. In particular, the computationally intensive back-propagation through time in training is eliminated, leading to faster training while achieving the SOTA inference accuracy in a diverse group of sequential tasks. For instance, applying the proposed model to sentiment analysis on IMDB review dataset reaches 89.4% test accuracy within 5 epochs, accompanied by over 35x reduction in the model size compared to Long Short-Term Memory (LSTM). The proposed novel RNN architecture is well poised for intelligent sequential processing in resource constrained hardware.</p>

<div>Machine Learning (ML) workloads, being memory and compute-intensive, consume large amounts of power running on conventional computing systems, restricting their implementations to large-scale data centers. Thus, there is a need for building domain-specific hardware primitives for energy-efficient ML processing at the edge. One such approach is in-memory computing, which eliminates frequent and unnecessary data-transfers between the memory and the compute units, by directly computing the data where it is stored. Most of the chip area is consumed by on-chip SRAMs in both conventional von-Neumann systems (e.g. CPU/GPU) as well as application-specific ICs (e.g. TPU). Thus, we propose various circuit techniques to enable a range of computations such as bitwise Boolean and arithmetic computations, binary convolution operations, non-Boolean dot-product operations, lookup-table based computations, and spiking neural network implementation - all within standard SRAM memory arrays.</div><div><br></div><div>First, we propose X-SRAM, where, by using skewed sense amplifiers, bitwise Boolean operations such as NAND/NOR/XOR/IMP etc. can be enabled within 6T and 8T SRAM arrays. Moreover, exploiting the decoupled read/write ports in 8T SRAMs, we propose read-compute-store scheme where the computed data can directly be written back in the array simultaneously. </div><div><br></div><div>Second, we propose Xcel-RAM, where we show how binary convolutions can be enabled in 10T SRAM arrays for accelerating binary neural networks. We present charge sharing approach for performing XNOR operations followed by a population count (popcount) using both analog and digital techniques, highlighting the accuracy-energy tradeoff. </div><div><br></div><div>Third, we take this concept further and propose CASH-RAM, to accelerate non-Boolean operations, such as dot-products within standard 8T-SRAM arrays by utilizing the parasitic capacitances of bitlines and sourcelines. We analyze the non-idealities that arise due to analog computations and propose a self-compensation technique which reduces the effects of non-idealities, thereby reducing the errors. </div><div><br></div><div>Fourth, we propose ROM-embedded caches, RECache, using standard 8T SRAMs, useful for lookup-table (LUT) based computations. We show that just by adding an extra word-line (WL) or a source-line (SL), the same bit-cell can store a ROM bit, as well as the usual RAM bit, while maintaining the performance and area-efficiency, thereby doubling the memory density. Further we propose SPARE, an in-memory, distributed processing architecture built on RECache, for accelerating spiking neural networks (SNNs), which often require high-order polynomials and transcendental functions for solving complex neuro-synaptic models. </div><div><br></div><div>Finally, we propose IMPULSE, a 10T-SRAM compute-in-memory (CIM) macro, specifically designed for state-of-the-art SNN inference. The inherent dynamics of the neuron membrane potential in SNNs allows processing of sequential learning tasks, avoiding the complexity of recurrent neural networks. The highly-sparse spike-based computations in such spatio-temporal data can be leveraged for energy-efficiency. However, the membrane potential incurs additional memory access bottlenecks in current SNN hardware. IMPULSE triew to tackle the above challenges. It consists of a fused weight (WMEM) and membrane potential (VMEM) memory and inherently exploits sparsity in input spikes. We propose staggered data mapping and re-configurable peripherals for handling different bit-precision requirements of WMEM and VMEM, while supporting multiple neuron functionalities. The proposed macro was fabricated in 65nm CMOS technology. We demonstrate a sentiment classification task from the IMDB dataset of movie reviews and show that the SNN achieves competitive accuracy with only a fraction of trainable parameters and effective operations compared to an LSTM network.</div><div><br></div><div>These circuit explorations to embed computations in standard memory structures shows that on-chip SRAMs can do much more than just store data and can be re-purposed as on-demand accelerators for a variety of applications. </div>

In recent years, neural networks have seen increased interest from both the cognitive computing and computation neuroscience fields. Neuromorphic computing systems simulate neural network efficiently, but have not yet reached the amount of neurons that a mammal has. Increasing this quantity is an aspiration, but more neurons will also increase the traffic load of the system. The placement of the neurons onto the neuromorphic computing system has a significant effect on the network load. This thesis introduces algorithms for placing a large amount of neurons in an efficient and agile way. First, an analysis of placement algorithms for very large scale integration design is done, displaying that computing complexity of these algorithms is high. When using the predefined underlying structure of the neural network, more rapid algorithms can be used. The results show that the population placement algorithm has high computing speed as well as providing exceptional result.

<p>With the Moore’s Law era coming to an end, much attention has been given to novel nanoelectronic devices as a key driving force behind technological innovation. Utilizing the inherent device physics of nanoelectronic components, for sensory and computational tasks have proven to be useful in reducing the area and energy requirements of the underlying hardware fabrics. In this work we demonstrate how the intrinsic noise present in nano magnetic devices can pave the pathway for energy efficient neuromorphic hardware. Furthermore, we illustrate how the unique magnetic properties of such devices can be leveraged for accurate estimation of environmental magnetic fields. We focus on spintronic technologies in particular, due to the low current and energy requirements in contrast to traditional CMOS technologies.</p><p>Image segmentation is a crucial pre-processing stage used in many object identification tasks that involves simplifying the representation of an image so it can be conveniently analyzed in the later stages of a problem. This is achieved through partitioning a complicated image into specific groups based on color, intensity or texture of the pixels of that image. Locally Excitatory Globally Inhibitory Oscillator Network or LEGION is one such segmentation algorithm, where synchronization and desynchronization between coupled oscillators are used for segmenting an image. In this work we present an energy efficient and scalable hardware implementation of LEGION using stochastic Magnetic Tunnel Junctions that leverage the fast parallel</p><p> nature of the algorithm. We demonstrate that the proposed hardware is capable of segmenting binary and gray-scale images with multiple objects more efficiently than<br> existing hardware implementations. </p><p>It is understood that the underlying device physics of spin devices can be used for emulating the functionality of a spiking neuron. Stochastic spiking neural networks based on nanoelectronic spin devices can be a possible pathway of achieving brain-like compact and energy-efficient cognitive intelligence. Current computational models attempt to exploit the intrinsic device stochasticity of nanoelectronic synaptic or neural components to perform learning and inference. However, there has been limited analysis on the scaling effect of stochastic spin devices and its impact on the operation of such stochastic networks at the system level. Our work attempts to explore the design space and analyze the performance of nanomagnet based stochastic neuromorphic computing architectures, for magnets with different barrier heights. We illustrate how the underlying network architecture must be modified to account for the random telegraphic switching behavior displayed by magnets as they are scaled into the superparamagnetic regime.<br></p><p>Next we investigate how the magnetic properties of spin devices can be utilized for real world sensory applications. Magnetic Tunnel Junctions can efficiently translate variations in external magnetic fields into variations in electrical resistance. We couple this property of Magnetic Tunnel Junctions with Amperes law to design a non-invasive sensor to measure the current flowing through a wire. We demonstrate how undesirable effects of thermal noise and process variations can be suppressed through novel analog and digital signal conditioning techniques to obtain reliable and accurate current measurements. Our results substantiate that the proposed noninvasive current sensor surpass other state-of-the-art technologies in terms of noise and accuracy.<br></p><br>

Novel devices are being investigated as artificial synapse candidates for neuromorphic computing. These memory devices share the characteristics of an electronic element called memristor. The memristor can be regarded as a resistor with a history dependent resistance, which mimics the plasticity of a biological synapse. The present work presents various types of candidate devices that have been proposed in neuromorphic research, describes how they mimic a biological synapse and how they can be employed in artificial neuron network architectures.

No description available.

La recherche dans le domaine de l’informatique neuro-inspirée suscite beaucoup d'intérêt depuis quelques années. Avec des applications potentielles dans des domaines tels que le traitement de données à grande échelle, la robotique ou encore les systèmes autonomes intelligents pour ne citer qu'eux, des paradigmes de calcul bio-inspirés sont étudies pour la prochaine génération solutions informatiques (post-Moore, non-Von Neumann) ultra-basse consommation. Dans ce travail, nous discutons les rôles que les différentes technologies de mémoire résistive non-volatiles émergentes (RRAM), notamment (i) Phase Change Memory (PCM), (ii) Conductive-Bridge Memory (CBRAM) et de la mémoire basée sur une structure Metal-Oxide (OXRAM) peuvent jouer dans des dispositifs neuromorphiques dédies. Nous nous concentrons sur l'émulation des effets de plasticité synaptique comme la potentialisation à long terme (Long Term Potentiation, LTP), la dépression à long terme (Long Term Depression, LTD) et la théorie STDP (Spike-Timing Dependent Plasticity) avec des synapses RRAM. Nous avons développé à la fois de nouvelles architectures de faiblement énergivore, des méthodologies de programmation ainsi que des règles d’apprentissages simplifiées inspirées de la théorie STDP spécifiquement optimisées pour certaines technologies RRAM. Nous montrons l’implémentation de systèmes neuromorphiques a grande échelle et efficace énergétiquement selon deux approches différentes: (i) des synapses multi-niveaux déterministes et (ii) des synapses stochastiques binaires. Des prototypes d'applications telles que l’extraction de schéma visuel et auditif complexe sont également montres en utilisant des réseaux de neurones impulsionnels (Feed-forward Spiking Neural Network, SNN). Nous introduisons également une nouvelle méthodologie pour concevoir des neurones stochastiques très compacts qui exploitent les caractéristiques physiques intrinsèques des appareils CBRAM. / Research in the field of neuromorphic- and cognitive- computing has generated a lot of interest in recent years. With potential application in fields such as large-scale data driven computing, robotics, intelligent autonomous systems to name a few, bio-inspired computing paradigms are being investigated as the next generation (post-Moore, non-Von Neumann) ultra-low power computing solutions. In this work we discuss the role that different emerging non-volatile resistive memory technologies (RRAM), specifically (i) Phase Change Memory (PCM), (ii) Conductive-Bridge Memory (CBRAM) and Metal-Oxide based Memory (OXRAM) can play in dedicated neuromorphic hardware. We focus on the emulation of synaptic plasticity effects such as long-term potentiation (LTP), long term depression (LTD) and spike-timing dependent plasticity (STDP) with RRAM synapses. We developed novel low-power architectures, programming methodologies, and simplified STDP-like learning rules, optimized specifically for some RRAM technologies. We show the implementation of large-scale energy efficient neuromorphic systems with two different approaches (i) deterministic multi-level synapses and (ii) stochastic-binary synapses. Prototype applications such as complex visual- and auditory- pattern extraction are also shown using feed-forward spiking neural networks (SNN). We also introduce a novel methodology to design low-area efficient stochastic neurons that exploit intrinsic physical effects of CBRAM devices.

L'augmentation du parallélisme, sur des puces dont la densité d'intégration est en constante croissance, soulève un certain nombre de défis tels que le routage de l'information qui se confronte au problème de "goulot d'étranglement de données", ou la simple difficulté à exploiter un parallélisme massif et grandissant avec les paradigmes de calcul modernes issus pour la plupart, d'un historique séquentiel.Nous nous inscrivons dans une démarche bio-inspirée pour définir un nouveau type d'architecture, basée sur le concept d'auto-adaptation, afin de décharger le concepteur au maximum de cette complexité. Mimant la plasticité cérébrale, cette architecture devient capable de s'adapter sur son environnement interne et externe de manière homéostatique. Il s'inscrit dans la famille du calcul incorporé ("embodied computing") car le substrat de calcul n'est plus pensé comme une boite noire, programmée pour une tâche donnée, mais est façonné par son environnement ainsi que par les applications qu'il supporte.Dans nos travaux, nous proposons un modèle de carte neuronale auto-organisatrice, le DMADSOM (pour Distributed Multiplicative Activity Dependent SOM), basé sur le principe des champs de neurones dynamiques (DNF pour "Dynamic Neural Fields"), pour apporter le concept de plasticité à l'architecture. Ce modèle a pour originalité de s'adapter sur les données de chaque stimulus sans besoin d'un continuum sur les stimuli consécutifs. Ce comportement généralise les cas applicatifs de ce type de réseau car l'activité est toujours calculée selon la théorie des champs neuronaux dynamique. Les réseaux DNFs ne sont pas directement portables sur les technologies matérielles d'aujourd'hui de part leurs forte connectivité. Nous proposons plusieurs solutions à ce problème. La première consiste à minimiser la connectivité et d'obtenir une approximation du comportement du réseau par apprentissage sur les connexions latérales restantes. Cela montre un bon comportement dans certain cas applicatifs. Afin de s'abstraire de ces limitations, partant du constat que lorsqu'un signal se propage de proche en proche sur une topologie en grille, le temps de propagation représente la distance parcourue, nous proposons aussi deux méthodes qui permettent d'émuler, cette fois, l'ensemble de la large connectivité des Neural Fields de manière efficace et proche des technologies matérielles. Le premier substrat calcule les potentiels transmis sur le réseau par itérations successives en laissant les données se propager dans toutes les directions. Il est capable, en un minimum d'itérations, de calculer l'ensemble des potentiels latéraux de la carte grâce à une pondération particulière de l'ensemble des itérations.Le second passe par une représentation à spikes des potentiels qui transitent sur la grille sans cycles et reconstitue l'ensemble des potentiels latéraux au fil des itérations de propagation.Le réseau supporté par ces substrats est capable de caractériser les densités statistiques des données à traiter par l'architecture et de contrôler, de manière distribuée, l'allocation des cellules de calcul. / The increasing degree of parallelism on chip which comes from the always increasing integration density, raises a number of challenges such as routing information that confronts the "bottleneck problem" or the simple difficulty to exploit massive parallelism thanks to modern computing paradigms which derived mostly from a sequential history.In order to discharge the designer of this complexity, we design a new type of bio-inspired self-adaptive architecture. Mimicking brain plasticity, this architecture is able to adapt to its internal and external environment and becomes homeostatic. Belonging to the embodied computing theory, the computing substrate is no longer thought of as a black box, programmed for a given task, but is shaped by its environment and by applications that it supports.In our work, we propose a model of self-organizing neural map, DMADSOM (for Distributed Multiplicative Activity Dependent SOM), based on the principle of dynamic neural fields (DNF for "Dynamic Neural Fields"), to bring the concept of hardware plasticity. This model is able to adapt the data of each stimulus without need of a continuum on consecutive stimuli. This behavior generalizes the case of applications of such networks. The activity remains calculated using the dynamic neural field theory. The DNFs networks are not directly portable onto hardware technology today because of their large connectivity. We propose models that bring solutions to this problem. The first is to minimize connectivity and to approximate the global behavior thanks to a learning rule on the remaining lateral connections. This shows good behavior in some application cases. In order to reach the general case, based on the observation that when a signal travels from place to place on a grid topology, the delay represents the distance, we also propose two methods to emulate the whole wide connectivity of the Neural Field with respect to hardware technology constraints. The first substrate calculates the transmitted potential over the network by iteratively allowing the data to propagate in all directions. It is capable, in a minimum of iterations, to compute the lateral potentials of the map with a particular weighting of all iterations.The second involves a spike representation of the synaptic potential and transmits them on the grid without cycles. This one is hightly customisable and allows a very low complexity while still being capable to compute the lateral potentials.The network supported, by these substrates, is capable of characterizing the statistics densities of the data to be processed by the architecture, and to control in a distributed manner the allocation of computation cells.

No description available.

Neuromorphic computing applications could be made faster and more power efficient by emulating the function of a biological synapse. Non-conventional spintronic devices have been proposed that demonstrate synaptic behavior through domain wall (DW) driving. In this work, current induced domain wall motion has been studied through micromagnetic simulations. We investigate the synaptic behavior of a head to head domain wall driven by a spin polarized current in permalloy (Py) nanostrips with shape anisotropy, where triangular notches have been modeled to account for edge roughness and provide pinning sites for the domain wall. We seek optimal material parameters to keep the critical current density for driving the domain wall at order 1011 A/m2.