For an Electrical Vehicle, the power is delivered from the battery pack to the electric motor through the use of power converter. Many research projects have been conducted in improving the efficiency of traction inverters. Inverter topologies are categorized based on the number of voltage levels of the inverter output phase voltage. The conventional 2-level Voltage Source Inverter (VSI) is commonly used as a traction inverter due to its simple structure. Due to the recent trend in utilizing higher DClink voltage in traction motor drives to achieve a higher power rating, multi-level inverters are gaining attention to replace the conventional VSI in EV powertrain. Multi-level voltage source inverters (MLVSI) have been widely adopted in high-power converters and medium-voltage drives. There are four major categories of MLVSI: the Flying Capacitor (FC), Neutral Point Clamped (NPC), Cascaded and Hybrid. The power rating of the MLVSI increases with the increase of inverter levels, but the size, number of switching devices, cost and control difficulty also increases. Due to the above reasons, 3-level NPC can be a good solution for traction inverters. Due to the structure and control limitation, Diode Clamp NPC suffers from uneven loss distribution and neutral point voltage balancing issues. This issue can be resolved with Active Clamped NPC (ANPC). In this thesis, the design, simulation, prototyping and testing of a 70kw 3-level ANPC traction is introduced. / Thesis / Master of Science (MSc)

Cette thèse a pour but l'analyse d'un système photovoltaïque connecté au réseau électrique en prenant en compte le contrôle, l'étude de la stabilité et la fiabilité. Un onduleur de type 2-Niveau a été comparé avec un onduleur multi-niveaux appelé Neutral Point Clamped. Les avantages et désavantage de chaque topologie ont été analysé en considérant l'efficacité énergétique, l'optimisation de l'injection de l'énergie sur le réseau électrique et la fiabilité du système. Pour le contrôle du courant de sortie de l'onduleur, ont été proposées deux solutions : un contrôle basé sur la théorie de la platitude et un contrôle par passivité. Ces deux différents contrôles sont comparés par rapport à la robustesse, la complexité et le nombre de capteurs utilisés. Il a été montré que les deux contrôles sont capables de gérer la problématique de la résonance du filtre LCL. Pour augmenter l'efficacité de l'algorithme MPPT dans une configuration Distributed-MPPT avec la connexion en série des deux sorties des convertisseurs boost, une nouvelle technique a été proposé pour l'équilibrage des tension d'entrée d'un onduleur NPC. En utilisant un outil appelé TPtool, un étude de la stabilité large signal par "Higher-Order-Singular-Value-Decomposition" a été présenté et comparé avec une méthode basée sur les modèles Takagi-Sugeno pour des systèmes non-linéaires. Finalement, l'onduleur 2-Niveaux est comparé avec deux multi-niveaux différents (NPP et NPC) en termes de disponibilité, en prenant en compte les niveaux de redondance des convertisseurs. Pour analyser la disponibilité, a été considérée la théorie des chaines de Markov et pour l'implémentation, le logiciel GRIF a été utilisé / The aim of this PhD thesis is to analyze a PV-grid connected system in terms of control, stability and reliability. A comparison between a classical 2-Level inverter and a multilevel NPC is presented. The advantages and weakness of both the converters are analyzed with respect to the power efficiency, optimization of the energy injection to the grid and reliability of the system. In order to control the inverter output current, two different solutions are proposed: flatness-based control and passivity-based control. These controls are compared in terms of robustness, complexity and number of sensors used. It is shown that both the controls may manage the resonance problems due to a LCL filter. For increasing the efficiency of the MPPT in a configuration Distributed-MPPT with connections in series of the boost converters outputs, a novel technique for the dc voltages balancing of a NPC inverter is proposed. A large stability analysis using "Higher-Order-Singular-Value-Decomposition" is presented and compared with Takagi-Sugeno approach for nonlinear systems. Finally, 2-Level inverter is compared with two multilevel inverters (NPC and NPP) in terms of availability, considering the redundancy levels of the converters. To analyze the systems availability, the Markov chains theory is considered and it is implemented on GRIF

Las topologías de convertidores multinivel han recibido una atención especial durante las dos últimas décadas debido a sus notables ventajas en aplicaciones de alta potencia y media/alta tensión. En estas topologías, y comparadas con el convertidor tradicional de dos niveles, el voltaje que soporta cada dispositivo semiconductor es menor, evitando los problemas asociados con la interconexión serie de dispositivos. La distorsión armónica en la tensión de salida es también menor y la eficiencia mayor. Pero incorporan un número superior de dispositivos semiconductores y la estrategia de modulación resultante es, por tanto, más compleja.Entre estas topologías, el convertidor cc-ca de tres niveles trifásico con conexión al punto neutro del bus de cc es probablemente el más popular. La aplicación a este convertidor de técnicas de modulación convencionales causa una oscilación de la tensión del punto neutro de baja frecuencia (tres veces la frecuencia fundamental de la tensión de salida). Esta oscilación, a su vez, supone un incremento del estrés de tensión de los dispositivos y provoca la aparición de armónicos de baja frecuencia en la tensión de salida.Esta tesis presenta una nueva técnica de modulación del pulso de conducción de los dispositivos semiconductores para convertidores de tres niveles trifásicos con conexión a punto neutro, capaz de conseguir un control completo de la tensión del punto neutro con una distorsión armónica reducida en la tensión de salida alrededor de la frecuencia de conmutación. Esta nueva técnica de modulación, basada en la definición de unos vectores espaciales virtuales, garantiza el equilibrado de la tensión del punto neutro con cualquier carga (lineal o no, cualquier factor de potencia) y para todo el rango de tensión de salida, con el único requisito de que la suma de corrientes de fase sea nula.Las características de la técnica de modulación propuesta y sus beneficios con respecto a otras modulaciones se han verificado a través de simulaciones y experimentos tanto en lazo abierto como en lazo cerrado. / Multilevel converter topologies have received special attention during the last two decades due to their significant advantages in high-power medium- and high-voltage applications. In these topologies, and compared to the previous two-level case, the voltage across each semiconductor is reduced, avoiding the problems of the series interconnection of devices. The harmonic distortion of the output voltage is also diminished and the converter efficiency increases. But a larger number of semiconductors is needed and the modulation strategy to control them becomes more complex.Among these topologies, the three-level three-phase neutral-point-clamped voltage source inverter is probably the most popular. The application of traditional modulation techniques to this converter causes a low frequency (three times the fundamental frequency of the output voltage) oscillation of the neutral-point voltage. This, in turn, increases the voltage stress on the devices and generates low-order harmonics in the output voltage.This thesis presents a novel pulsewidth modulation for the three-level three-phase neutral-point-clamped converter, able to achieve a complete control of the neutral-point voltage while also having a low output voltage distortion at around the switching frequency. The new modulation, based on a virtual space vector concept, guarantees the balancing of the neutral-point voltage for any load (linear or nonlinear, any load power factor) over the full range of converter output voltage, the only requirement being that the addition of the output three-phase currents equals zero.The performance of this modulation approach and its benefits over other previously proposed solutions are verified through simulation and experiments in both open- and closed-loop converter configurations.

Due to development of industries, power factor and harmonic pollution have become serious concerns in the power system. This thesis presents an adaptive linear neuron (ADALINE) - based static synchronous compensator (STATCOM) to cope with power quality issues in the industrial power system. The targeted compensating current of the STATCOM is generated based on the so-called LMS algorithm, thus the compensated system current becomes balanced and active even in reactive, unbalanced or distorted loads. In this thesis, the STATCOM is realized by using a three-level neutral point-clamped (NPC) inverter with the in-phase level-shifted sinusoidal pulse width modulation (IPLSPWM). Theoretical analysis of ADALINE method is detailed and hardware implementation of STATCOM is conducted to validate effectiveness of the proposed approach.

Power inverters, used to convert DC power to AC, are often used in e.g. solar power applications. However, they tend to be impractically large and expensive; as such, power miniaturization is an active research area. In this thesis, several classes of modern power inverters are evaluated and compared with regards to size, efficiency and output quality in order to identify areas of potential improvement. Methods for estimation of THD, power losses and input ripple are created and verified against a simulation of a five-level neutral-point-clamped inverter with SPWM control. Finally, this design is implemented physically and is found to achieve 94.5% efficiency and 7% THD under low voltage laboratory conditions, while remaining smaller than an average textbook.

As wide-bandgap devices continue to experience deeper penetration in commercial applications, there are still a number of factors which make the adoption of such technologies difficult. One of the most notable issues with the application of wide-bandgap technologies is meeting existing noise requirements and regulations. Due to the faster dv/dt and di/dt of SiC devices, more noise is generated in comparison to Si IGBTs. Therefore, in order to fully experience the benefits offered by this new technology, the noise must either be filtered or mitigated by other means. A survey of various DC/DC topologies was conducted in order to find a candidate for a battery interface in a UPS system. A three-level NPC topology was explored for its potential benefit in terms of noise, efficiency, and additional features. This converter topology was modeled, simulated, and a hardware prototype constructed for evaluation within a UPS system, although its uses are not limited to such applications. A UPS system is a good example of an application with strict noise requirements which must be fulfilled according to IEC standards. Based on a newly devised mode of operation, this converter was verified to produce no common-mode voltage under ideal conditions, and was able to provide a 6 dB reduction in common-mode voltage emissions in the UPS prototype. This was done while achieving a peak efficiency in excess of 99% with the ability to provide bidirectional power flow between the UPS and battery backup. The converter was verified to operate at the rated UPS conditions of 20 kW while converting between a total DC bus voltage of 800 V and a nominal battery voltage of 540 V. / Master of Science / As material advancements allow for the creation of devices with superior electrical characteristics compared to their predecessors, there are still a number of factors which cause these devices to see limited usage in commercial applications. These devices, typically referred to as wide-bandgap devices, include silicon carbide (SiC) transistors. These SiC devices allow for much faster switching speeds, greater efficiencies, and lower system volume compared to their silicon counterparts. However, due to the faster switching of these devices, there is more electromagnetic noise generated. In many applications, this noise must be filtered or otherwise mitigated in order to meet international standards for commercial use. Consequently, new converter topologies and configurations are necessary to provide the most benefit of the new wide-bandgap devices while still meeting the strict noise requirements. A survey of topologies was conducted and the modeling, design, and testing of one topology was performed for use in an uninterruptible power supply (UPS). This converter was able to provide a noticeable reduction in noise compared to standard topologies while still achieving very high efficiency at rated conditions. This converter was also verified to provide power bidirectionally—both when the UPS is charging the battery backup, and when the battery is supplying power to the load.

Neutral-point-clamped (NPC) three-level inverter is capable of handling higher dc bus voltage and producing output waveform of better quality than a conventional two-level inverter. The main objective of the present work is to analyze the existing PWM schemes for two-level and three-level inverters in terms of line current ripple, and to design new PWM techniques for the NPC inverter to reduce line current distortion. Various discontinuous PWM or bus-clamping PWM (BCPWM) methods for a two-level voltage source inverter are analyzed in terms of rms line current ripple, which is evaluated by integrating the error voltage (i.e. error between the applied and reference voltages). The BCPWM schemes can be broadly classified into continual-clamp PWM (CCPWM) and split-clamp PWM (SCPWM). It is shown that split-clamp PWM scheme leads to lower harmonic distortion than CCPWM scheme. Further, advanced bus-clamping PWM (ABCPWM) methods for a two-level inverter are also studied. These methods clamp each phase to the positive and negative DC terminals over certain intervals as in BCPWM schemes, and also switch each phase at double the nominal frequency in certain other intervals unlike in BCPWM. Analytical closed-form expressions are derived for the total rms harmonic distortion due to SCPWM, CCPWM and ABCPWM schemes. Existing sinusoidal and bus-clamping PWM schemes for three-level NPC inverters are also analyzed in the space vector domain. These methods are compared in terms of line current ripple analytically as well as experimentally. As earlier, closed-form expressions are derived for the harmonic distortion factors corresponding to centered space vector PWM (CSVPWM) and the various BCPWM methods. A three-level inverter can be viewed as an equivalent two-level inverter in each sixth of the fundamental cycle or hextant. This is widely used to simplify the control of an NPC inverter. Further, this approach makes it simple to extend the BCPWM and ABCPWM methods for two-level inverters to three-level inverters. Furthermore, the method of analysis of line current ripple for the two-level inverter can also be easily extended to the three-level case. The pivot vector, which is half the length of the longest voltage vectors produced by the NPC inverter, acts as an equivalent null vector for the conceptual two-level inverter. Each pivot vector can be produced by two inverter states termed as “pivot states”. Typically, in continuous modulation methods for NPC inverter such as sinusoidal PWM and centered space vector PWM, the switching sequence (i.e. the sequence in which the voltage vectors are applied) begins and ends with the same pivot vector in each subcycle, which is equivalent to a half-carrier cycle. To be more precise, the switching sequence starts with one pivot state and ends with the other in each subcycle. However, in case of BCPWM schemes, only one pivot state is used in a subcycle. The choice of pivot state results in a variety of BCPWM schemes for an NPC inverter. Different BCPWM schemes are evaluated in terms of rms line current ripple. The optimal BCPWM, which minimizes the rms current ripple, is determined for an NPC inverter, controlled as an equivalent two-level inverter. Further, four new switching sequences are proposed here for a three-level inverter, controlled as a conceptual two-level inverter. These sequences apply the pivot vector only once, but employ one of the other two vectors twice within the subcycle. These four switching sequences are termed as “ABCPWM sequences” for three-level inverter. These sequences exploit the flexibility available in the space vector approach to PWM to switch a phase more than once in a subcycle, which results in the application of an active vector twice within the subcycle. Influence of the proposed ABCPWM sequences on the line current ripple over a subcycle is studied. The various sequences are compared in terms of rms line current ripple over a subcycle. An analytical closed-form expression for rms line current ripple over a subcycle is derived in terms of reference magnitude, angle of reference voltage vector, and subcycle duration for each of the sequences. Further, closed-form expressions are also derived for the rms current ripple over a line cycle in terms of modulation index and subcycle duration, corresponding to the various sequences. The four proposed ABCPWM sequences for the NPC inverter can be grouped into two pairs of sequences. Each pair of sequences is shown to perform better than the individual sequences, if the two sequences are employed in appropriate spatial regions. Hence, with these two pairs of sequences, two hybrid PWM schemes are proposed. Finally, a hybrid PWM technique is proposed which employs all five sequences (conventional and proposed four sequences) in spatial regions where each performs the best. This is termed as “five-zone hybrid PWM”. The total harmonic distortion (THD) in the motor current, pertaining to all the proposed schemes, is studied theoretically over the entire range of linear modulation. The theoretical investigations are validated experimentally on a 2.2 kW, 415V, 4.9A, 50 Hz induction motor drive. The no-load current THD is measured over a range of fundamental frequency from 10 Hz to 50 Hz in steps of 2 Hz for the various PWM methods. Theoretical and experimental results bring out the reduction in current THD due to the proposed BCPWM schemes at fundamental frequencies of 45 Hz and above, compared to CSVPWM. The ABCPWM methods improve the performance at higher as well as lower modulation indices. Further improvement is achieved with the proposed five-zone hybrid PWM. At the rated frequency (50 Hz) of the drive, the improvement in line current distortion is around 36% with this hybrid PWM scheme over CSVPWM. The reduction in THD is also experimentally verified at different loads on the motor. The difference between the top and bottom capacitor voltages is measured at various operating conditions, corresponding to CSVPWM and the proposed schemes. No significant difference is observed in the dc neutral voltage shifts with the different proposed schemes and CSVPWM method. Thus, the proposed methods improve the THD at low and high speed ranges without appreciable worsening of the dc voltage unbalance.

This thesis project focuses on the simulation, design, hardware realization, and performance evaluation of a Three-phase Three-level (3-L) Sparse Neutral Point Clamped Converter (SNPCC) for Industrial Variable Speed Drives (VSDs). The basic operating principle of the SNPCC is briefly described based on switching functions. Accordingly, the modulation strategies as a combination of switching sequences are introduced. Three representative strategies are selected to be verified in this project. Afterward, active and passive components are selected based on analytical analysis mainly focusing on semiconductors losses, AC-side differential mode and common mode stresses. Meantime, the analytical analysis enables a straightforward performance comparison among the selected modulation strategies. Additionally, the reverse recovery process in the anti-parallel diode is identified, of which the energy losses are calculated. A calorimetric method is adopted in this project, which allows accurate temperature rise monitoring and provides a reliable way to measure the power losses generated by semiconductors. Eventually, an 800V 7.5kW prototype is constructed and put under test. The performance of the designed SNPCC is therefore evaluated and compared from losses and AC-side flux-linkage ripples perspectives, with the promising features highlighted and limits indicated. / Projektet fokuserar på simulering, konstruktion, hårdvarutillverkning och utvärdering av en trefas tre-nivå (3-L) Sparse Neutral Point Clamped Converter (SNPCC) för industriella varvtalsstyrda motordrifter (VSD). SNPCC:s grundläggandefunktionsprincip beskrivs kortfattat utifrån så kallade switchningsfunktioner. Därefter introduceras moduleringsstrategierna som en kombination av switchningssekvenser. Tre representativa strategier har valts ut för att verifieras i detta projekt. Därefter väljs aktiva och passiva komponenter på grundval av en analys som främst fokuserar på halvledarförluster och ledningsbundna störningar på växelsströmssidan. Analysen gör det möjligt att göra en enkel jämförelse av prestanda mellan de valda moduleringsstrategierna. Dessutom identifieras body-diodens återhämtningsprocess och energiförlusterna beräknas. I detta projekt används en kalorimetrisk förlustberäkning, som möjliggör noggrann övervakning av temperaturökningen och ger ett tillförlitligt sätt att mäta energiförlusterna i effekthalvledarna. Slutligen konstrueras och testas en 800V 7.5kW-prototyp. Prestandan hos den konstruerade SNPCC:n utvärderas med hänseende till förluster och flödesrippel på växelströmssidan. Fördelarna för den föreslagna tekniken lyfts fram och begränsningarna anges.

CoordenaÃÃo de AperfeiÃoamento de Pessoal de NÃvel Superior / Visando superar os desafios inerentes à conversÃo de energia elÃtrica em sistemas de alta potÃncia, minimizando as perdas e melhorando a qualidade da energia processada, este tra-balho tem por objetivo analisar e implementar uma tÃcnica de modulaÃÃo para ser aplicada nas duas topologias de inversores multinÃveis mais disseminadas - com neutro grampeado (NPC), e com capacitor flutuante (FC) - a fim de reduzir os esforÃos nos semicondutores, bem como melhorar o Ãndice de distorÃÃo harmÃnica da tensÃo de saÃda. Ao longo do trabalho foi evidenciada a necessidade da digitalizaÃÃo da tÃcnica proposta, visto que o desenvolvimento analÃgico da mesma acarretaria em um circuito complexo e de baixa confiabilidade. Dessa forma, escolheu-se como plataforma digital um FPGA, devido à sua facilidade de programa-ÃÃo e reconfiguraÃÃo, alÃm da alta velocidade e quantidade de pinos de entrada e saÃda. AlÃm da tÃcnica proposta, foram tambÃm desenvolvidas outras modulaÃÃes para fins de compara-ÃÃo, apresentando os padrÃes de chaveamento para cada uma delas, bem como o comporta-mento da corrente atravÃs dos semicondutores em cada perÃodo de chaveamento. Foi tambÃm realizada a anÃlise teÃrica das topologias e suas respectivas etapas de operaÃÃo, caracterÃsticas e levantamento das equaÃÃes que ditam a anÃlise das perdas para as diferentes situaÃÃes de tÃcnicas aplicadas a cada uma das estruturas. O desenvolvimento digital das tÃcnicas mostrou-se correta atravÃs da anÃlise das formas-de-onda colhidas por meio de um circuito digital-analÃgico. AlÃm disso, a comparaÃÃo da aplicaÃÃo dessas modulaÃÃes em inversores a trÃs nÃveis NPC e FC de 6 kW mostrou-se favorÃvel à tÃcnica proposta em termos de eficiÃncia e reduÃÃo da distorÃÃo harmÃnica em ambas as topologias, comprovando sua utilidade em con-versores multinÃveis de alta potÃncia. Por fim, foi apresentado o desenvolvimento da tÃcnica proposta em inversores com mais de trÃs nÃveis, onde se pode comprovar sua eficiente aplica-ÃÃo para tais fins, bem como sua expansibilidade para inversores de n nÃveis. / In order to overcome the challenge of processing electric energy in high power systems with minimal losses and high energy quality, this work presents the implementation and anal-ysis of a modulation technique applicable on both most well-known multilevel inverter struc-tures - neutral point-clamped (NPC), and flying capacitors (FC) - to reduce the stresses across the semiconductors devices, and to improve the total harmonic distortion of the output volt-age. Throughout the work, the necessity to digitalize the proposed technique has been evi-denced due to the high complexity and low reliability inherent to the analogical approach. Thus, the digital controller FPGA has been chosen, as it is easy to program and reconfigure, works at high speed, and has a lot of input and output pins. Additionally, other modulation techniques were also implemented to compare their performance with the proposed one, pre-senting the switching patterns and the behavior of the electrical currents through the semicon-ductors for each modulation. A theoretical analysis was also performed for both topologies and their respective operation principle, characteristics, and equations used on the losses anal-ysis for the different combinations of modulation applied to each structure. Finally, the digital development of the various techniques has proved to be correct by observing the waveforms obtained through the digital/analogical circuit. Besides, the comparison of the modulation techniques on 6 kW NPC and FC three-level prototype inverters proved to be favorable to the proposed technique in terms of efficiency and total harmonic distortion reduction on both topologies, confirming its usefulness on high power multilevel converters. At last, it was pre-sented the application of the proposed modulation technique to inverters with more than three levels, where it was observed its eligibility for n-levels topologies.

Made available in DSpace on 2016-12-12T20:27:38Z (GMT). No. of bitstreams: 1 Tiago Lemes.pdf: 2229669 bytes, checksum: 9b9cd44356c6d0002fccf67fe418f52b (MD5) Previous issue date: 2014-09-26 / Coordenação de Aperfeiçoamento de Pessoal de Nível Superior / The main subject of this work is the study of a 5 levels T-Type NPC inverter topology, which is applied in photovoltaic energy processing for power generation. The grid power injection is done controlling converter current, which is injected into grid. This work presents equations, component-designs and their validation, which are necessary for the Inverter s power structure implementation. Also inverter modeling and design of implemented controllers are described. Through this study, it was possible to build a 3 kW prototype, which besides the current control, has a system to balance the differential voltage of bus capacitors. Through the prototype, experimental results were acquired. / O objeto de estudo deste trabalho é a topologia inversora NPC T-Type 5 níveis, aplicada no processamento da energia fotovoltaica, sendo o principal objetivo a geração de energia elétrica por meio do controle da corrente aplicada à rede. Este trabalho apresenta o equacionamento, projeto dos componentes e sua validação, que fazem parte da estrutura de potência do inversor, bem como a sua modelagem e projeto dos controladores implementados. Por intermédio deste estudo foi possível construir um protótipo com potência nominal de 3 kW, que além do controle da corrente, apresenta uma malha de equilíbrio da tensão diferencial do barramento. Mediante construção desse protótipo, foram extraídos os resultados experimentais.