The electrical efficiency of telecommunication power supplies is increasing to meet customer demands for lower total cost of ownership. Increased capital cost can now be justified if it enables sufficiently large energy savings, allowing the use of topologies and devices previously considered unnecessarily complex or expensive. Silicon carbide Schottky diodes have already been incorporated into commercial power supplies as expensive, but energy saving components. This thesis pursues the next step of considering silicon carbide transistors for use in telecommunications power converters. A range of silicon carbide transistors was considered with a primary focus on recently developed, normally-off, junction field effect transistors. Tests were devised and performed to uncover a number of previously unpublished characteristics of normally-off silicon carbide JFETs. Specifically, unique reverse conduction and associated gate current draw relationships were measured as well as the ability to block small reverse voltages when a negative gate-source voltage is applied. Reverse recovery-like characteristics were also measured and found to be superior to those of silicon MOSFETs. These characteristics significantly impact the steps that are required to maximize efficiency with normally-off SiC JFETs in circuits where synchronous rectification or bidirectional blocking is performed. A gate drive circuit was proposed that combines a number of recommendations to achieve rapid and efficient switching of normally-off SiC JFETs. Specifically, a low transient output impedance was provided to achieve rapid turn-on and turn-off transitions as well as a high dc output impedance to limit the steady state drive current while sustaining the turned-on state. A prototype circuit was constructed using building blocks that are typically found in single chip MOSFET drivers. The circuit was shown to operate well from a single supply, alleviating the need for a split supply such as that required by many published JFET drive circuits. This demonstrated a proof of concept for a single chip JFET driver solution. An active power factor correction circuit topology was extensively modelled and a prototype designed and tested to verify the model. The circuit was able to operate at switching frequencies in excess of 100kHz when using SiC JFETs, whereas silicon MOSFETs could only achieve switching frequencies of several kHz before switching losses became excessive. The circuit was designed as the dc equivalent for a 2kW, 230V AC input power converter with a split +/-400V dc output. A commercial single phase telecommunications power converter was modified to utilise normally-off SiC JFETs in its power factor correction circuit. The converter was tested and found to achieve similar electrical efficiency with 1200V SiC JFETs to that achieved with 600V silicon MOSFETs. The performance of the 1200V SiC JFETs in this application was also compared to that of 900V silicon MOSFETs and found to be superior. Finally, a prototype three-phase cyclo-converter was modified to use 1200V normallyoff SiC JFETs in place of 600V silicon MOSFETs and found to achieve similar electrical efficiency to the silicon MOSFETs in a 208V three phase system. These results strongly indicate that the 1200V SiC JFETs would provide better performance than 900V silicon MOSFETs in a 400V three phase system (that had been considered for commercial development).

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Power consumption is one of the most important design factors in modern electronic design. With a large market increase in portable battery-operated devices and push for environmental focus, it is of interest for the industry to decrease the power consumption of modern chips as much as possible. However, as circuits scale down in size the leakage current increases. This increases the static power consumption, and in future technologies the static power is expected to make up most of the overall power consumption. Power gating can decrease static power by isolating a circuit block from the power supply. In large chips, this requires state-retention flip flops and non-volatile memories in order to keep the circuit functioning continuously between power gating sequences. A design concept utilizing this is a Normally Off computer, which is in an off-state with no static power for the majority of the time. This is achieved by using non-volatile logic and memories. This concept has been realized by using a new semiconductor technology developed at Semiconductor Energy Laboratories Corporation Ltd., which is known as crystalline In-Ga-Zn oxide semiconductor material. This technology realizes transistors with an ultra-low off-state current, and enables several novel designs of state-retention circuits suitable for Normally-Off computers. This thesis presents two different architectures of state retention flip flops utilizing In-Ga-Zn oxide semiconductor transistors, which are produced and compared to determine their tradeoffs and effectiveness. These flip flops are then implemented in a 32-bit Normally-Off microprocessor to determine the performance of each implementation. This is evaluated by calculating the energy break-even time, which is the power gating time required to overcome the power overhead introduced by the state-retention flip flops. The resulting circuits and the work in this thesis has been presented at two conferences and submitted for publication in one scientific journal.

Depuis le début des années 2000, les composants en carbure de silicium (SiC) sont présents sur le marché principalement sous la forme de diodes Schottky et de transistors FET. Ces nouveaux semi-conducteurs offrent des performances en commutation bien supérieures à celles des composants en silicium (Si) ce qui se traduit par une diminution des pertes et une réduction de la température de fonctionnement à système de refroidissement identique. L’utilisation de composants SiC ouvre donc la possibilité de concevoir des convertisseurs plus compacts ou à une fréquence de commutation élevée pour une même compacité. C’est avec cet objectif d’augmentation de la fréquence de commutation qu’a été menée cette étude axée sur l’utilisation de composants SiC au sein d’un onduleur triphasé. Le convertisseur sur lequel se base l’étude accepte une tension d’entrée de 450V et fournit en régime nominal un courant de sortie efficace par phase de 40 A. Le choix des composants SiC s’est porté sur des transistors JFET Normally-Off et des diodes Schottky SiC car ces composants étaient disponibles à la vente au début de ces travaux et offrent des pertes en commutation et en conduction inférieures aux autres structures en SiC. Les transistors FET possèdent une structure et des propriétés bien différentes des IGBT habituellement utilisés pour des convertisseurs de la gamme considérée notamment par leur capacité à conduire un courant inverse avec ou sans diode externe. De ce fait, il est nécessaire de développer de nouveaux outils d’aide au dimensionnement dédiés à ces composants SiC. Ces outils de calculs sont basés principalement sur les paramètres électriques et thermiques du système et sur les caractéristiques des composants SiC. Les premiers résultats montrent qu’en autorisant la conduction d’un courant inverse au sein des transistors, il est possible de diminuer le nombre de composants. Basées sur ces estimations, une maquette de bras d’onduleur a été développée et testée. Les premiers thermiques montrent que pour une puissance de 12kW, il est possible d’augmenter la fréquence de commutation de 12 kHz à 100 kHz. / Since 2000, Silicon Carbide (SiC) components are available on the market mainly as Schottky diodes and FET transistor. These new devices provide better switching performance than Silicon (Si) components that leads to a reduction of losses and operating temperatures at equivalent cooling system. Using SiC components allows to a better converter integration. It is in this context that ECA-EN has started this thesis dedicated to using SiC devices in a three-phase inverter at high switching frequency. The converter object of this study is supply by a input voltage of 450V and provides a current of 40A per phase. The components used for these study are SiC Normally-Off JFET and Schottky Diodes because these devices were commercialized at the begining of this thesis and offer better switching performance than others SiC components. FET transistors have a different structure compared to traditionnal IGBT especially their capability to conduct a reverse current with or without body diode. So it is necessary to develop new tools dedicated to the design of converters built with SiC components. These tools are based on the electrical properties of the converters and the statics and dynamics characteristics of the transistor and the diode. The results show that when the transistors conduct a reverse current, the number of components/dies can be reduced. According to data, a PCB board of an inverter leg has been built and tested at ECA-EN. The thermal measurement based on the heatsink shows that the switching frequency of an inverter leg can be increased from 12 to 100 kHz for an ouput power of 12kW.

La thèse porte sur le développement de composants à base d’hétérojonction AlGaN/GaN. Cette hétérojonction permet de bénéficier d’une excellente mobilité (2000 cm²/V.s) grâce à l’apparition d’un gaz d’électron dans le GaN. Cependant, les composants fabriqués sur cette hétérojonction sont normally-on. Pour des raisons de sécurité et d’habitude de conception des composants normally-off sont nécessaires. Il existe de nombreuses façons de fabriquer des transistors normally-off à base d’hétérojonction AlGaN/GaN, dans cette thèse nous avons choisi d’étudier un MOSCHEMT, cette structure est caractérisée par une grille de type MOS et des accès de type HEMT possédant les excellentes propriétés de l’hétérojonction, en fonction des paramètres technologiques : épitaxie, process et structure des composants. L’une des variations technologiques étudiées est une structure cascodée permettant d’améliorer les performances à l’état passant sans détériorer la caractéristique en blocage des composants. L’objectif est de concevoir un composant normally-off sur substrat silicium 200 mm avec une tension de seuil supérieure à 1V, pouvant tenir 600 V en blocage, avec un calibre en courant entre 10 A et 30 A et compatible en salle blanche CMOS. Le manuscrit comporte quatre chapitres. Grâce à une étude bibliographique, le premier chapitre présente les différentes méthodes permettant d’obtenir un transistor normally-off à base de nitrure de gallium. Ce chapitre présente et justifie le choix technologique du CEA-LETI. Le deuxième chapitre présente les modèles ainsi que les méthodes de caractérisations utilisés au cours de la thèse. Le troisième chapitre traite des résultats obtenus en faisant varier les paramètres de fabrication sur les MOSC-HEMT. Enfin, le quatrième chapitre montre une étude sur une technologie innovante de type cascode. Cette structure doit permettre d’augmenter la tension de claquage des transistors sans détériorer l’état passant. / This thesis focuses on the development of AlGaN/GaN heterojunction components or HEMT. This heterojunction has an excellent mobility (2000 cm² / V.s) thanks to the appearance of an electron gas in the GaN. However, the components made with this heterojunction are normally-on. For safety reasons particularly, normally-off components are required. There are many ways to make normally-off transistors based on AlGaN/GaN heterojunction. In this thesis we chose to study a MOSCHEMT strucutre. This structure is characterized by a MOS type gate and HEMT type accesses. The study shows the effects of technological parameters (epitaxy, process and component structure) on the electrical behaviour of the components. Another structure studied is the monolithic cascode, which can improve on-state performance of the MOSC-HEMT without damaging the characteristic in reverse of the components. The objective of this thesis is to design a normally-off component on silicon substrate 200 mm with a threshold voltage higher than 1V, able to hold 600 V in reverse, with a current rating between 10 A and 30 A and compatible in CMOS clean room. The manuscript has four chapters. Through a bibliographic review, the first chapter presents the different methods to obtain a normally-off transistor based on gallium nitride. This chapter presents and justifies the technological choice of CEA-LETI. The second chapter presents the models as well as the methods of characterizations used during the thesis. The third chapter deals with the results obtained by varying the manufacturing parameters on the MOSC-HEMTs. Finally, the fourth chapter shows a study on innovative cascode technology. This structure must make it possible to increase the breakdown voltage of the transistors without damaging the on state.

Ce document présente les travaux de thèse ayant pour objet la recherche et développement d’une technologie co-intégrée HEMT GaN normale-on/normally-off compatible avec les matériaux et procédés technologiques de la technologie normally-on hyperfréquence. Un exposé théorique et une revue de l’état de l’art permettent d’abord d’entrevoir les différentes solutions technologiques qui s’offrent à nous, tout en affirmant et en précisant les applications visées. Différentes briques technologiques sont ensuite développées pour la fabrication de MOS-HEMTs GaN à recess de grille sur des épi-structures à barrière AlGaN ou (Ga)InAlN dédiées aux applications hyperfréquences. Nous insistons sur la possibilité d’intégrer les 2 fonctionnalités normally-off et normally-on de manière monolithique. Les échantillons ainsi réalisés sont ensuite caractérisés électriquement de manière conventionnelle, mais aussi en utilisant des techniques avancées de spectroscopie de pièges comme les paramètres S à basse fréquence et la mesure du transitoire de RON. Bien que certains phénomènes de piègeage dans l’oxyde de grille soient mis en évidence, les résultats sont très satisfaisants : des composants normally-off sont obtenus pour les 2 structures, et les performances sont au niveau de l’état de l’art mondial, avec plusieurs pistes d’amélioration en perspective. / This document reports on research and development efforts towards a normally-on/normally-off integrated GaN HEMT technology that remains compatible with the material and processing dedicated to normally-on microwave devices. Following several theoretical considerations, the state-of-the-art is presented, which gives a perspective on the available technological solutions and helps define the specifications and the targeted applications. The development and optimization of new process steps enables the fabrication of gate-recessed MOS-HEMTs on epi-structures with AlGaN or (Ga)InAlN barrier, monolithically integrable with normally-on transistors. The samples are electrically characterized by means of standard measurements and more advanced trap spectroscopy techniques such as low-frequency S-parameters or RON transient monitoring. In spite of oxide-related trapping phenomena, the results are very promising: normally-off devices are obtained for both structures, and the performances are in line with literature accounts while identified possible improvements can be explored.

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