Este trabalho mostra os diversos sistemas de representação numérica, incluindo o sistema numérico normalmente utilizado em circuitos e alguns sistemas alternativos. Uma maior ênfase é dada ao sistema numérico por resíduos. Este último apresenta características muito interessantes para o desenvolvimento de circuitos aritméticos nos dias atuais, como por exemplo, a alta paralelização. São estudadas também as principais arquiteturas de somadores e multiplicadores. Várias descrições de circuitos aritméticos são feitas e sintetizadas. A arquitetura de circuitos aritméticos utilizando o sistema numérico por resíduos também é estudada e implementada. Os dados da síntese destes circuitos são comparados com os dados dos circuitos aritméticos tradicionais. Com isto, é possível avaliar as potenciais vantagens de se utilizar o sistema numérico por resíduos no desenvolvimento de circuitos aritméticos. / This work shows various numerical representation systems, including the system normally used in current circuits and some alternative systems. A great emphasis is given to the residue number system. This last one presents very interesting characteristics for the development of arithmetic circuits nowadays, as for example, the high parallelization. The main architectures of adders and multipliers are also studied. Some descriptions of arithmetic circuits are made and synthesized. The architecture of arithmetic circuits using the residue number system is also studied and implemented. The synthesis data of these circuits are compared with the traditional arithmetic circuits results. Then it is possible to evaluate the potential advantages of using the residue number system in arithmetic circuits development.

Speeding up addition is the key to faster digital signal processing (DSP). This can be achieved by exploiting the properties of redundant number systems. Their expanded symbol (digit) alphabet gives them multiple representations for most values. Utilising redundant representations at the output of an adder permits addition to be performed without carry-propagation, yielding fast, constant time performance irrespective of the word length. A resource efficient implementation of this fast adder structure is developed that re-purposes the fast carry logic of low-cost field programmable gate arrays (FPGAs). Experiments confirm constant time addition and show that it outperforms binary ripple carry addition at word lengths of greater than 44 bits in a Xilinx Spartan 3 FPGA and 24 bits in an Altera Cyclone III FPGA. Redundancy also provides other properties that can be exploited for performance gain. Some redundant representations will have more zero-symbols than others. These maximise the opportunities to exploit the multiplicative absorbing and additive identity properties of zero that when exercised reduce superfluous calculations. A serial recoding algorithm is developed that generates a redundant representation for a specified value with as few nonzero symbols as possible. Unlike previously published methods, it accepts a wide specification of number systems including those with irregularly spaced symbol alphabets. A Markov analysis and analysis of the elementary cycles in the formulated state machine provides average and worst case measures for the tested number system. Typically, the average number of non-zero symbols is less than a third and the worst case is less than a half. Further to the increase in zero-symbols, zero-dominance is proposed as a new property of redundant number representations. It promotes a set of representations that have uniquely positioned zero-symbols, in a Pareto-optimal sense. This set covers all representations of a value and is used to select representations to optimise the calculation of a dot-product. The dot-product or vector-multiply is a fundamental operation in DSP, since it is employed in filtering, correlation and convolution. The nonzero partial products can be packed together, substantially reducing the calculation time. The application of redundant number systems provides a two-fold benefit. Firstly, the number of nonzero partial products is reduced. Secondly, a novel opportunity is identified to use the representations in the zero-dominant set to optimise the packing further, gaining an extra 18% improvement. An implementation of the proposed dot-product with partial product packing is developed for a Cyclone II FPGA. It outperforms a quad-multiplier binary implementation in throughput by 50% . Redundant number systems excel at increasing performance in particular DSP subsystems, those that are numerically intensive and consist of considerable accumulation. The conversion back to a binary result is the performance bottleneck in the DSP algorithm, taking a time proportional to a binary adder. Therefore, redundant number systems are best utilised when this conversion cost can be amortised over many fast redundant additions, which is typical in many DSP and communications applications.

Switched-Capacitor Converters (SCC) suffer from a fundamental power loss deficiency which make their use in some applications prohibitive. The power loss is due to the inherent energy dissipation when SCC operate between or outside their output target voltages. This drawback was alleviated in this work by developing two new classes of SCC providing binary and arbitrary resolution of closely spaced target voltages. Special attention is paid to SCC topologies of binary resolution. Namely, SCC systems that can be configured to have a no-load output to input voltage ratio that is equal to any binary fraction for a given number of bits. To this end, we define a new number system and develop rules to translate these numbers into SCC hardware that follows the algebraic behavior. According to this approach, the flying capacitors are automatically kept charged to binary weighted voltages and consequently the resolution of the target voltages follows a binary number representation and can be made higher by increasing the number of capacitors (bits). The ability to increase the number of target voltages reduces the spacing between them and, consequently, increases the efficiency when the input varies over a large voltage range. The thesis presents the underlining theory of the binary SCC and its extension to the general radix case. Although the major application is in step-down SCC, a simple method to utilize these SCC for step-up conversion is also described, as well as a method to reduce the output voltage ripple. In addition, the generic and unified model is strictly applied to derive the SCC equivalent resistor, which is a measure of the power loss. The theoretical predictions are verified by simulation and experimental results.

Submitted by Cláudia Bueno (claudiamoura18@gmail.com) on 2015-10-26T16:12:34Z No. of bitstreams: 2 Dissertação - Iron Felisberto de Freitas - 2015.pdf: 4566285 bytes, checksum: 347da00cced574440e6a02e8b4ddf92f (MD5) license_rdf: 23148 bytes, checksum: 9da0b6dfac957114c6a7714714b86306 (MD5) / Approved for entry into archive by Luciana Ferreira (lucgeral@gmail.com) on 2015-10-27T14:35:43Z (GMT) No. of bitstreams: 2 Dissertação - Iron Felisberto de Freitas - 2015.pdf: 4566285 bytes, checksum: 347da00cced574440e6a02e8b4ddf92f (MD5) license_rdf: 23148 bytes, checksum: 9da0b6dfac957114c6a7714714b86306 (MD5) / Made available in DSpace on 2015-10-27T14:35:43Z (GMT). No. of bitstreams: 2 Dissertação - Iron Felisberto de Freitas - 2015.pdf: 4566285 bytes, checksum: 347da00cced574440e6a02e8b4ddf92f (MD5) license_rdf: 23148 bytes, checksum: 9da0b6dfac957114c6a7714714b86306 (MD5) Previous issue date: 2015-03-27 / Coordenação de Aperfeiçoamento de Pessoal de Nível Superior - CAPES / This paper addresses the formal-logical construction of number systems from the set of natural numbers to the real numbers. Being the rst of these sets presented by the axioms of Peano (1858 - 1932) and the latter results of Dedekind cuts (1831 - 1916) on the set of rational numbers. The passage the set of natural numbers to the integers and for these the rational is done by equivalence classes. From a historical perspective, in order to do that mathematics could advance, had to migrate from a sense of \reality" to an abstract concept of number not subject to the amount of idea. Since the beginning of this formal-logical construction of number systems it is necessary to use the concept of correspondences between any two non-empty sets. Finally , are also addressed the polynomial functions of 1st and 2nd degrees and the respective charts in orthogonal Cartesian plane. / O presente trabalho aborda a constru c~ao l ogico-formal dos sistemas num ericos desde, o conjunto dos n umeros naturais at e ao dos n umeros reais. Sendo o primeiro destes conjuntos apresentado pelos axiomas de Peano (1858 - 1932), e o ultimo resulta dos cortes de Dedekind (1831 - 1916) sobre ao conjunto dos n umeros racionais. A passagem do conjunto dos n umeros naturais ao dos inteiros e destes ao dos racionais e realizado por classes de equival^encias. Em uma perspectiva hist orica, a m de que, a Matem atica pudesse avan car, era preciso migrar de uma no c~ao de \realidade" para um conceito abstrato de n umero n~ao subordinado a ideia de quantidade. Desde o in cio desta constru c~ao l ogico-formal dos sistemas num ericos faz-se necess ario o uso do conceito de correspond^encias entre dois conjuntos n~ao vazios quaisquer. Por m, s~ao tamb em abordadas as fun c~oes polinomiais de 1o e 2o graus e seus respectivos gr a cos no plano cartesiano ortogonal.

What do the Honda Civic, the Mazda 626, and the Boeing 747 have in common? What about Weird Al's song Bob, the first name of Miley Cyrus' alter ego, and the 70s sensation Abba? What do all these things have in common? They all contain palindromes. While some people recognise a palindrome when they see one, fewer realise that a palindrome is a special case of a pattern and that these patterns are all around. Palindromes frequently occur in names, both of vehicles and people, and in music.