As the number of cores integrated on a single chip continues to increase, communication has the potential to become a severe bottleneck to overall system performance. The presence of thread sharing and the distribution of data across cache banks on the chip can result in long distance communication. Long distance communication incurs substantial latency that impacts performance; furthermore, this communication consumes significant dynamic power when packets are switched over many Network-on-Chip (NoC) links and routers. Thread migration can mitigate problems created by long distance communication. This thesis presents Moths, which stands for Mobile Threads. Moths is an efficient run-time algorithm that responds automatically to dynamic NoC traffic patterns, providing beneficial thread migration to decrease overall traffic volume and average packet latency. Moths reduces latency by up to 28.4% (18.0% on average) and traffic volume by up to 24.9% (20.6% on average) across a variety of commercial and scientific benchmarks.

As the number of cores integrated on a single chip continues to increase, communication has the potential to become a severe bottleneck to overall system performance. The presence of thread sharing and the distribution of data across cache banks on the chip can result in long distance communication. Long distance communication incurs substantial latency that impacts performance; furthermore, this communication consumes significant dynamic power when packets are switched over many Network-on-Chip (NoC) links and routers. Thread migration can mitigate problems created by long distance communication. This thesis presents Moths, which stands for Mobile Threads. Moths is an efficient run-time algorithm that responds automatically to dynamic NoC traffic patterns, providing beneficial thread migration to decrease overall traffic volume and average packet latency. Moths reduces latency by up to 28.4% (18.0% on average) and traffic volume by up to 24.9% (20.6% on average) across a variety of commercial and scientific benchmarks.

En la última década del siglo XX, el campo de los microsistemas para análisis total (µ-TAS) y, más concretamente, el de los DNA-chips ha adquirido una importancia preponderante en el ámbito de los microsistemas. En gran parte, el creciente interés por estos dispositivos se debe a las substanciales mejoras que prometen: análisis más rápidos, baratos y automatizados, pero también es debido a la posibilidad de implementar técnicas analíticas antes impensables (e.g. chips de hibridación). En el caso particular de los DNA-chips, se han desarrollado prototipos funcionales para PCR, LCR, electroforesis en gel, di-electroforesis, hibridación y varias combinaciones de estas técnicas, al tiempo que los chips de hibridación masiva (mayoritariamente basados en arrayers) han llegado a convertirse en un éxito comercial. Aun así, y aunque se ha llevado a cabo mucho trabajo en estos años, es necesaria todavía mucha investigación para afrontar algunos de los principales retos de los DNA-chips. En el transcurso de esta tesis doctoral, se ha llevado a cabo el desarrollo un proceso tecnológico común para la fabricación de DNA-chips multifunción (i.e. sistemas versátiles basados en PCR y electroforesis), poniendo un especial énfasis en la compatibilidad con los procesos CMOS estándar, a fin de conseguir desarrollar prototipos proto-industriales. Como demostrador de esta puesta a punto tecnológica, se han diseñado, fabricado y testado chips de PCR, y la PCR en chips ha sido optimizada con respecto a materiales de fabricación, metodologías de inserción/extracción, composición bioquímica de la mix de PCR, diferentes configuraciones de calentadores/sensores (Peltier/termopares vs. resistencias integradas) y la cinética de la reacción. / In the last decade of the twentieth century, the fields of µ-TAS and, more specifically, DNA-chips have acquired increasing importance in the microsystems arena. The main reason for this surge of interest lies in the advantages these new devices seek to bring forth: faster, cheaper and completely automated analyses, and also in the outbreak of novel analytical techniques (e.g. hybridization chips). In the particular case of DNA-chips, functional prototypes have been demonstrated for PCR, LCR, gel electrophoresis, di-electrophoresis, hybridization and various combinations of these techniques, whilst hybridization chips (mainly arrayer chips) have become a successful market application. But, even though a considerable amount of work has been carried out in these few years, much research is still required to address fundamental problems of DNA-chips. In this doctoral work, a common-ground technological setup for the production of multifunction DNA-chips (i.e. PCR plus electrophoresis systems) has been laid down, placing strong emphasis in its compatibility with standard CMOS processes in order to produce proto-industrial prototypes. As a demonstrator of this technological setup, PCR-chips have been designed, manufactured and tested, and the chip PCR reaction has been optimized with respect to surface materials, insertion and extraction methods, biochemical mix composition, heater/sensor setups (Peltier/thermocouple vs. thin-film driven systems) and reaction kinetics.

This project targets the problems with design and implementation of Single Instruction Multiple Data (SIMD) architectures in System-on-Chip (SoC), with the goal to construct a reconfigurable framework in VHDL to ease this process. The resulting framework should be implemented on an FPGA and its usability tested. The main parts of a SIMD archi- tecture was identified to be the Control Unit (CU), the Processing Elements (PE) and the Interconnection Network (ICN), and a framework was constructed with these parts as the main building blocks. The constructed framework is reconfigurable in data width, memory size, number of PEs, topology and instruction set. To test ease of use and per- formance of the system a FIR-filter application was implemented. The scalability of the system and its different parts has been measured and comparisons are illustrated.

In this thesis we focus on the investigation of the relation between the the chip-firing and fractional coloring. Since chi_{f}(G)=inf {n/k : G is homomorphic to K(n,k)}, we find that G has an (n,k)-periodic sequence for some configuration if and only if G is homomorphic to K(n,k). Then we study the periodic configurations for the Kneser graphs. Finally, we try to evaluate the number of chips of the periodic configurations for K(n,k).

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An in-circuit emulator (ICE) is an important tool for the development of microprocessor-based systems. External ICE boxes are complex and expensive piece of hardware so their use is usually limited to debugging phases of the microprocessor-based systems that involve hardware/software integration or investigation of real time I/O or bus events. On the other hand, a ROM monitor is inexpensive, but provides less observablity for the microprocessor¡¦s operations. In either case, the design practice of the ICE devices is usually independent to the design task of the microprocessor itself. The performance and cost of the ICE devices are not relevant to the microprocessors since they are two different entities. The ICE¡¦s are used only during the development/debugging of the microprocessor-based systems by substituting the original microprocessor on the socket with the ICE. The ICE is unplugged after debugging and the original microprocessor is placed back into the socket for normal operations of the microprocessor-based systems. Therefore, the performance and cost of the ICE¡¦s do not impact these of the microprocessor-based systems because the ICE¡¦s do not exist in them. We then define three feasible solutions software, hardware and hybrid) and integrate them with a synthesizable ARM7 icroprocessor core. The microprocessors with the embedded ICE¡¦s are synthesized and simulated to analyze and compare the corresponding hardware/software performance and cost and the debugging features of these approaches.

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Thesis (Ph. D.)--University of Texas at Austin, 2002. / Vita. Includes bibliographical references. Available also from UMI Company.

Thesis (Ph. D.)--School of Mechanical Engineering, Georgia Institute of Technology, 2004. Directed by Daniel F. Baldwin. / Vita. Includes bibliographical references (leaves 202-210).