L'évolution de Systems-on-Chip (SoCs) est rapide et le nombre des processeurs augmente conduisant à la transition des les plates-formes Multi-core vers les Manycore. Dans telles plates-formes, l'architecture d'interconnexion a également décalé des bus traditionnels vers les Réseaux sur puce (NoC) afin de faire face à la mise en échelle. Les NoC permettent aux processeurs d'échanger des informations avec la mémoire et les périphériques lors de l'exécution d'une tâche et d'effectuer plusieurs communications en parallèle. Les plates-formes basées sur un NoC sont aussi présentes dans des systèmes embarqués, caractérisés par des exigences comme la prédictibilité, la sécurité et la criticité mixte. Afin de fournir telles fonctionnalités dans les plates-formes commerciales existantes, il faut prendre en considération le NoC qui est un élément clé ayant un impact important sur les performances d'un SoC. Une tâche échange des informations à travers du NoC et par conséquent, son temps d'exécution dépend du temps de transmission des flux qu'elle génère. En calculant le temps de transmission de pire cas (WCTT) des flux dans le NoC, une étape est faite vers le calcul du temps d'exécution de pire cas (WCET) d'une tâche. Ceci contribue à la prédictibilité globale du système. De plus, en prenant en compte les politiques d'arbitrage dans le NoC, il est possible de fournir des garanties de sécurité contre des tâches compromises qui pourraient essayer de saturer les ressources du système (attaque DoS). Dans les systèmes critiques de sécurité, une distinction des tâches par rapport à leur niveau de criticité, permet aux tâches de criticité mixte de coexister et d'exécuter en harmonie. De plus, ça permet aux tâches critiques de maintenir leurs temps d'exécution au prix de tâches de faible criticité qui seront ralenties ou arrêtées. Cette thèse vise à fournir des méthodes et des mécanismes dans le but de contribuer aux axes de prédictibilité, de sécurité et de criticité mixte dans les architectures Manycore basées sur Noc. En outre, l'incitation consiste à relever conjointement les défis dans ces trois axes en tenant compte de leur impact mutuel. Chaque axe a été étudié individuellement, mais très peu de recherche prend en compte leur interdépendance. Cette fusion des aspects est de plus en plus intrinsèque dans des domaines tels que Internet-of-Things, Cyber-Physical Systems (CPS), véhicules connectés et autonomes qui gagnent de l'élan. La raison en est leur haut degré de connectivité qui crée une grande surface d'exposition ainsi que leur présence croissante qui rend l'impact des attaques sévère et visible. Les contributions de cette thèse consistent en une méthode pour fournir une prédictibilité aux flux dans le NoC, un mécanisme pour la sécurité du NoC et une boîte à outils pour la génération de trafic utilisée pour l'analyse comparative. La première contribution est une adaptation de l'approche de la trajectoire traditionnellement utilisée dans les réseaux avioniques (AFDX) pour calculer le WCET. Dans cette thèse, nous identifions les différences et les similitudes dans l'architecture NoC et modifions l'approche de la trajectoire afin de calculer le WCTT des flux NoC. La deuxième contribution est un mécanisme qui permet de détecter les attaques de DoS et d'atténuer leur impact dans un ensemble des flux de criticité mixte. Plus précisément, un mécanisme surveille le NoC et lors de la détection d'un comportement anormal, un deuxième mécanisme d'atténuation s'active. Ce dernier applique des limites de trafic à la source et restreint le taux auquel le NoC est occupé. Cela atténuera l'impact de l'attaque, garantissant la disponibilité des ressources pour les tâches de haute criticité. Finalement NTGEN, est un outil qui peut générer automatiquement des jeux des flux aléatoires mais qui provoquent une occupation NoC prédéterminée. Ces ensembles sont ensuite injectés dans le NoC et les informations sont collectées en fonction de la latence / The evolution of Systems-on-Chip (SoCs) is rapid and the number of processors has increased transitioning from Multi-core to Manycore platforms. In such platforms, the interconnect architecture has also shifted from traditional buses to Networks-on-Chip (NoC) in order to cope with scalability. NoCs allow the processors to exchange information with memory and peripherals during task execution and enable multiple communications in parallel. NoC-based platforms are also present in embedded systems, characterized by requirements like predictability, security and mixed-criticality. In order to enable such features in existing commercial platforms it is necessary to take into consideration the NoC which is a key element with an important impact to a SoC's performance. A task exchanges information through the NoC and as a result, its execution time depends on the transmission time of the flows it generates. By calculating the Worst Case Transmission Time (WCTT) of flows in the NoC, a step is made towards the calculation of the Worst Case Execution Time (WCET) of a task. This contributes to the overall predictability of the system. Similarly by leveraging arbitration and traffic policies in the NoC it is possible to provide security guarantees against compromised tasks that might try to saturate the system's resources (DoS attack). In safety critical systems, a distinction of tasks in relation to their criticality level, allows tasks of mixed criticality to co-exist and execute in harmony. In addtition, it allows critical tasks to maintain their execution times at the cost of tasks of lower criticality that will be either slowed down or stopped. This thesis aims to provide methods and mechanisms with the objective to contribute in the axes of predictability, security and mixed criticality in NoC-based Manycore architectures. In addition, the incentive is to jointly address the challenges in these three axes taking into account their mutual impact. Each axis has been researched individually, but very little research takes under consideration their interdependence. This fusion of aspects is becoming more and more intrinsic in fields like the Internet-of-Things, Cyber-Physical Systems (CPSs), connected and autonomous vehicles which are gaining momentum. The reason being their high degree of connectivity which is creates great exposure as well as their increasing presence which makes attacks severe and visible. The contributions of this thesis consist of a method to provide predictability to a set of flows in the NoC, a mechanism to provide security properties to the NoC and a toolkit for traffic generation used for benchmarking. The first contribution is an adaptation of the trajectory approach traditionally used in avionics networks (AFDX) to calculate WCET. In this thesis, we identify the differences and similarities in NoC architecture and modify the trajectory approach in order to calculate the WCTT of NoC flows. The second contribution is a mechanism that detects DoS attacks and mitigates their impact in a mixed criticality set of flows. More specifically, a monitor mechanism will detect abnormal behavior, and activate a mitigation mechanism. The latter, will apply traffic shaping at the source and restrict the rate at which the NoC is occupied. This will limit the impact of the attack, guaranteeing resource availability for high criticality tasks. Finally NTGEN, is a toolkit that can automatically generate random sets of flows that result to a predetermined NoC occupancy. These sets are then injected in the NoC and information is collected related to latency

The wide variety of interconnection structures presently nowadays for SoC (Systemon- Chip), bus and networks-on-Chip NoCs, each of them with a wide set of setup parameters, provides a huge amount of design alternatives. Although the interconnection structure is a key SoC component, there are few design tools in order to set the appropriate configuration parameters for a given application. An efficient SoC project may comply an exploration stage among the possible solutions for the communication structure, during the first steps of the design process. The absence of appropriate tools for that exploration makes critical the designer?s judgment. The present study aims to enhance the communication SoC structure design area, when a NoC is used. This work proposes a methodology that allows the establishment of the NoC communication parameters using a high level model (SystemC TLM timed). Our approach analyzes and evaluates the NoC performance under a wide variety of traffic conditions. The experimental stage was conducted employing a model of a net represented by a SystemC TLM timed (Hermes_Temp). Parametric and pseudo-random generators control the network traffic. The analysis was carried on with a tool designed for these purpose, which generates a group of performance metrics. The results allow to elucidate the global and inner network behavior. The performance values are useful for the heterogeneous and homogeneous NoC design projects, improving the performance evaluation studies scope. / The wide variety of interconnection structures presently nowadays for SoC (Systemon- Chip), bus and networks-on-Chip NoCs, each of them with a wide set of setup parameters, provides a huge amount of design alternatives. Although the interconnection structure is a key SoC component, there are few design tools in order to set the appropriate configuration parameters for a given application. An efficient SoC project may comply an exploration stage among the possible solutions for the communication structure, during the first steps of the design process. The absence of appropriate tools for that exploration makes critical the designer?s judgment. The present study aims to enhance the communication SoC structure design area, when a NoC is used. This work proposes a methodology that allows the establishment of the NoC communication parameters using a high level model (SystemC TLM timed). Our approach analyzes and evaluates the NoC performance under a wide variety of traffic conditions. The experimental stage was conducted employing a model of a net represented by a SystemC TLM timed (Hermes_Temp). Parametric and pseudo-random generators control the network traffic. The analysis was carried on with a tool designed for these purpose, which generates a group of performance metrics. The results allow to elucidate the global and inner network behavior. The performance values are useful for the heterogeneous and homogeneous NoC design projects, improving the performance evaluation studies scope.

The tetratricopeptide repeat (TPR) motif contains 34 amino acids forming a helix-turn-helix structure. Different numbers of tandem TPR motifs assemble to form a TPR domain, thereby generating a polypeptide-binding interaction surface. The TPR domain provides a scaffold for mediating protein-protein interactions. Proteins that contain TPR domains exist in a broad range of organisms. These proteins have various functions. Cyclophilin 40 (Cyp40) and C-terminal Hsc70 interaction protein (CHIP) are two typical members of the family of TPR-containing proteins. Both proteins have the ability to bind the molecular chaperones Hsp70 and Hsp90. In most cases, TPR domains act as a scaffold to link chaperone and substrate or multi-protein complexes. Recent evidence suggests that Hsp90 binding to TPR domains can change the overall protein conformation but the allosteric mechanism triggered by ligand binding to the TPR domain remained unknown. This study focuses on using biophysical methods on the two TPR domain containing proteins Cyp40 and CHIP. In particular, this study reveals how the binding of the molecular chaperones Hsp70/90 to the TPR domains of Cyp40 and CHIP influences protein conformation and function. Here we show how conformational changes of the TPR domains affect structure and activity of Cyp40 and CHIP. By using biophysical methods, including thermal denaturation assay (TDA), differential scanning calorimetry (DSC), hydrogen deuterium exchange with mass spectrometry (HDX-MS) and small angle X-ray scattering (SAXS), together with enzymatic assays, we showed that (1) heat shock proteins allosterically affect the enzyme activity of both Cyp40 and CHIP, (2) heat shock proteins bind to the TPR domains of both Cyp40 and CHIP; (3) the binding increases the thermostability of both proteins. Further, by mutating an essential lysine in the TPR1 domain of both proteins (K30 for CHIP, and K227 for Cyp40) to alanine, the thermostability was significantly affected. The SAXS data showed in addition of the SRMEEVD peptide reduced the flexibility of CHIP. HDX-MS experiments suggest that the dynamic alteration due to binding with the Hsp90 peptide or the mutations further reduce the flexibility of the catalytic domains of both proteins. The results imply that the allosteric effects on the enzymatic activity are consequences of dynamic changes of the TPR domains. Hsp70 was also found to bind less tightly to CHIP-K30A than to wild-type CHIP, and thus showed less inhibition of enzymatic activity. These results further confirmed the discovery, that the dynamics of TPR domains allosterically affect enzymatic activity.

Huang, Lin. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2011. / Includes bibliographical references (leaves 218-232). / Abstracts in English and Chinese. / Abstract --- p.i / Acknowledgement --- p.iv / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Preface --- p.1 / Chapter 1.2 --- Background --- p.5 / Chapter 1.3 --- Contributions --- p.6 / Chapter 1.3.1 --- Lifetime Reliability Modeling --- p.6 / Chapter 1.3.2 --- Simulation Framework --- p.7 / Chapter 1.3.3 --- Applications --- p.9 / Chapter 1.4 --- Thesis Outline --- p.10 / Chapter I --- Modeling --- p.12 / Chapter 2 --- Lifetime Reliability Modeling --- p.13 / Chapter 2.1 --- Notation --- p.13 / Chapter 2.2 --- Assumption --- p.16 / Chapter 2.3 --- Introduction --- p.16 / Chapter 2.4 --- Related Work --- p.19 / Chapter 2.5 --- System Model --- p.21 / Chapter 2.5.1 --- Reliability of A Surviving Component --- p.22 / Chapter 2.5.2 --- Reliability of a Hybrid k-out-of-n:G System --- p.26 / Chapter 2.6 --- Special Cases --- p.31 / Chapter 2.6.1 --- Case I: Gracefully Degrading System --- p.31 / Chapter 2.6.2 --- Case II: Standby Redundant System --- p.33 / Chapter 2.6.3 --- Case III: l-out-of-3:G System with --- p.34 / Chapter 2.7 --- Numerical Results --- p.37 / Chapter 2.7.1 --- Experimental Setup --- p.37 / Chapter 2.7.2 --- Experimental Results and Discussion --- p.40 / Chapter 2.8 --- Conclusion --- p.43 / Chapter 2.9 --- Appendix --- p.44 / Chapter II --- Simulation Framework --- p.47 / Chapter 3 --- AgeSim: A Simulation Framework --- p.48 / Chapter 3.1 --- Introduction --- p.48 / Chapter 3.2 --- Preliminaries and Motivation --- p.51 / Chapter 3.2.1 --- Prior Work on Lifetime Reliability Analysis of Processor- Based Systems --- p.51 / Chapter 3.2.2 --- Motivation of This Work --- p.53 / Chapter 3.3 --- The Proposed Framework --- p.54 / Chapter 3.4 --- Aging Rate Calculation --- p.57 / Chapter 3.4.1 --- Lifetime Reliability Calculation --- p.58 / Chapter 3.4.2 --- Aging Rate Extraction --- p.60 / Chapter 3.4.3 --- Discussion on Representative Workload --- p.63 / Chapter 3.4.4 --- Numerical Validation --- p.65 / Chapter 3.4.5 --- Miscellaneous --- p.66 / Chapter 3.5 --- Lifetime Reliability Model for MPSoCs with Redundancy --- p.68 / Chapter 3.6 --- Case Studies --- p.70 / Chapter 3.6.1 --- Dynamic Voltage and Frequency Scaling --- p.71 / Chapter 3.6.2 --- Burst Task Arrival --- p.75 / Chapter 3.6.3 --- Task Allocation on Multi-Core Processors --- p.77 / Chapter 3.6.4 --- Timeout Policy on Multi-Core Processors with Gracefully Degrading Redundancy --- p.78 / Chapter 3.7 --- Conclusion --- p.79 / Chapter 4 --- Evaluating Redundancy Schemes --- p.83 / Chapter 4.1 --- Introduction --- p.83 / Chapter 4.2 --- Preliminaries and Motivation --- p.85 / Chapter 4.2.1 --- Failure Mechanisms --- p.85 / Chapter 4.2.2 --- Related Work and Motivation --- p.86 / Chapter 4.3 --- Proposed Analytical Model for the Lifetime Reliability of Proces- sor Cores --- p.88 / Chapter 4.3.1 --- "Impact of Temperature, Voltage, and Frequency" --- p.88 / Chapter 4.3.2 --- Impact of Workloads --- p.92 / Chapter 4.4 --- Lifetime Reliability Analysis for Multi-core Processors with Vari- ous Redundancy Schemes --- p.95 / Chapter 4.4.1 --- Gracefully Degrading System (GDS) --- p.95 / Chapter 4.4.2 --- Processor Rotation System (PRS) --- p.97 / Chapter 4.4.3 --- Standby Redundant System (SRS) --- p.98 / Chapter 4.4.4 --- Extension to Heterogeneous System --- p.99 / Chapter 4.5 --- Experimental Methodology --- p.101 / Chapter 4.5.1 --- Workload Description --- p.102 / Chapter 4.5.2 --- Temperature Distribution Extraction --- p.102 / Chapter 4.5.3 --- Reliability Factors --- p.103 / Chapter 4.6 --- Results and Discussions --- p.103 / Chapter 4.6.1 --- Wear-out Rate Computation --- p.103 / Chapter 4.6.2 --- Comparison on Lifetime Reliability --- p.105 / Chapter 4.6.3 --- Comparison on Performance --- p.110 / Chapter 4.6.4 --- Comparison on Expected Computation Amount --- p.112 / Chapter 4.7 --- Conclusion --- p.118 / Chapter III --- Applications --- p.119 / Chapter 5 --- Task Allocation and Scheduling for MPSoCs --- p.120 / Chapter 5.1 --- Introduction --- p.120 / Chapter 5.2 --- Prior Work and Motivation --- p.122 / Chapter 5.2.1 --- IC Lifetime Reliability --- p.122 / Chapter 5.2.2 --- Task Allocation and Scheduling for MPSoC Designs --- p.124 / Chapter 5.3 --- Proposed Task Allocation and Scheduling Strategy --- p.126 / Chapter 5.3.1 --- Problem Definition --- p.126 / Chapter 5.3.2 --- Solution Representation --- p.128 / Chapter 5.3.3 --- Cost Function --- p.129 / Chapter 5.3.4 --- Simulated Annealing Process --- p.130 / Chapter 5.4 --- Lifetime Reliability Computation for MPSoC Embedded Systems --- p.133 / Chapter 5.5 --- Efficient MPSoC Lifetime Approximation --- p.138 / Chapter 5.5.1 --- Speedup Technique I - Multiple Periods --- p.139 / Chapter 5.5.2 --- Speedup Technique II - Steady Temperature --- p.139 / Chapter 5.5.3 --- Speedup Technique III - Temperature Pre- calculation --- p.140 / Chapter 5.5.4 --- Speedup Technique IV - Time Slot Quantity Control --- p.144 / Chapter 5.6 --- Experimental Results --- p.144 / Chapter 5.6.1 --- Experimental Setup --- p.144 / Chapter 5.6.2 --- Results and Discussion --- p.146 / Chapter 5.7 --- Conclusion and Future Work --- p.152 / Chapter 6 --- Energy-Efficient Task Allocation and Scheduling --- p.154 / Chapter 6.1 --- Introduction --- p.154 / Chapter 6.2 --- Preliminaries and Problem Formulation --- p.157 / Chapter 6.2.1 --- Related Work --- p.157 / Chapter 6.2.2 --- Problem Formulation --- p.159 / Chapter 6.3 --- Analytical Models --- p.160 / Chapter 6.3.1 --- Performance and Energy Models for DVS-Enabled Pro- cessors --- p.160 / Chapter 6.3.2 --- Lifetime Reliability Model --- p.163 / Chapter 6.4 --- Proposed Algorithm for Single-Mode Embedded Systems --- p.165 / Chapter 6.4.1 --- Task Allocation and Scheduling --- p.165 / Chapter 6.4.2 --- Voltage Assignment for DVS-Enabled Processors --- p.168 / Chapter 6.5 --- Proposed Algorithm for Multi-Mode Embedded Systems --- p.169 / Chapter 6.5.1 --- Feasible Solution Set --- p.169 / Chapter 6.5.2 --- Searching Procedure for a Single Mode --- p.171 / Chapter 6.5.3 --- Feasible Solution Set Identification --- p.171 / Chapter 6.5.4 --- Multi-Mode Combination --- p.177 / Chapter 6.6 --- Experimental Results --- p.178 / Chapter 6.6.1 --- Experimental Setup --- p.178 / Chapter 6.6.2 --- Case Study --- p.180 / Chapter 6.6.3 --- Sensitivity Analysis --- p.181 / Chapter 6.6.4 --- Extensive Results --- p.183 / Chapter 6.7 --- Conclusion --- p.185 / Chapter 7 --- Customer-Aware Task Allocation and Scheduling --- p.186 / Chapter 7.1 --- Introduction --- p.186 / Chapter 7.2 --- Prior Work and Problem Formulation --- p.188 / Chapter 7.2.1 --- Related Work and Motivation --- p.188 / Chapter 7.2.2 --- Problem Formulation --- p.191 / Chapter 7.3 --- Proposed Design-Stage Task Allocation and Scheduling --- p.192 / Chapter 7.3.1 --- Solution Representation and Moves --- p.193 / Chapter 7.3.2 --- Cost Function --- p.196 / Chapter 7.3.3 --- Impact of DVFS --- p.198 / Chapter 7.4 --- Proposed Algorithm for Online Adjustment --- p.200 / Chapter 7.4.1 --- Reliability Requirement for Online Adjustment --- p.201 / Chapter 7.4.2 --- Analytical Model --- p.203 / Chapter 7.4.3 --- Overall Flow --- p.204 / Chapter 7.5 --- Experimental Results --- p.205 / Chapter 7.5.1 --- Experimental Setup --- p.205 / Chapter 7.5.2 --- Results and Discussion --- p.207 / Chapter 7.6 --- Conclusion --- p.211 / Chapter 7.7 --- Appendix --- p.211 / Chapter 8 --- Conclusion and Future Work --- p.214 / Chapter 8.1 --- Conclusion --- p.214 / Chapter 8.2 --- Future Work --- p.215 / Bibliography --- p.232

Tese de mestrado integrado. Engenharia Electrotécnica e de Computadores. Faculdade de Engenharia. Universidade do Porto. 2010

<p>In this report the two-tone PLL circuit intended for on-chip test of RF blocks is presented. The primary application is the third order intermodulation test (TOI), vital for RF front-ends. If the spectral analysis can also be completed by DSP available on the chip or on board, it provides a built in self-test (BiST) which can replace costly test instrumentation (ATE). The advantage of the designed two-tone PLL is that it practically prevents the locking effect while keeping the two oscillation frequencies close. Also by careful design the possible intermodulation distortion of the two-tone stimulus can be avoided.</p><p>The two-tone PLL has been designed and verified at the system level using Verilog-A models in Cadence ^TM.Besides, two building blocks of the PLL were implemented at the circuit level in 90nm CMOS technology. The obtained results are promising in terms of a practical two-tone BiST implementation.</p>

<p>This project targets the problems with design and implementation of Single Instruction </p><p>Multiple Data (SIMD) architectures in System-on-Chip (SoC), with the goal to construct </p><p>a reconfigurable framework in VHDL to ease this process. The resulting framework should </p><p>be implemented on an FPGA and its usability tested. The main parts of a SIMD archi- </p><p>tecture was identified to be the Control Unit (CU), the Processing Elements (PE) and </p><p>the Interconnection Network (ICN), and a framework was constructed with these parts </p><p>as the main building blocks. The constructed framework is reconfigurable in data width, </p><p>memory size, number of PEs, topology and instruction set. To test ease of use and per- </p><p>formance of the system a FIR-filter application was implemented. The scalability of the </p><p>system and its different parts has been measured and comparisons are illustrated.</p>

With the progress of the semiconductor technology, the devices scaling down to submicron range leads to increase I/Os number and very fine pitch IC package type; such as BGA, Flip Chip and CSP type packages. For Flip chip packaging, the solder bumping process act as the role of I/O interconnection instead of conventational wirebonding process. The ball mounted process is defined as the solder ball mounted on the Flip Chip Ball Grad Array (FC-BGA) substrate for solder bumping. In this study, how to improve the strength of ball-shear; residual tin capability and capability of process kit are the main issues to be investigated for the ball mounted process. To analyze the root cause and to implement the corrective action are the important purpose for solving the failures occurred on the ball mounted process. The following technologies included as (1) engineering ststictic methodology; JMP (statistical software) (2) Problem solving methodology (PSM) (3) Optimizing the process window (4) Set up the main parameters to analyse in machinery (5) how to monitor the CPK capability & material properties analysis, are used for these issues. Finally, the ball mounted process has been successfully investigated and results in solving the failure of Flip Chip ball mounted process and surface mounted technology (SMT) process for assembly packaging manufacture completely.

The key to the complexity of higher organisms lies not in the number of protein coding genes they carry, but rather in the intrinsic complexity of the gene regulatory networks. The major effectors of transcriptional regulation are proteins called transcription factors, and in this thesis four papers describing genome-wide studies of seven such factors are presented, together with studies on components of the chromatin and transcriptome. In Paper I, we optimized a large-scale in vivo method, ChIP-chip, to study protein – DNA interactions using microarrays. The metabolic-disease related transcription factors USF1, HNF4a and FOXA2 were studied in 1 % of the genome, and a surprising number of binding sites were found, mostly far from annotated genes. In Paper II, a novel sequencing based method, ChIP-seq, was applied to FOXA2, HNF4a and GABPa, allowing a true genome-wide view of binding sites. A large overlap between the datasets were seen, and molecular interactions were verified in vivo. Using a ChIP-seq specific motif discovery method, we identified both the expected motifs and several for co-localized transcription factors. In Paper III, we identified and studied a novel transcription factor, ZBED6, using the ChIP-seq method. Here, we went from one known binding site to several hundred sites throughout the mouse genome. Finally, in Paper IV, we studied the chromatin landscape by deep sequencing of nucleosomal DNA, and further used RNA-sequencing to quantify expression levels, and extended the knowledge about the binding profiles for the transcription factors NFY and TCF7L2.

In the current research, an analytical chip formation model and the methodology to determine material flow data have been developed. The efforts have been made to address work hardening and thermal softening effects and allow the material to flow continuously through an opened-up deformation zone. Oxley's analysis of machining is extended to the application of various engineering materials. The basic model is extended to the simulation of end milling process and validated by comparing the predictions with experimental data for AISI1045 steel and three other materials (AL-6061, AL7075 and Ti-6Al-4V) from open literatures. The thorough boundary conditions of the velocity field in the primary shear zone are further identified and analyzed. Based on the detailed analysis on the boundary conditions of the velocity and shear strain rate fields, the thick “equidistant parallel-sided” shear zone model was revisited. A more realistic nonlinear shear strain rate distribution has been proposed under the frame of non-equidistant primary shear zone configuration, so that all the boundary conditions can be satisfied. Based on the developed model, inverse analysis in conjugation of genetic algorithm based searching scheme is developed to identify material flow stress data under the condition of metal cutting. ii On the chip-tool interface, The chip-tool interface is assumed to consist of the secondary shear zone and elastic friction zone(i.e. sticking zone and sliding zone). The normal stress distribution over the entire contact length is represented by a power law equation, in which the exponent is determined based on the force and moment equilibrium. The shear stress distribution for the entire contact length is assumed to be independent of the normal stress. The shear stress is assumed to be constant for the plastic contact region and exponentially distributed over the elastic contact region, with the maximum equal to the shear flow stress at the end of sticking zone and zero at the end of total contact. The total contact length is derived as a function governed by the shape of normal stress distribution. The length of the sticking zone is determined as the distance from the cutting edge to the location where the local coefficient of friction reaches a critical value that initiates the bulk yield of the chip. Considering the shape of the secondary shear zone, the length of the sticking zone can also be determined by angle relations. The maximum thickness of the secondary shear zone is determined by the equality of the sticking lengths calculated by two means. With an arbitrary input of the sliding friction coefficient, various processing parameters as well as contact stress distributions during orthogonal metal cutting can be obtained. / UOIT