Flip chip interconnections have superior performance for microwave applications compared to wire bond interconnections because of their reduced parasitics, more compact architecture, and flexibility in laying out flip chip bond pads. Reduction in interconnect parasitics enables these interconnects to support broadband signals, therefore increasing the bandwidth capabilities of flip chip-assembled systems. Traditional flip chip designs provide mechanical and electrical connections from a top chip to a carrier substrate with rigid solder joints. For heterogeneous assemblies, flip chip connections suffer from thermo-mechanical failures caused by coefficient of thermal expansion mismatches. As an alternative, flexible flip chip interconnections incorporating a metal, which is liquid at room temperature, mitigates the possibility of such thermo-mechanical failures. Additionally, liquid metal, flip chip interconnections allow for room temperature assembly, simplifying assembly and rework processes. This dissertation focuses on the design and characterization of liquid metal interconnections, specifically using Galinstan, an alloy of gallium indium and tin, for the heterogeneous assembly of active monolithic microwave integrated circuits (MMICs) onto a CTE mismatched substrate. Carrier substrates designed for liquid metal transitions were fabricated on high resistivity Si and on three dimensional copper structures. The three dimensional copper structures were fabricated in the PolyStrata™ process. Individual MMIC chips were post-processed to mate with carrier substrates in a liquid metal, flip chip configuration. S-parameter measurements of prototype MMIC assemblies with liquid metal, flip chip interconnections showed an average transition loss of 0.7dB over the MMIC's frequency of operation (4.9 - 8.5 GHz). Passive assemblies were also fabricated to characterize the power and temperature performance of liquid metal transitions. Liquid metal interconnections show excellent power handling, maintaining consistent RF performance while transmitting 100W of continuous wave power for an hour. Liquid metal interconnections were also tested following 200 temperature cycles over the -140°C – 125°C range. A comparison of S parameter measurements taken before and after temperature cycling, over a frequency range of 10MHz - 40GHz showed no significant changes in performance. These passive assemblies were also used to develop a lumped element model of the interconnection which is useful for the verification the interconnection\'s performance and for comparison of liquid metal interconnection parasitic to wire bond and flip chip interconnect parasitics. The experimental results presented in this dissertation confirm that liquid metal interconnect are viable for wider use in military and commercial applications. In the future, additional environmental testing and further refinement of the processing flow, such as improved contact metallurgy, are needed to make this interconnect approach more viable for large volume manufacturing. / Ph. D.

Single particle electron microscopy (EM) allows us to examine the molecular world and gain insights into protein structures implicated in human disease. Visualizing the 3D architecture of the macromolecules can inform drug design and preventative care. While X-ray crystallography and NMR are able to resolve atomic structures, the methodology is better suited for smaller structures with limited flexibility. Single particle EM allows us analyze larger structures that have inherent flexibility. Protein structures can broadly be categorized as symmetry or asymmetric. There are computational advantages when analyzing symmetrical structures. Specifically, structural information can be extrapolated from fewer vantage points. Thus, symmetrical macromolecules are an advantageous for pioneering new methodologies in single particle EM. Rotavirus double layered particles (DLPs) are large macromolecular complexes that display icosahedral symmetry. Previous studies have led to a high resolution structure of transcriptionally inactive rotavirus frozen in time. However, to more fully understand rotavirus we need to examine the structure under transcriptionally active conditions. To expand our understanding, we first evaluated these viral assemblies using cryo-EM under active and inactive conditions. We found both internal and external structural differences. Based on these findings we sought to further our understanding of these nano-machines by developing a liquid cell environment to evaluate their dynamics over time. Our research not only developed a new methodology to evaluate active particles over time, we also found that the mobility of the DLPs were directly correlated to the level of transcriptional activity. When analyzing asymmetrical and flexible protein complexes previous studies have utilized methodologies to limit the proteins' conformational variability. While this does allow for a higher resolution structure, it limits our understanding to a specific orientation and compromises the biological insights. BRCA1 is an asymmetric protein containing a large flexible region and is important in the prevention of breast cancer. We utilize silicon nitride microchips with integrated wells and decorated with a lipid monolayer to capture and image BRCA1 complexes. This imaging platform minimizes heterogeneity and ensures the sample quality while not biasing confirmation. Thus, allowing for high resolution cryo-EM imaging of flexible native proteins. We were able to examine BRCA1 complexes from cells at both the primary and metastatic sites. Our ability to visualize these proteins in their native form provide insights into the variability of BRCA1 in disease progression. We found that BRCA1 complexes isolated from metastatic cells have additional density in the C-terminal domain. Our data suggests this density it due an interaction with p53. Overall, our methodologies highlight the power of single particle EM for studying protein complexes. Furthermore, our findings emphasize the importance of examining protein complexes in their native state. / PHD / Single particle electron microscopy (EM) allows us to examine the molecular world and gain insights into protein structures implicated in human disease. Visualizing the 3D architecture of macromolecules can inform drug design and preventative care. While X-ray crystallography and NMR are able to resolve atomic structures, the methodology is better suited for smaller structures with limited flexibility. Single particle EM allow us analyze larger structures that have inherent flexibility. Protein structures can broadly be categorized as symmetry or asymmetric. There are computational advantages when analyzing symmetrical structures. Specifically, structural information can be extrapolated from fewer vantage points. Thus, symmetrical macromolecules are an advantageous for pioneering new methodologies in single particle EM. Rotavirus double layered particles (DLPs) are large, highly symmetrical macromolecular complexes that represent an ideal model system for developing technology. Previous studies have led to a high resolution structure of inactive rotavirus DLP frozen in time. However, to more fully understand rotavirus we need to examine the structure under active conditions. To expand our understanding, we first evaluated these viral assemblies using cryo-EM under active and inactive conditions. We found structural differences. Based on these findings we sought to further our understanding of these nano-machines by developing a liquid cell environment to evaluate their dynamics over time. Our new methodology revealed new insights into the mobility of the DLPs. When analyzing asymmetrical and flexible protein complexes previous studies have utilized methodologies to limit the proteins’ movement. While this does allow for a higher resolution structure, it limits our understanding to a specific orientation and compromises the biological insights. BRCA1 is a highly flexible asymmetric protein implicated in the development of breast cancer. We utilize specialized microchips to capture and image BRCA1 complexes. This imaging platform ensures sample quality and allows for high resolution cryoEM imaging of flexible native proteins. We were able to examine BRCA1 complexes from cells at both the primary and metastatic sites. Our ability to visualize these proteins in their native form provide insights into the variability of BRCA1 in disease progression. Our data found that BRCA1 complexes isolated from metastatic cells are structurally different than those at the primary site. Overall, our methodologies highlight the power of single particle EM for studying protein complexes. Furthermore, our findings emphasize the importance of examining protein complexes in their native state.

As single-chip systems are predicted to soon contain over a billion transistors, design methodologies are evolving dramatically to account for the fast evolution of technologies and product properties. Novel methodologies feature the exploration of design alternatives early in development, the support for IPs, and early error detection — all with a decreasing time-to-market. In order to accommodate these product complexities and development needs, the modeling levels at which designers are working have quickly changed, as development at higher levels of abstraction allows for faster simulations of system models and earlier estimates of system performance while considering design trade-offs. Recent design advancements to exploit instruction-level parallelism on single-processor computer systems have become exceedingly complex, and modern applications are presenting an increasing potential to be partitioned and parallelized at the thread level. The new Single-Chip, Message-Passing (SCMP) parallel computer is a tightly coupled mesh of processing nodes that is designed to exploit thread-level parallelism as efficiently as possible. By minimizing the latency of communication among processors, memory access time, and the time for context switching, the system designer will undoubtedly observe an overall performance increase. This study presents in-depth evaluations and quantitative analyses of various design and performance aspects of SCMP through the development of abstract hardware models by following a formalized, well-defined methodology. The performance evaluations are taken through benchmark simulation while taking into account system-level communication and synchronization among nodes as well as node-level timing and interaction amongst node components. Through the exploration of alternatives and optimization of the components within the SCMP models, maximum system performance in the hardware implementation can be achieved. / Master of Science

The importance of securing hardware, particularly in the context of the Internet of Things (IoT), cannot be overstated in light of the increasing prevalence of low-level attacks. As the IoT industry continues to expand, security has become a more holistic concern, as evidenced by the wide range of attacks that we observed, from large-scale distributed denial-of-service attacks to data theft through monitoring a device's low-level behavior, such as power consumption. Traditional software-based security measures fall short in defending against the full spectrum of attacks, particularly those involving physical tampering with system hardware. This underscores the critical importance of proactively integrating attack vectors that encompass both hardware and software domains, with a particular emphasis on considering both the analog and digital characteristics of hardware. This thesis investigates system security from a hardware perspective, specifically examining how low-level circuit behavior and architectural design choices impact SRAM's data remanence and its implications for security. This dissertation not only identifies new vulnerabilities due to SRAM data remanence but also paves the way for novel security solutions in the ongoing "security arms race". I present an attack, volt boot, that executes cold-boot style short-term data remanence in on-chip SRAM without using temperature effect. This attack exploits the fact that SRAM's power bus is externally accessible and allows data retention using a simple voltage probe. Next, I present a steganography method that hides information in the SRAM exploiting long-term data remanence. This approach leverages aging-induced degradation to imprint data in SRAM's analog domain, ultimately resulting in hidden and plausibly deniable information storage in the hardware. Finally, I show how an adversary weaponizes SRAM data remanence to develop an attack on a hardware-backed security isolation mechanism. The following provides a brief overview of the three major contributions of this thesis: 1. Volt boot is an attack that demonstrates the vulnerability of on-chip SRAM due to the physical separation common in modern SoCs' power distribution networks. By probing external power pins (to the cache) of an SoC while simultaneously shutting down the main system power, Volt boot creates data retention across power cycles. On-chip SRAM can be a safe memory when the threat model considers traditional off-chip cold-boot-style attacks. This research demonstrates an alternative method for preserving information in on-chip SRAM through power cycles, expanding our understanding of data retention capabilities. Volt boot leverages asymmetrical power states (e.g., on vs. off) to force SRAM state retention across power cycles, eliminating the need for traditional cold boot attack enablers, such as low-temperature or intrinsic data retention time. 2. Invisible Bits is a hardware steganography technique that hides secret messages in the analog domain of SRAM embedded within a computing device. Exploiting accelerated transistor aging, Invisible Bits stores hidden data along with system data in an on-chip cache and provides a plausible deniability guarantee from statistical analysis. Aging changes the transistor's behavior which I exploit to store data permanently (ie long-term data remanence) in an SRAM. Invisible Bits presents unique opportunities for safeguarding electronic devices when subjected to inspections by authorities. 3. UntrustZone utilizes long-term data remanence to exfiltrate secrets from on-chip SRAM. An attacker application must be able to read retained states in the SRAM upon power cycles, but this needs changing the security privilege. Hardware security schemes, such as ARM TrustZone, erase a memory block before changing its security attributes and releasing it to other applications, making short-term data remanence attacks ineffective. That is, attacks such as Volt boot fail when hardware-backed isolation such as TEE is enforced. UntrustZone unveils a new threat to all forms of on-chip SRAM even when backed by hardware isolation: long-term data remanence. I show how an attacker systematically accelerates data imprinting on SRAM's analog domain to effectively burn in on-chip secrets and bypass TrustZone isolation. / Doctor of Philosophy / In computing systems, hardware serves as the fundamental bulwark against security breaches. The evolution in software security has compelled adversaries to seek potential vulnerabilities in the hardware.The infamous cold boot attack exemplifies such vulnerabilities, showcasing how adversaries exploit hardware to access runtime secrets, even when cryptographic algorithms protect the system's disk. In this attack, volatile main memory (DRAM) is `frozen' at extremely cold temperatures, allowing it to retain information even when disconnected from the victim machine. Subsequently, an adversary transfers this `frozen memory' to another machine to extract the victim's secrets. This classic case is among numerous sophisticated hardware vulnerabilities identified in recent years, highlighting the evolving challenge of securing hardware against ingenious attacks. This rise in hardware-based attacks across industry and academia underscores the importance of adopting a comprehensive approach to safeguard computing systems. This approach must encompass secure processor design, ensuring a trusted distribution chain, rigorous software security vetting, and protection against runtime side-channel leakage. Consequently, there is a growing emphasis in both industry and academia on prioritizing security in design decisions. My dissertation delves into the low-level hardware behaviors, particularly focusing on the data remanence phenomena of Static Random Access Memory (SRAM). By discovering new security vulnerabilities and proposing effective mitigation strategies, this thesis contributes to the ongoing effort to fortify computing systems against evolving threats that are rooted in the hardware. SRAM stands as a ubiquitous form of volatile memory found in most processors and microcontrollers, serving as a crucial component for temporary storage of instructions and data to facilitate rapid access. By design, SRAM forgets its contents upon a processor's power cycle and defaults to a state determined by low-level circuit behavior. However, this dissertation unveils the possibility of retaining on-chip information even after power cycling, leveraging inherent low-level circuit behaviors to create data retention. This revelation exposes major security implications, resulting in the following three key contributions: Firstly, I introduce the volt boot attack, which exploits the vulnerability of on-chip SRAM, particularly to physical separation in modern System on Chip (SoC) power distribution networks. We conventionally assume that on-chip SRAM is secure against off-chip cold-boot attacks, but volt boot demonstrates the feasibility of achieving a similar state without traditional prerequisites such as low temperatures or long intrinsic data retention times. Subsequently, I propose a data hiding technique---invisible Bits, which leverages accelerated device wear out to embed data into the transistors of SRAM. This method introduces a novel form of hardware-based steganography, concealing data within the analog domain alongside digital system data. Lastly, I show how accelerated device aging can be weaponized to design a sophisticated attack aimed at extracting secrets from a Trusted Execution Environment (TEE) like ARM TrustZone. While short-term data remanence attacks such as Volt boot are rendered ineffective against hardware-backed isolation enforced by TEEs, UntrustZone harnesses the methodologies and tools from preceding works to induce long-term data remanence. This poses a new threat to on-chip cryptography that stores secrets on chip, even when fortified by hardware isolation mechanisms, such as ARM TrustZone.

This thesis reports the fabrication of three dimensionally independent on-chip microchannels using a CMOS-compatible single mask deep reactive ion etching (DRIE) process for cooling 3D ICs. Three dimensionally independent microchannels are fabricated by utilizing the RIE lag effect. This allows complex microchannel configurations to be fabricated using a single mask and single silicon etch step. Furthermore, the microchannels are sealed in one step by low temperature oxide deposition. The micro-fin channels heat transfer characteristics are similar to previously published channel designs by being capable of removing 185 W/cm2 before the junction temperatures active elements exceed 85°C. To examine the heat transfer characteristics of this proposed on-chip cooler, different channel geometries were simulated using computational fluid dynamics. The channel designs were simulated using 20°C water at different flow rates to achieve a laminar flow regime with Reynolds numbers ranging from 200 to 500. The steady state simulations were performed using a heat flux of 100 W/cm2. Simulation results were verified using fabricated test chips. A micro-fin geometry showed to have the highest heat transfer capability and lowest simulated substrate temperatures. While operating with a Reynolds number of 400, a Nusselt number per input energy (Nu/Q) of 0.24 W-1 was achieved. The micro-fin geometry is also capable of cooling a substrate with a heat flux of 100W/cm2 to 45ºC with a Reynolds number of 525. These channels also have a lower thermal resistance compared to external heat sinks because there is no heat spreader or thermal interface material layer. / Master of Science

Increased costs of fossil fuels, regulatory policies, and investments by federal and state governments have caused increased interest and incentive for the use of wood as a renewable form of energy. As a result, landowners and forest managers are considering chipping whole trees and harvesting residues as a means to meet increased demand of wood chips as a renewable source of energy. However, the profitability, productivity gains, and sustainability of these alternative harvesting methods continue to be an area of research. The objective of this study was to compare two biomass harvesting treatments with regard to the characteristics of the chips they produced, chipper productivity, nutrient removals, and site disturbance. The first biomass harvesting treatment was an integrated harvest where roundwood was merchandized and hauled to the appropriate mill and limbs, tops, and small stems (residues) were chipped for hog fuel. The second biomass harvesting treatment simulated a scenario where biomass markets were competing with pulpwood markets and landowners could choose to sell wood for energy or pulp wood. In this treatment whole trees and small stems were chipped for hog fuel. A third harvesting treatment was a conventional roundwood harvest where no wood was chipped, and this treatment was used as a control for comparison of nutrient removals and site disturbance. The chips produced from both harvesting treatments were very similar, but those produced from whole trees tended to be slightly smaller than those produced from residues. Chipper productivity was significantly higher when chipping whole trees and it was also much more efficient in terms of fuel use. Estimations of nutrient removals showed that there was very little difference in the amount of nutrient removed from the biomass harvesting treatments, but both treatments removed significantly more N and Ca than the conventional roundwood harvesting treatment. There was significantly more downed and standing material left on the site after harvesting in the conventional treatment, but this did not translate into a large amount of additional nutrients left on the site. There was little difference in soil disturbance between all three treatments, and due to the dry soil conditions during harvesting, there was very little visual soil disturbance at all during harvesting. / Master of Science

Conventional pre-clinical drug screening, reliant on 2D cell cultures and animal studies, faces challenges—the former lacks biological complexity, and the latter lacks predictability due to differences between animals and humans from genetic to functional levels. Organ-on-chip technologies have evolved to bridge the gap between preclinical and clinical trials, necessitating human cells for precise predictions of human responses. Considering the significance of the vascular system in various diseases, incorporating vascular units into organ-on-chip devices is critical. For effective drug discovery using vessels-on-chips, achieving high-throughput and consistency between samples is crucial. However, many vessels-on-chips are manually handled during preparation and data collection, reducing throughput and increasing sample-to-sample variations. The conventional closed microfluidic chip format further impedes accessibility, hindering automation. This thesis focuses on two high-throughput micro-vessel models replicating vascular functions under perfusion in a 384-well plate format. These open-top models allow automated preparation and examination, enhancing efficiency in compound screening. The first model features a self-assembled perfusable micro-vascular network on a 384-well plate, co-culturing endothelial cells (EC) with stromal cells in a hydrogel. Automated using a robotic system and a fluorescent plate reader, it supports organ-specific functions and enables nanoparticle transport to target tissues. Utilized for testing cancer therapeutic drugs, it demonstrates dose-related responses in vascular permeability and architectures. The second model is dedicated to crafting micro-vessels of consistent quality for biological testing and disease modeling. It employs a sacrificial material for pre-designed tubular shapes for EC seeding. The integration of automated processes and a straight channel design minimizes sample discrepancies. Furthermore, a tri-culture system enhances barrier integrity, enabling effective drug screening that distinguishes between vasculotoxic and non-vasculotoxic agents with notable sensitivity and specificity. Looking ahead, there is potential to further refine these models to encompass a broader range of vascular diseases, which could lead to novel insights and therapeutic targets. / Thesis / Doctor of Philosophy (PhD) / In clinical trials, a staggering 90% of drugs fail during testing in people. Traditional preclinical drug screening methods rely on culturing human cells on flat surfaces or using animal models, both fraught with limitations such as lacking structural complexity or having DNA differences from humans. Addressing this issue could notably reduce efforts and costs. This thesis is dedicated to advancing preclinical drug testing through micro-vessel models. It focuses on constructing 3D vessels using human cells, offering a more accurate representation of human physiology. Two models are discussed: one with self-assembled vessels featuring complex structures, and another emphasizing sacrificial materials to design simpler vascular shapes, ensuring consistency in testing. By leveraging these innovative models, researchers can subject various drugs to micro-vessels constructed in vitro, enabling them to predict their effects in humans. This approach has the potential to transform drug testing methodologies, moving towards the utilization of artificial human organ models.

Master of Science / Department of Civil Engineering / Mustaque A. Hossain / Preventive maintenance strategies are applied to pavement to bring it back to appropriate serviceability when it starts to deteriorate soon after construction due to several factors, e.g., traffic loading, deterioration of pavement materials, and climatic effects. In recent years, more and more highway agencies are adopting preventive maintenance strategies and moving away from rehabilitation actions since rehabilitating pavements at near failure is not a cost-effective pavement management technique. A variety of preventive maintenance treatments or thin surface treatments are available to bring pavements back to appropriate serviceability for road users. The Kansas Department of Transportation (KDOT) has adopted several preventive maintenance treatments including thin overlay, ultra-thin bonded asphalt surface (Nova Chip), chip seal, and slurry seal. This thesis discusses the effectiveness of thin surface or preventive maintenance treatments applied in 2007 on 16 highway sections in Kansas. Three types of thin surface treatments, 25-mm Hot-Mix-Asphalt (1” HMA) overlay, ultra-thin bonded asphalt surface (Nova Chip), and chip seal, were examined in this study. These treatments were applied on three types of surface preparation, namely, bare surface, 25-mm surface recycle (1” SR), and 50-mm surface recycle (2” SR). Effectiveness of the thin surface or preventive maintenance treatments for mitigating typical distresses and enhancing pavement performance was evaluated by conducting before-and-after (BAA) comparisons. All data required for this study were extracted from the Pavement Management Information System (PMIS) database of KDOT. It was observed that transverse and fatigue cracking significantly decreased and rutting conditions were improved after the thin surface treatments were applied. Roughness conditions were observed to be better on the highway test sections treated with 25-mm (1”) HMA and Nova Chip, while the effects of chip seals on reducing roughness were not as obvious. Benefit and performance levels of the pavements were observed to rise after the thin surface treatments were applied. The Hamburg Wheel-Tracking Device (HWTD) test was conducted on core samples taken from the highway sections under this study. Laboratory test results showed that most projects exceeded the maximum rut-depth limit (20 mm) specified for 20,000 wheel passes, and the number of wheel passes to failure varied significantly among the projects. Cores from only three projects, two treated with Nova Chip and one with 25-mm (1”) HMA, carried 20,000 wheel passes without exceeding the maximum rut limit of 20 mm (0.8 inch). Pair-wise comparisons or contrasts among the treatments were also performed with the statistical analysis software, SAS. Air void of the HWTD test cores was found to be a significant factor affecting performance of thin surface treatments. The results also revealed that performance was significantly affected by the type of treatment and surface preparation.

Chip-package interaction (CPI) has become a critical reliability issue for flip-chip packaging of Cu/low-k chip with organic substrate. The thermo-mechanical deformation and stress develop inside the package during assembly and subsequent reliability tests due to the mismatch of the coefficients of thermal expansion (CTEs) between the chip and the substrate. The thermal residual stress causes many mechanical reliability issues in the solder joints and the underfill layer between die and substrate, such as solder fatigue failure and underfill delamination. Moreover, the thermo-mechanical deformation of the package can be directly coupled into the Cu/low-k interconnect, inducing large local stresses to drive interfacial crack formation and propagation. The thermo-mechanical reliability risk is further aggravated with the implementation of ultra low-k dielectric for better electrical performance and the mandatory change from Pb-containing solders to Pb-free solders for environmental safety. These CPI-induced reliability issues in flip-chip packaging of Cu/low-k chips are investigated in this dissertation at both chip level and package level using high-resolution Moiré interferometry and Finite Element Analysis (FEA). Firstly, the thermo-mechanical deformation in flip-chip packages is analyzed using high-resolution Moiré interferometry. The effect of underfill properties on package warpage is studied and followed by a strategy study of proper underfill selection to improve solder fatigue life time and reduce the risk of interfacial delamination in underfill and low-k interconnects under CPI. The chip-package interaction is found to maximize at the die attach step during assembly and becomes most detrimental to low-k chip reliability because of the high thermal load generated by the solder reflow process before underfilling. A three-dimensional (3D) multilevel sub-modeling method combined with modified virtual crack closure (MVCC) technique is employed to investigate the CPI-induced interfacial delamination in Cu/low-k interconnects. It is first focused on the effects of dielectrics and solder materials on low-k interconnect reliability and then extended to the scaling effect where the reduction of the interconnect dimension is accompanied with an increased number of metal levels and the implementation of ultralow-k porous dielectrics. Recent studies on CPI-induced crack propagation in the low-k interconnect and the use of crack-stop structures to improve the chip reliability are also discussed. Finally, 3D integration (3DI) with through silicon vias (TSV) has been proposed as the latest solution to increase the device density without down-scaling. The thermo-mechanical reliability issues facing 3DI are analyzed. Three failure modes are proposed and studied. Design optimization of 3D interconnects to reduce the thermal residual stress and the risks of fracture and delamination are discussed. / text

Multiprocessor system on chip (MPSOC) have strongly emerged in the past decade in communication, multimedia, networking and other embedded domains. MPSOC became a new paradigm of high performance embedded application design. This thesis addresses the design and the physical implementation of a Network on Chip (NoC) based Multiprocessor System on Chip. We studied several aspects at different design stages: high level synthesis, architecture design, FPGA implementation, application evaluation and ASIC physical implementation. We try to analysis and find the impacts of these aspects for the MPSOC's final performance, power consumption and area cost. We implemented a NoC based 16 processors embedded system on FPGA prototyping. Three NoCs provide different functionalities for sixteen PE tiles. We also demonstrated the use of our performance monitoring system for software debugging and tuning. With the bi-synchronous FIFO method, our GALS architecture successfully solves the long clock signal distribution problem and allows that each clock domain can run at its own clock frequency. On the other hand we successfully implemented AES and TDES block cipher cryptographic algorithms on this platform and results show linear speedup in computation time. The network part of our architecture has been implemented on ASIC technology and has been explored with different timing constraints and different library categories of STmicroelectronics' 65nm/45nm technologies. The experimental results of ASIC and FPGA are compared, and we inducted the discussion of technology change impact on parallel programming.