Neste trabalho foi feita uma ampla pesquisa sobre blocos de RF, VCOs e LNAs, que fazem parte de transceptores. Esses blocos foram projetados utilizando um indutor externo com um alto Q, com o intuito de melhorar as principais características de desempenho de cada um dos blocos. Com a finalidade de ter um ponto de comparação foram projetados os mesmos blocos implementando todos os indutores integrados (internos). Foi proposta a utilização da tecnologia flip chip para interconectar os indutores externos aos dies dos circuitos, devido às vantagens que ela apresenta. Para implementar os indutores externos propôs-se um processo de fabricação completo, incluindo especificação das etapas de processos e dos materiais utilizados para estes indutores. Adicionalmente foi projetado um conjunto de máscaras para fabricar os indutores externos e fazer a montagem e teste dos circuitos que os utilizam. Para validar o processo proposto e caracterizar os indutores externos foram projetadas diferentes estruturas de teste. O Q do indutor externo é da ordem de 6 vezes maior que do indutor integrado, para a tecnologia escolhida. Foram projetados e fabricados dois VCOs LC: FC-VCO (Flip Chip VCO com o indutor externo), OC-VCO (On Chip VCO com o indutor interno), e dois LNAs CMOS de fonte comum cascode com degeneração indutiva: FC-LNA (Flip Chip LNA com o indutor Lg externo) e OC-LNA (On Chip LNA com todos os indutores internos). O objetivo desses quatro circuitos é demonstrar que o desempenho de circuitos RF pode ser melhorado, usando indutores externos com alto Q, conectados através de flip chip. Para implementação desses circuitos utilizou-se a tecnologia de processo AMS 0,35µm CMOS, para aplicações na banda 2,4GHz ISM, considerando o padrão Bluetooth. Foram medidos apenas os blocos com os indutores internos (OC-VCO e OC-LNA). Para os blocos com os indutores externos (FC-VCO e FC-LNA) foram apresentados os resultados de simulação pós-layout. Através da comparação dos resultados de simulação entre os VCOs foi comprovado que o uso de um indutor externo com alto Q conectado via flip chip pode melhorar significativamente o ruído de fase dos VCOs, atingindo -117dBc/Hz a 1MHz de frequência de offset para o FC-VCO, em 2,45GHz, onde a FOM é 8dB maior que o OC-VCO. Outro ganho foi através da área poupada, o FC-VCO tem uma área cerca de 83% menor que a do OC-VCO. Após as medidas elétricas do OC-VCO obteve-se um desempenho do ruído de fase de -110dBc/Hz@1MHz para 2,45GHz, e -112dBc/Hz@1MHz para 2,4GHz, o qual atende as especificações de projeto. O FC-LNA, que foi implementado com o indutor de porta Lg externo ao die, conectado via flip chip, atingiu uma figura de ruído de 2,39dB, 1,1dB menor que o OC-LNA com o mesmo consumo de potência. A área ocupada pelo FC-LNA é aproximadamente 30% menor do que o OC-LNA. Através das medidas elétricas do OC-LNA verificou-se que o circuito apresenta resultados adequados de S11 (perda de retorno da entrada) e S22 (perda de retorno da saída) na banda de frequências de interesse. No entanto, o valor do ganho apresenta uma redução em relação ao esperado. A proposta do trabalho de unir a tecnologia flip chip ao uso de indutores externos, proporciona circuitos mais compactos e consecutivamente mais baratos, pela economia de área de Si. Adicionalmente, após os indutores externos serem caracterizados, os mesmos indutores podem ser reutilizados independente da tecnologia CMOS utilizada facilitando o projeto dos blocos de RF em processos mais avançados. / This work presents a research about RF blocks that are used in Transceivers, VCOs and LNAs. These blocks were designed using a high-Q RF external inductor in order to improve the main performance characteristics. The same blocks were designed implementing all inductors on-chip (internal) in order to have a point of comparison. It was proposed the use of Flip Chip technology to interconnect the external inductors to the dies of the circuits due to the advantages that this technology offers. A full manufacturing process was proposed to implement the external inductors, including the specification of process steps and materials used for these inductors. Additionally, a set of masks was designed to fabricate the external inductors, to mount and test the circuits that used these inductors. Different test structures were designed to validate the proposed process and to characterize the external inductors. Q factor of the external inductor is around 6 times larger than the inductor integrated into the chosen IC technology. Two LC VCOs and two common-source cascode CMOS LNAs with inductive degeneration were designed and fabricated: FC-VCO (Flip Chip VCO using external inductor), OC-VCO (On Chip VCO using on-chip inductor), FCLNA (Flip Chip LNA using an external Lg inductor) and OC-LNA (On Chip LNA with all inductors implemented on-chip). The purpose of these four circuits is to demonstrate that the performance of RF circuits can be improved by using high-Q external inductors, connected by flip chip. The 0.35µm CMOS AMS technology was used to implement these circuits intended for applications in the 2.4 GHz ISM band, considering the Bluetooth standard. Were measured only the blocks with internal inductors (OC-VCO and OC-LNA). For the blocks with external inductors (FCVCO and FC-LNA) were presented the results of post-layout simulation. The comparison between the VCOs simulations results demonstrates that using an external high-Q inductor connected by flip chip can significantly improve the phase noise of VCOs. FC-VCO reached a phase noise of -117dBc/Hz at 1MHz offset frequency and a FOM 8dB greater than the OC-VCO. Another important improvement was the saved area, the FC-VCO has an area approximately 83% lower than that of OC-VCO. After electrical characterizations of the OC-VCO, phase noise performances of -110dBc/Hz@1MHz for 2.45GHz and -112dBc/Hz@1MHz for 2.4GHz were obtained, that accomplish the design specifications. FC-LNA reached a noise figure of 2.39dB, 1.1dB lower than that of OC-LNA with the same power comsumption. The total area occupied by FC-LNA is around 30% lower than that OC-LNA. Measurement results of the OC-LNA showed that the circuit presents suitable S11 (input return loss) and S22 (output return loss) values in the desired frequency band. However, the gain value presents a reduction compared with the expected values. The proposal to use the flip chip technology together with external inductors, allows more compact and cheap circuits, because Silicon area can be saved. Moreover, after the external inductors being characterized, the same inductors can be reused regardless of the CMOS technology facilitating the design of RF blocks in more advanced processes.

Este estudo tem por objetivo o desenvolvimento de uma metodologia de fabricação de sistemas Lab On Chip, úteis no estudo de processos celulares, a partir da adaptação de tecnologias próprias da microeletrônica. Foram exploradas todas as etapas envolvidas na fabricação de sistemas Lab On Chip em Poli-Di-Metil-Siloxano e desenvolvidos protocolos de fabricação de moldes, técnicas de moldagem e processos de ativação de PDMS com plasma de oxigênio para sua solda química sobre diferentes materiais, obtendo uniões irreversíveis que permitem a integração com outras tecnologias como a microeletrônica em silício e o encapsulamento com cerâmica verde, completando uma metodologia que permite a prototipagem de dispositivos micro-fluídicos de multicamadas com um nível de sofisticação comparável ao estado da arte. Foi desenvolvido o protótipo de um equipamento ótico para litografia por projeção que permite a fabricação de máscaras óticas com resolução de 5 m e oferece a possibilidade de litografia em escala de cinzas para gerar canais e estruturas com relevos arbitrários. Foram adicionalmente abordados três problemas de biofísica celular, para os quais foram propostos novos dispositivos para separação de células móveis de acordo às suas velocidades lineares, dispositivos para crescimento confinado de bactérias e dispositivos para manipulação da curvatura de membranas celulares. / The objective of this study is the development of a methodology for the fabrication of Lab On Chip systems, useful for the analysis of cellular processes, through the adaptation of technologies from microelectronics. All the steps involved with the fabrication of Lab on Chip system in Poly-Di-Methil-Siloxane (PDMS) were explored, developing protocols for mold fabrication, molding techniques and processes for oxygen plasma activation of PDMS for its bonding to different materials, achieving irreversible bonds that enable the integration with other technologies such as silicon microelectronics and green tape packaging. All this techniques constitute a methodology that allows the prototyping of multilayer microfluidic devices comparable with state of the art devices. It was developed the prototype of optical equipment for projection lithography capable of mask fabrication with 5 m resolution, and which offers also the capability of gray scale lithography for the generation of free form microchannels. Additionally three different problems in cellular biophysics where boarded, proposing new devices for the separation of motile cells according to their linear speeds in liquids, new devices for constrained bacterial growth and for curvature manipulation of cell membranes.

Uma das maiores restrições que existe atualmente no fluxo de projeto de CIs é a necessidade de um ciclo menor de desenvolvimento. Devido às grandes dimensões dos sistemas atuais, é muito provável encontrar no projeto de blocos IP, erros ou bugs originados na passagem de uma dada especificação inicial para seus correspondentes modelos de descrição de hardware. Isto faz com que seja necessário verificar tais modelos para garantir aplicações cem por cento funcionais. Uma das técnicas de verificação que tem adquirido bastante popularidade recentemente é a verificação funcional, uma vez que é uma alternativa que ajuda a manter baixos custos de validação dos modelos HDL ao longo do projeto completo do circuito. Na verificação funcional, que está baseada em ambientes de simulação, a funcionalidade completa (ou relevante) do modelo é explorada, aplicando-se casos de teste, um após o outro. Isto permite examinar o modelo em todas as seqüências e combinações de entradas desejadas. Na verificação funcional, existe a possibilidade de simular o modelo estimulando-o com casos de teste aleatórios, o qual ajuda a cobrir um amplo número de estados. Para facilitar a aplicação de estímulos em simulação de circuitos, é comum que espaços definidos por parâmetros de entrada sejam limitados em sua abrangência e agrupados de tal forma que subespaços sejam formados. No desenvolvimento de testbenches, os geradores de estímulos aleatórios podem ser criados de forma a conter subespaços que se sobrepõem (resultando em estímulos redundantes) ou subespaços que contenham condições que não sejam de interesse (resultando em estímulos inválidos). É possível eliminar ou diminuir, os casos de teste redundantes e inválidos através da aplicação de metodologias de modificação do espaço de estímulos de entrada, e assim, diminuir o tempo requerido para completar a simulação de modelos HDL. No presente trabalho, é realizada uma análise da aplicação da técnica de organização do espaço de entrada através de domínios de parâmetros do IP, e uma metodologia é desenvolvida para tal, incluindo-se, aí, uma ferramenta de codificação automática de geradores de estímulos aleatórios em linguagem SyatemC: o GET_PRG. Resultados com a aplicação da metodologia é comparada a casos de aplicação de estímulos aleatórios gerados a partir de um espaço de estímulos de entrada sem modificações.Como esperado, o número de casos de teste redundantes e inválidos aplicados aos testbenches foi sempre maior para o caso de estimulação aleatória a partir do espaço de estímulos de entrada completo com um tempo de execução mais longo. / One of the strongest restrictions that exist throughout ICs design flow is the need for shorter development cycles. This, along with the constant demand for more functionalities, has been the main cause for the appearance of the so-called System-on-Chip (SOC) architectures, consisting of systems that contain dozens of reusable hardware blocks (Intellectual Properties, or IPs). The increasing complexity makes it necessary to thoroughly verify such models in order to guarantee 100% functional applications. Among the current verification techniques, functional verification has received important attention, since it represents an alternative that keeps HDL validation costs low throughout the circuits design cycle. Functional verification is based in testbenches, and it works by exploring the whole (or relevant) models functionality, applying test cases in a sequential fashion. This allows the testing of the model in all desired input sequences and combinations. There are different techniques concerning testbench design, being the random stimulation an important approach, by which a huge number of test cases can be automatically created. In order to ease the stimuli application in circuit simulation, it is common to limit the range of the space defined by input parameters and to group such restricted parameters in sub-spaces. In testbench development, it may occur the creation of random stimuli generators containing overlapping sub-spaces (resulting in redundant stimuli) or sub-spaces containing conditions of no interest (resulting in invalid stimuli). It is possible to eliminate, or at least reduce redundant and invalid test cases by modifying the input stimuli space, thus, diminishing the time required to complete the HDL models simulation. In this work, the application of a technique aimed to organize the input stimuli space, by means of IP parameter domains, is analyzed. A verification methodology based on that is developed, including a tool for automatic coding of random stimuli generators using SystemC: GET_PRG. Results on applying such a methodology are compared to cases where test vectors from the complete verification space are generated. As expected, the number of redundant test cases applied to the testbenches was always greater for the case of random stimulation on the whole (unreduced, unorganized) input stimuli space, with a larger testbench execution time.

GcvB est un ARN bactérien conservé de 200 nucléotides, qui régule négativement l’expression de plusieurs gènes impliqués dans l’import et la biosynthèse des acides aminés. Bien que le rôle physiologique de GcvB ne soit pas complètement élucidé, il contribuerait vraisemblablement à équilibrer les ressources nutritionnelles en conditions de croissance rapide. GcvB inhibe la traduction des ARNm cibles en s’appariant avec des séquences à l’intérieur ou en amont du site de liaison du ribosome. Dans cette étude, la caractérisation d’un nouveau locus régulé par GcvB a permis de dévoiler des aspects singuliers du mode de fonctionnement de cet ARN régulateur. Nous avons découvert que GcvB réprime yifK - un gène très conservé, codant pour un transporteur d’acides aminés putatif - en ciblant un élément activateur de la traduction sur l’ARNm. Deux motifs ACA dans la séquence cible sont les déterminants principaux de la fonction activatrice. Le remplacement de l’un ou l’autre avec des triplets aléatoires, provoque une diminution de 10 fois du niveau d’expression de yifK, quelque soit l’allèle de GcvB (délétion ou changement de séquence permettant la reconnaissance de la cible mutante). Il apparait ainsi que l’efficacité de GcvB à réguler négativement sa cible serait liée a sa capacité d’antagoniser l’élément activateur. Lorsque l’activateur est éliminé, l’action de GcvB n’est plus un facteur limitant pour l’expression de yifK. Dans son ensemble, cette étude apporte une meilleure compréhension de la fonction de GcvB et révèle un nouvel aspect du processus d’initiation de la traduction. En plus du contrôle par GcvB, le locus yifK est régulé au niveau transcriptionnel par Lrp (leucine-responsive regulatory protein) et par HdfR (YifA) un régulateur transcriptionnel peu connu qui requerrait le produit du gène adjacent orienté de façon divergente, yifE, pour son expression ou activité. Enfin, la transcription initiée au niveau du promoteur yifK s’étend dans l’opéron d’ARNt argX-hisR-leuT-proM adjacent, donnant lieu à un transcrit primaire qui est à la fois un lARNm et un précurseur des ARNt. Cet ARN chimère est rapidement maturé par l’ARNase E. / GcvB is a conserved 200 nucleotide RNA that downregulates several genes involved in amino acid uptake or biosynthesis in bacteria. The physiological role of GcvB action is not entirely clear, but it is likely aimed at balancing of nutritional resources under fast growth conditions. GcvB inhibits translation of target messenger RNAs by pairing with sequences inside or upstream of ribosome binding sites. In the present study, characterization of a novel GcvB-regulated locus revealed some unique features in the mode of functioning of this regulatory RNA. We found that GcvB represses yifK - a highly conserved locus encoding a putative amino acid transporter - by targeting a translational enhancer element. Two ACA motifs within the target sequence are the main determinants of the enhancer activity. Replacing either of these motifs with random triplets caused up to a 10-fold decrease in yifK expression regardless of the GcvB allele (deleted or suitably modified to recognize the mutated target). It thus appears that GcvB effectiveness as a regulator results from countering the enhancer activity. When the enhancer is removed, GcvB action no longer constitutes a rate-limiting factor for yifK expression. Overall, this study is relevant not only to a better understanding of GcvB function but it also provides insight into an elusive aspect of the translation initiation process. Besides the GcvB control, the yifK locus is regulated at the transcriptional level by the leucine responsive regulator Lrp, and by HdfR (YifA) a poorly known transcriptional regulator, that appears to require the product of the adjacent, divergently oriented gene, yifE, for expression or activity. Transcription initiating at the yifK promoter extends into the adjacent argX-hisR-leuT-proM tRNA operon yielding an unusual primary transcript which both a messenger RNA and a tRNA precursor. This chimeric RNA si rapidly processed by RNAse E.

This thesis deals with factors which are important for making decisions in the game of poker. The goal is to find a way to improve players chances of success in this game. The first two chapters describe the rules of poker and the basics and presumptions of the game theory The following chapters analyze some mathematical models and assumptions for applying these models in the game. These models should find the optimal solution for individuals in decision making situations. It can be considered a static situation, where the behavior of each player is predetermined and the decision maker tries to find an appropriate strategy. It is also can be considered a dynamic situation, when all players react to each other, which heads to equilibrium solution. As a consequence of rising popularity of poker tournaments many strategy books have appeared, as well as analytic software. Nevertheless, it is and probably will remain impossible to solve all decision situations which can occur. A very important factor of success are some gamblers attitude, experience and mental skills. Mathematical knowledge, however, will become more and more important. This thesis will help to understand the basic of mathematic models and their application in poker game.

Les facteurs environnementaux, tels que les pesticides, peuvent induire des changements phénotypiques dans une variété d'organisme incluant les mammifères. Nous avons étudié chez la souris les effets d'un pesticide largement utilisé, l'atrazine (ATZ), sur la méiose, une étape clé du processus de spermatogenèse. L'utilisation des méthodes de puces à ADN (Gene-Chip) et de séquençage de chromatine immunoprécipité (ChIP-seq) nous a permis de mettre en évidence l'effet de l'ATZ sur une variété de fonctions cellulaires, incluant l'activité GTPase, la fonction mitochondriale et le métabolisme des hormones stéroïdes. De plus, les souris traitées présentent un enrichissement des marques d'histone H3K4me3 au niveau des régions de forte recombinaison (sites de cassures double brin) de gènes très long et une réduction de ces mêmes marques au niveau des régions pseudo-autosomal du chromosome X. Nos données démontrent que l'exposition à l'ATZ interfère avec le déroulement normal de la méiose, ceci affectant la production des spermatozoïdes. Nous avons trouvé que les marques H3K4me3, chez la souris mâle, sont largement affectées par l'ATZ grâce à l'utilisation de technique de séquençage du génome entier. La reprogrammation embryonnaire nécessite l'action coordonnée d'un grand nombre de gène et de facteurs épigénétiques afin de permettre la transition de cellules somatique en cellules germinales. Les modifications épigénétiques imposées pendant la transition des cellules somatiques en cellules germinales et affectées par des expositions nocives, peuvent être héritées et transmises aux générations suivantes via les gamètes. Dans cette étude, nous avons examiné l'héritage des histones modifié aux générations suivantes. Nous avons exposés des femelles gestantes CD1 non consanguines à l'ATZ et les mâles issus de ces femelles ont été croisés pendant trois générations avec des femelles non traitées. Nous avons démontré ici que l'exposition à l'ATZ réduit le nombre de spermatozoïdes sans affecter la morphologie cellulaire ou la proportion des différents types cellulaires constituant l'épithélium séminifère chez les individus issus de la 3ème génération après traitement. Beaucoup de gènes associés avec la réparation de l'ADN, la reproduction et les fonctions mitochondriales sont dérégulés chez les mâles issus de la 3ème génération après traitement. De façon importante, l'exposition à l'ATZ change dramatiquement l'initiation de la transcription, l'épissage et la polyadénylation alternative des ARN. Nous avons aussi observé chez les mâles F3 issus de souris traitées à l'ATZ une altération de la localisation des marques H3K4me3 dans le promoteur de gène associé à la régulation de processus métaboliques cellulaires, à la régulation de la transcription et à la mitose. Les changements de localisation des marques H3K4me3 chez les mâles F3 issus de souris traitées à l'ATZ correspondent à des changements de la localisation de ces marques au niveau de gènes impliqués dans la différenciation des cellules de type souche de la génération F1.Nos données suggèrent que l'héritage transgénérationnel est permis grâce à de multiples voies et repose sur le statut épigénétique de gènes impliqués dans la différenciation des cellules de type souches tels que Pou5f1 et Sox2, l'action des facteurs de transcription et la rétention d'histones dans le sperme. / Environmental factors such as pesticides can cause phenotypic changes in various organisms, including mammals. We studied the effects of the widely used herbicide atrazine (ATZ) on meiosis, a key step of gametogenesis, in male mice. We demonstrate that exposure to ATZ reduces testosterone levels and the number of spermatozoa in the epididymis and delays meiosis. Using Gene-Chip and ChIP-Seq analysis of H3K4me3 marks, we found that a broad range of cellular functions, including GTPase activity, mitochondrial function and steroid-hormone metabolism, are affected by ATZ. Furthermore, treated mice display enriched histone H3K4me3 marks in regions of strong recombination (double-strand break sites), within very large genes and reduced marks in the pseudoautosomal region of X chromosome. Our data demonstrate that atrazine exposure interferes with normal meiosis, which affects spermatozoa production.We found that the H3K4me3 marks in male mice are broadly affected by the widely used herbicide atrazine with genome wide ChIP-sequencing. Embryonic reprogramming requires the coordinated action of many genes and epigenetic factors to perform somatic to germline transition. The epigenetic modifications imposed during somatic to germline transition and affected by harmful exposure can be inherited and transferred to subsequent generations via the gametes. In this study, we examine the inheritance of altered histone modifications by subsequent generations. We exposed pregnant outbred CD1 female mice to the widely used herbicide atrazine (ATZ), and the male progeny were crossed for three generations with untreated females. We demonstrate here that exposure to ATZ reduces the number of spermatozoa without changing the cell morphology or types in testis tissue in the third generation after treatment. Many genes associated with DNA repair, reproduction and mitochondrial function became dysregulated in the third generation (F3) of males after treatment. Importantly, exposure to ATZ dramatically changes the transcription initiation, splicing and alternative polyadenylation of RNA. We also observed altered occupancy of H3K4me3 markers in the F3 generation of ATZ-derived males in gene promoters associated with the regulation of cellular metabolic processes, transcriptional regulation and mitosis. The changes in H3K4me3 occupancy in F3 ATZ-derived males correspond to changes in the H3K4me3 occupancy of stem cell differentiation genes in the F1 generation. Our data suggest that transgenerational inheritance is accomplished through multiple pathways and relies on the epigenetic state of stem cell differentiation genes such as Pou5f1 and Sox2, transcription factor action and sperm histone retention.

Physically Unclonable Functions (PUFs) are now widely being used to uniquely identify Integrated Circuits (ICs). In this work, we propose a novel Set-Reset (SR) Flip-flop based PUF design. For a NAND gate based SR flip-flop, the input condition S (Set) = 1 and R (Reset) = 1 must be avoided as it is an inconsistent condition. When S=R=1 is applied followed by S=R=0, then the outputs Q and Q' undergo race condition and depending on the delays of the NAND gates in the feedback path, the output Q can settle at either 0 or 1. Because of process variations in an IC, the NAND delays are statistical in nature. Thus, for a given SR FF based $n$-bit register implemented in an IC, when we apply S=R=1 to all flip-flops followed by S=R=0, then we obtain an $n$ bit string that can be interpreted as a signature of the chip. Due to process variations, the signature is highly likely to be unique for an IC. We validated the proposed idea by SPICE-level simulations for 90nm, 45nm, and 32nm designs for both intra- and inter-chip variations to establish the robustness of the proposed PUF. Experimental results for 16-, 32-, 64-, and 128-bit registers based on Monte-Carlo simulations demonstrate that the proposed PUF is robust. The main advantage of the proposed PUF is that there is very little area overhead as we can reuse existing registers in the design.

The Task Scheduling Paradigm is a general technique for leveraging fine and coarse grain parallelism from applications of several domains with minimum impact on code readability, relying on the automatic inference of data dependencies among tasks. The performance of Task Parallel applications is correlated with the speed at which the underlying Task Scheduling System is able to detect such dependencies, something that is critical for fine-granularity workloads, which cannot amortize scheduling overheads with long periods of useful computation. That being the case, several groups have recently been developing FPGA-accelerated Task Scheduling Systems architectures where a software Task Scheduling Runtime is able to offload its bookkeeping computations to an FPGA-based accelerator with the goal of efficiently scheduling fine-grained tasks to CPU cores. Even though these FPGA-accelerated systems offer substantial gains over the software-only baseline, it is also true that FPGA-CPU communication bottlenecks prevent such designs from handling scenarios with either large number of cores or very fine-grained tasks. With that in mind, we proposed the implementation of a Native Task Scheduling System that is, a processor with native support for task scheduling embedded into its architecture with the goal of substantially reducing these overheads. More specifically, this project aimed at embedding the HW logic of Picos, a mature Task Scheduling Accelerator developed by the Barcelona Supercomputing Center (BSC), into Rocket Chip, an open-source, silicon-proven, multi-core implementation of RISC-V. The ISA of the resulting system provides special instructions for Task Applications to interact with this Task Scheduling Logic, ruling out all FPGA-CPU communication latencies. To evaluate the prototype performance, we both (1) adapted Nanos, a mature Task Scheduling runtime, to benefit from the new task-scheduling-accelerating instructions; and (2) developed Phentos, a new HW-accelerated light weight Task Scheduling runtime. Our experiments show that task parallel programs using Nanos-RV the Nanos version ported to our system are on average 2.13 times faster than those being serviced by baseline Nanos, while programs running on Phentos are 13.19 times faster, considering geometric means. Using eight cores, Nanos-RV is able to deliver speedups with respect to serial execution of up to 5.62 times, while Phentos produces speedups of up to 5.72 times. / Paralelismo por Tarefas é uma técnica genérica de extração de paralelismo de granularidade arbitrária aplicável a programas de vários domínios, com mínimo impacto sobre legibilidade de código, baseada na inferência automática de dependências de dados entre tarefas. O desempenho de aplicações paralelas baseadas nesse paradigma depende da velocidade com a qual o runtime de Paralelismo por Tarefas que lhe dá suporte é capaz de detectar tais dependências, fato que é ainda mais crítico para aplicações envolvendo tarefas de granularidade fina, já que nesse cenário o overhead de escalonamento não é amortizado por períodos significativamente maiores de computação útil. Recentemente, diversos grupos têm desenvolvido Sistemas de Suporte a Paralelismo por Tarefas acelerados por FPGAs, os quais são capazes de fazer offload das operações de inferência de dependências para um acelerador em FPGA de modo a melhorar o seu desempenho ao lidar com tarefas de granularidade fina. Por outro lado, ainda que esses sistemas acelerados por FPGA apresentem ganhos substanciais com relação às alternativas baseadas puramente em software, o desempenho dessas soluções é prejudicado por gargalos de comunicação entre a CPU e a FPGA, os quais limitam a capacidade desses sistemas de lidar com cenários envolvendo grande número de núcleos ou tarefas muito finas. Motivados por isso, implementamos um Sistema de Suporte Nativo a Paralelismo por Tarefas isto é, um processador com suporte arquitetural nativo a Paralelismo por Tarefas com o objetivo de reduzir consideravelmente tais overheads de comunicação. Mais especificamente, integramos a lógica em hardware do Picos, um acelerador de Paralelismo por Tarefas desenvolvido pelo Barcelona Supercomputing Center (BSC), ao Rocket Chip, uma implementação multi-core de código livre do RISC-V desenvolvida pela Universidade da Califórnia, Berkeley. O sistema resultante contém em sua ISA (Instruction Set Architecture) as instruções necessárias para que aplicações baseadas em tarefas possam interagir diretamente com essa lógica de escalonamento, minimizando os overheads associados ao uso de runtimes intermediários e eliminando toda a latência de comunicação FPGA-CPU. Para avaliar a performance do protótipo que então se construiu, nós tanto (1) adaptamos o runtime de escalonamento de tarefas Nanos para que ele pudesse ser acelerado pelas novas instruções de escalonamento de tarefas, quanto (2) criamos um novo runtime leve de escalonamento de tarefas a que demos o nome de Phentos. Nossos experimentos mostram que programas baseados em paralelismo por tarefas usando o runtime Nanos-RV a versão do runtime Nanos com suporte ao sistema que produzimos são executados em média 2,13 vezes mais rapidamente do que versões dos mesmos programas utilizando a versão básica do Nanos, enquanto programas executados com o Phentos são em média 13,19 vezes mais rápidos do que suas versões correspondentes baseadas na mesma versão básica do Nanos. Tais valores médios correspondem à média geométrica dos conjuntos de dados pertinentes. Usando oito núcleos, Nanos-RV entrega ganhos de desempenho com relação a execuções seriais de até 5,62 vezes, enquanto Phentos entrega ganhos de até 5,72 vezes.

L'électronique de puissance d'aujourd'hui s'inscrit dans un contexte environnemental où l'économie d'énergie est au centre des préoccupations. La traduction technologique d'une telle problématique sera, pour l'électronicien, la recherche de structures de conversion optimisant à la fois le rendement, la fiabilité et la qualité de l'énergie absorbée ou produite. Cet effort d'optimisation énergétique ne saurait être satisfaisant sans une recherche d'adaptation matérielle aux applications industrielles ou domestiques visées (avion tout électrique, éclairage...). C'est dans ce contexte que se situe ce travail de thèse, visant à chercher des solutions innovantes en terme de package de convertisseurs statiques satisfaisant les exigences de ces nouveaux secteurs d'exploitation, dans lesquels la miniaturisation, la fiabilité ou encore l'immunité aux perturbations CEM sont déterminants.

Reducing cost and time is a major concern in clinical diagnostics. Current molecular diagnostics are multi-step processes that usually take at least several hours or even days to complete multiple reagents delivery, incubations and several washing processes. This highly labor-intensive work and lack of automation could result in reduced reliability and low efficiency. The Laboratory-on-a-chip (LOC), taking advantage of the merger and development of microfluidics and biosensor technology, has shown promise towards a solution for performing analytical tests in a self-contained and compact unit, enabling earlier and decentralized testing. However, challenges are to integrate the fluid regulatory elements on a single platform and to detect target analytes with high sensitivity and selectivity. The goal of this research work is to develop an AC electrokinetic (ACEK) flow through concentrator for in-situ concentration of biomolecules and develop a comprehensive understanding of effects of ACEK flow on the biomolecule transport (in-situ concentration) and their impact on electronic biosensing mechanism and performance, achieving automation and miniaturization. ACEK is a new and promising technique to manipulate micro/bio-fluids and particles. It has many advantages over other techniques for its low applied voltage, portability and compatibility for integration into lab-on-a-chip devices. Numerical study on preconcentration system design in this work has provided an optimization rule for various biosensor designs using ACEK technique. And the microfluidic immunoassay lab-chip designed based on ACET effect has showed promising prospect for accelerated diagnostics. With optimized design of channel geometry, electrode patterns, and properly selected operation condition (ac frequency and voltage), the preconcentration system greatly reduced the reaction time to several minutes instead of several hours, and improved sensitivity of the assay. With the design of immunoassay lab-chip, one can quantitatively study the effect of ACET micropumping and mixing on molecular level binding. Improved sensors with single-chip form factor as a general platform could have a significant impact on a wide-range of biochemical detection and disease diagnostics including pathogen/virus detection, whole blood analysis, immune-screening, gene expression, as well as home land security.