Continuing to scale down the transistor size makes the introduction of high-k dielectric necessary. However, there are still a lot of problems with highk transistors such as worse reliability and Fermi-level pinning. In HfO₂, low crystallization temperature, fixed charge in the bulk and low quality of the Si/HfO₂ interface cause reliability problems. Fermi-level pinning results in high threshold voltage. For the first work in this dissertation, forming Hf1-xTaxO through doping HfO₂ with Ta is used to improve the crystallization temperature and electron mobility. Then, the fluorine passivation of high-k dielectrics is studied. With fluorine passivation, the electron mobility was improved in NMOSFETs with gate stacks of poly-Si/TaN/HfO₂/p-Si with thin TaN layers. Inserting a 1.5nm layer of HfSiON between TaN and HfO₂ completely blocked the fluorine atoms so that they could not reach the Si interface. Thus, no mobility was improved even with fluorine implantation. In order to decrease threshold voltage, we must study mechanisms of Fermi level pinning (FLP) in high-k gate stacks. We summarize three FLP mechanisms: (1) the dipole formation at the interface between metal gate and high-k dielectric due to hybridization; 2) the dipole formation through oxygen vacancy mechanism; (3) the dipole formation at the interface between high-k dielectric and interfacial SiO₂. The rest of dissertation focuses on the mechanism of Vfb shift by capping a thin layer of Me₂O₃ (Me=Gd, Y and Dy) on SiO₂ and HfO₂-based high-k dielectrics with TaN, W and Pt metal gate. It is proposed that the negative Vfb shift with TaN metal gate be due to the dipole formation at the interface between Me₂O₃ and the interfacial SiO₂. An XPS (X-ray photoelectron spectroscopy) study of Gd₂O₃ capping on SiO₂ indicates clear Si, O and Gd related bonding state change at the interface between Gd₂O₃ (or GdSiO) and the interfacial SiO₂. So the bonding state change is the root cause of the dipole formation. When there is an oxygen deficiency in Me₂O₃, another dipole formation through oxygen vacancy mechanism can also be observed. For a full understanding of the Vfb shift, all three FLP mechanisms must be considered. / text

The performance scaling of metal-oxide-semiconductor field-effect-transistors (MOSFETs) has been historically achieved through shrinking the gate length of transistors for over four decades. Addressing the current challenges with CMOS scaling, the 2005 edition of International Technology Roadmap for Semiconductors has predicted the need for so-called technology boosters involving new materials for the gate dielectric and the channel as well as innovative structures. Theoretical studies suggest that the incorporation of high-mobility channel materials such as germanium and III-Vs could outperform bulk Si technology in terms of switching characteristics. Hence, this has recently led to tremendous research activity to explore the prospects of III-V materials for CMOS applications. Nevertheless, technological challenges such as formation of highquality interface between gate dielectric and III-V channel have hindered the demonstration of enhancement-mode III-V MOSFETs. Hence, tremendous effort has been devoted to study the exact origin of Fermi level pinning at the oxide/III-V interface. On the other hand, the advent of high-k materials has opened up the possibility of exploring new channel materials, for which it is challenging to achieve high-quality interface analogous to that of SiO2 on Si. Lately, III-Vs have been extensively explored in order to find compatible gate dielectrics which can unpin the Fermi level at the interface. Amongst various schemes, atomic layer deposition of high-k dielectrics offers some unique advantages such as reduction of GaAs interfacial oxides upon high-k deposition through an appropriate choice of precursor chemistry. The chief focus of this dissertation is to develop a simple wet clean process prior to high-k deposition, suitable for III-V substrates. The impact of various chemical treatments of GaAs substrates on the properties of high-k/GaAs interface was studied through extensive material and electrical characterization methods. The suitability of the ALD-grown high-k gate dielectrics on GaAs for MOSFET fabrication was explored. Charge trapping was found to result in significant errors in mobility extraction in high-k GaAs interface, where the role of high-k is not well understood. Hence, pulsed I-V and QV measurements and galvanomagnetic effects were utilized in order to directly measure the inversion charge in the channel without being affected by the charge traps as much as possible. It was also found that the material studies on GaAs substrates can be readily extended to other III-V channels, such as InGaAs. / text

This document details experiments attempting to increase the performance of metal-oxide-semiconductor field-effect-transistors (MOSFETs) which are the mainstay of the semiconductor industry. Replacing the silicon channel with an ultra-thin epitaxial germanium layer grown selectively on a silicon (100) bulk wafer is examined in detail. The gate oxide chosen for the germanium devices is a high-k gate oxide, HfO2, and the gate electrode is a metal gate, tantalum-nitride. They demonstrate large improvements in drive current and mobility over identically processed silicon PMOSFETs. In addition to the planar germanium PMOSFETs, a process has been developed for 50nm and smaller germanium P-finFETs and N and P germanium tunnel-FETs. The patterning of sub-30nm wide and 230nm tall three dimensional fins has been done with electron beam lithography and dry plasma etching. The processes to deposit high-k gate oxide and metal gates on the sub-30nm wide fins have been developed. All that remains for the production of these devices is electron beam lithography with a maximum misalignment error of 40nm. / text

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