Three-Dimensional (3D) optical range-imaging is a field experiencing rapid growth, expanding into a wide variety of machine vision applications, most recently including consumer gaming. Time of Flight (ToF) cameras, akin to RADAR with light, sense distance by measuring the round trip time of modulated Infra-Red (IR) illumination light projected into the scene and reflected back to the camera. Such systems generate 'depth maps' without requiring the complex processing utilised by other 3D imaging techniques such as stereo vision and structured light. Existing range-imaging solutions within the ToF category either perform demodulation in the analogue domain, and are therefore susceptible to noise and non-uniformities, or by digitally detecting individual photons using a Single Photon Avalanche Diode (SPAD), generating large volumes of raw data. In both cases, external processing is required in order to calculate a distance estimate from this raw information. To address these limitations, this thesis explores alternative system architectures for ToF range imaging. Specifically, a new pixel concept is presented, coupling a SPAD for accurate detection of the arrival time of photons to an all-digital Phase- Domain Delta-Sigma (PDΔΣ) loop for the first time. This processes the SPAD pulses locally, converging to estimate the mean phase of the incoming photons with respect to the outgoing illumination light. A 128×96 pixel sensor was created to demonstrate this principle. By incorporating all of the steps in the range-imaging process – from time resolved photon detection with SPADs, through phase extraction with the in-pixel phase-domain ΔΣ loop, to depth map creation with on-chip decimation filters – this sensor is the first fully integrated 3D camera-on-achip to be published. It is implemented in a 130nm CMOS imaging process, the most modern technology used in 3D imaging work presented to date, enabled by the recent availability of a very low noise SPAD structure in this process. Excellent linearity of ±5mm is obtained, although the 1σ repeatability error was limited to 160mm by a number of factors. While the dimensions of the current pixel prevent the implementation of very high resolution arrays, the all-digital nature of this technique will scale well if manufactured in a more advanced CMOS imaging process such as the 90nm or 65nm nodes. Repartitioning of the logic could enhance fill factor further. The presented characterisation results nevertheless serve as first validation of a new concept in 3D range-imaging, while proposals for its future refinement are presented.

This thesis describes the development and demonstration of a new technique for the fabrication of well-defined quantum dots in a bulk silicon substrate, for potential applications such as quantum computation in coupled quantum dots. Hall characterisation was performed on double-gated mesaMetal-Oxide- Semiconductor Field-Effect Transistors (MOSFETs) on a silicon-on-insulator (SOI) substrate, for the purpose of silicon quantum dots in etched nanowires on SOI. Carrier density and mobility results are presented, demonstrating top- and backgate control over the two inversion layers created at the upper and lower surfaces of the superficial silicon mesa. A new technique is developed enabling effective depletion gating of quantum dots in a bulk silicon substrate. A lower layer of aluminium gates is defined using electron beam lithography; the surface of these gates is oxidised using a plasma oxidation technique; and a further layer of aluminium gates is deposited. The lower gates form tunable tunnel barriers in the narrow inversion layer channel created by the upper MOSFET gate. The two layers of gates are electrically isolated by the localised layer of aluminium oxide. Low-temperature transport spectroscopy has been performed in both the many electron (∼100 electrons) and the few electron (∼10 electrons) regimes.Excited states in the bias spectroscopy provide evidence of quantum confinement. Preliminary temperature and magnetic field dependence data are presented. These results demonstrate that depletion gates are an effective technique for defining quantum dots in silicon. Furthermore, the demonstration of the first silicon radio-frequency single electron transistor is reported. The island is again defined by electrostatically tunable tunnel barriers in a narrow channel field effect transistor. Charge sensitivities of better than 10μe/√Hz are demonstrated at MHz bandwidth. These results establish that silicon may be used to fabricate fast, sensitive electrometers.

"August 2003" Bibliography: leaves 108-117. 1. Ruthenium-106 ophthalmic applicators -- 2. General principle of thermoluminescent dosimeter -- 3. Study of basic characteristics of CaSO4:Dy TLD -- 4. Measurements of COB and CCA type ruthenium-106 ophthalmic applicator dose distributions -- 5. Determination of the dose rate distribution using a MOSFET detector -- 6. Summary and conclusion. In this project, small CaSO4:Dy TLDs and a semiconductor MOSFET dosimeter were used for the determination of on-axis depth dose-rate distributions of 15-mm and 20-mm ruthenium-106 applicators in acrylic eye phantoms. The TLDs were also used to determine off-axis dose distributions.

This thesis focuses on the design of high voltage MOSFET on SiC and its application in power electronic systems. Parameters extraction for 4H SiC MOS devices is the main focus of the first topic developed in this thesis. Calibration of two-dimensional (2-D) device and circuit simulators (MEDICI and SPICE) with state-of-the-art 4H SiC MOSFETs data are performed, which includes the mobility parameter extraction. The experimental data were obtained from lateral N-channel 4H SiC MOSFETs with nitrided oxide-semiconductor interfaces, exhibiting normal mobility behavior. The presence of increasing interface-trap density (Dit) toward the edge of the conduction band is included during the 2-D device simulation. Using measured distribution of interface-trap density for simulation of the transfer characteristics leads to good agreement with the experimental transfer characteristic. The results demonstrate that both MEDICI and SPICE simulators can be used for design and optimization of 4H SiC MOSFETs and the circuits utilizing these MOSFETs. Based on critical review of SiC power MOSFETs, a new structure of SiC accumulation-mode MOSFET (ACCUFET) designed to address most of the open issues related to MOS interface is proposed. Detailed analysis of the important design parameters of the novel structure is performed using MEDICI with the parameter set used in the calibration process. The novel structure was also compared to alternative ACCUFET approaches, specifically planar and trench-gate ACCUFETs. The comparison shows that the novel structure provides the highest figure of merit for power devices. The analysis of circuit advantages enabled by the novel SiC ACCUFET is given in the final part of this thesis. The results from circuit simulation show that by utilizing the novel SiC ACCUFET the operating frequency of the circuit can be increased 10 times for the same power efficiency of the system. This leads to dramatic improvements in size, weight, cost and thermal management of power electronic systems.

Thesis (Ph. D.)--University of Texas at Austin, 2006. / Vita. Includes bibliographical references.

Thesis (M.S.)--Rochester Institute of Technology, 2007. / Typescript. Includes bibliographical references.

The major limiting factor of DRAM access time is the low transconductance of the MOSFET's which have only limited current drive capability. The bipolar junction transistor(BJT) has a collector current amplification factor, ��, times base current and is limited mostly by the willingness to supply this base current. This collector current is much larger than the MOSFET drain current under similar conditions. The requirements for low power and low power densities results in lower power supply voltages which are also inconsistent with the threshold voltage variations in CMOS technology, as a consequence at least pulsed body bias or synchronous body bias will probably be utilized. Given that of the CMOS body will be driven or the CMOS gate and body connected a BJT technique is proposed for ultra low voltages like Vdd=0.5. Utilizing present CMOS process technology good results can be achieved with ultra low power using gate-body connected transistors and a current sense amplifier. / Graduation date: 1999

Full integration of CMOS low noise amplifiers (LNA) presents a challenge for low cost CMOS receiver systems. A critical problem faced in the design of an RF CMOS LNA is the inaccurate high-frequency noise model of the MOSFET implemented in circuit simulators such as SPICE. Silicon-based monolithic inductors are another bottleneck in RF CMOS design due to their poor quality factor. In this thesis, a CMOS implementation of a fully-integrated differential LNA is presented. A small-signal noise circuit model that includes the two most important noise sources of the MOSFET at radio frequencies, channel thermal noise and induced gate current noise, is developed for CMOS LNA analysis and simulation. Various CMOS LNA architectures are investigated. The optimization techniques and design guidelines and procedures for an LC tuned CMOS LNA are also described. Analysis and modeling of silicon-based monolithic inductors and transformers are presented and it is shown that in fully-differential applications, a monolithic transformer occupies less die area and achieves a higher quality factor compared to two independent inductors with the same total effective inductance. It is also shown that monolithic transformers improve the common-mode rejection of the differential circuits. / Graduation date: 1999

High-accuracy and high-speed CMOS track-and-hold (T/H) or sample-and-hold (S/H) circuits are an important part of the analog-to-digital interface. The switched-capacitor (SC) circuits usually contain one or more op-amps whose dc offset, finite gain, finite bandwidth have a big impact on the accuracy of the track-and-hold circuit. Basic correlated double sampling (CDS) scheme can reduce such effects, but the compensation that it provides may not be good enough for high-accuracy application. Also, the high-quality analog poly-poly capacitors used in most SC circuits are not available in a basic digital CMOS process. The MOSFET-only predictive track-and-hold circuit, discussed in this thesis, replaces the poly-poly capacitors with easily-available low-cost area-saving MOSFET capacitors biased in accumulation region. It also uses the predictive correlated double sampling (CDS) scheme, in which the op-amp predicts its output for the next clock period during the present clock period, so that the adjacent two output samples are nearly the same. The predictive operation results in more correlation between the unwanted signal and the signal that is subtracted during the double sampling, and hence can achieve offset and gain compensation over wider frequency range. Hence, this circuit is suitable for high-accuracy applications, while using only a basic digital process. / Graduation date: 1997

Scaling down of the CMOS technology requires thinner gate dielectric to maintain high performance. However, due to the depletion of poly-Si gate, it is difficult to reduce the gate thickness further especially for sub-65 nm CMOS generation. Fully silicidation metal gate (FUSI) is one of the most promising solutions. Furthermore, FUSI metal gate reduces gate-line sheet resistance, prevents boron penetration to channels, and has good process compatibility with high-k gate dielectric. Poly-SiGe gate technology is another solution because of its enhancement of boron activation and compatibility with the conventional CMOS process. Combination of these two technologies for the formation of fully germanosilicided metal gate makes the approach very attractive. In this paper, the deposition of undoped Poly-Si₁₋xGex (0 < x < 30% ) films onto SiO₂ in a low pressure chemical vapor deposition (LPCVD) system is described. Detailed growth conditions and the characterization of the grown films are presented. / Singapore-MIT Alliance (SMA)