<p>As  thefundamentallimits  of  two-dimensional(2D)geometric  scaling  of  commercial transistors  are  being reached,  there  is  tremendous  demand  for  new  materials  and  process innovations  that  can  keep  delivering  performance  improvements  for  future  generations  of computing chips. One major avenue being explored istheincorporation ofan increasing degree of three-dimensionality   by   vertically   stacking   logic   and   memory   layerswith   high-density interconnections.In  this  dissertation,  high-performanceultra-thin  amorphousindium  oxide transistors  are  demonstrated as  an  excellent  candidate  for these  back-end-of-line  (BEOL)  and monolithic 3D (M3D) integration applications.</p> <p>A  major  pain-point  in the  development  of  BEOL  and  M3D  systems is  the  strict  thermal budget imposed –once the bottom layer of devices is fabricated, they can generally withstand no more  than  400 °C.  It  is  exceedingly  difficult  to  directly  deposit  single-crystal  material  at  these temperatures, and polycrystalline materials will have grain boundary instability issues. Amorphous materials  generally  have  low  carrier  mobilities,  which  would  seemingly  remove  them  from contention as well. Indium oxideand itsclass of related metal oxides are exceptions. Indium oxideis  a  wide  bandgap  semiconductor  with  high  electron  mobility  up  to  about  100  cm²/V∙s  in amorphous form. Ithas a strong preference for native degenerate n-type doping which has hindered prior  devices  fabricated  with it.  In  this  dissertation,  extremely  thin  layers  on  the  order  of  1  nm thick are used for which quantum confinement effects widen the bandgap further, reliably enabling gate-controllable  carrier  densitiesand  demonstration  of  excellent  transistor  performance  with  a low thermal budget of just 225 °C.</p> <p>Detailed characterization is performed down to 40 nm channel lengths revealing excellent transistor characteristics  includingenhancement-mode operation withon currents greater than 2 A/μm, low  subthreshold  swing,and  high  on/off  ratios  due  to  the  wide  bandgap.  Subsequent chaptersdemonstrate the fundamental lower limits of off current around 6 ×10^-20A/μmby a novel measurement  technique,  good  gate  bias  stress  stability  behaviorwith  small  parameter  drift  at silicon  complementary  metal  oxide  semiconductor  (CMOS)  logic  voltages,  and  high-frequency operationin the GHz regime enabling easy operation at CMOS clock frequencies.</p>

The underlying physical mechanisms of destructive single event effects (SEE) from heavy ion radiation have been widely studied in traditional vertical double-diffused power MOSFETs (VDMOS). Recently lateral double-diffused power MOSFETs (LDMOS), which inherently provide lower gate charge than VDMOS, have become an attractive option for MHz-frequency DC-DC converters in terrestrial power electronics applications [1]. There are growing interests in extending the LDMOS concept into radiation-hard space applications. Since the LDMOS has a device structure considerably different from VDMOS, the well studied single event burn-out (SEB) or single event gate rapture (SEGR) response of VDMOS cannot be simply assumed for LDMOS devices without further investigation. A few recent studies have begun to investigate ionizing radiation effects in LDMOS devices, however, these studies were mainly focused on displacement damage and total ionizing dose (TID) effects, with very limited data reported on the heavy ion SEE response of these devices [2]-[5]. Furthermore, the breakdown voltage of the LDMOS devices in these studies was limited to less than 80 volts (mostly in the range of 20-30 volts), considerably below the voltage requirement for some space power applications. In this work, we numerically and experimentally investigate the physical insights of SEE in two different fabricated LDMOS devices designed by the author and intended for use in radiation hard applications. The first device is a 24 V Resurf LDMOS fabricated on P-type epitaxial silicon on a P+ silicon substrate. The second device is a iv much different 150 V SOI Resurf LDMOS fabricated on a 1.0 micron thick N-type silicon-on-insulator substrate with a 1.0 micron thick buried silicon dioxide layer on an N-type silicon handle wafer. Each device contains internal features, layout techniques, and process methods designed to improve single event and total ionizing dose radiation hardness. Technology computer aided design (TCAD) software was used to develop the transistor design and fabrication process of each device and also to simulate the device response to heavy ion radiation. Using these simulations in conjunction with experimentally gathered heavy ion radiation test data, we explain and illustrate the fundamental physical mechanisms by which destructive single event effects occur in these LDMOS devices. We also explore the design tradeoffs for making an LDMOS device resistant to destructive single event effects, both in terms of electrical performance and impact on other radiation hardness metrics

A simulation program has been developed to facilitate the investigation and analysis of power semiconductor devices under the reverse-bias condition. The electrostatic potential distribution is solved by using Poisson's equation alone, with particular attention to the neighborhood of avalanche breakdown. Because of its generality and efficiency, the program emerges as a powerful engineering tool for the design of power devices incorporating special junction termination techniques. Results are presented for a DMOS structure to illustrate the improvement in breakdown voltage when a field plate is applied. Numerical solution techniques for solving elliptic partial differential equations in a multi-material domain are discussed. The discretization of this domain is nonuniform in general due to its highly nonuniform physical parameters. By careful selection of grid lines near interfaces, the difference equation coefficients are considerably simplified. The resultant matrix of coefficients is symmetric even though Neumann boundary conditions are specified.

The Jain and Balk analytic model for two-dimensional effects in short channel MOSFETS is investigated. The effects considered are Drain Induced Barrier Lowering, DIBL, and the maximum electric field, Emax, which influences Drain Induced High Field, DIHF. A scaled short channel design is used as the basis for the investigation. Cases are numerically simulated using the MINIMOS program. DIBL and Emax are calculated using the Jain and Balk model. Model values are compared to numerical simulation values. Results show the model consistently overestimates DIBL. Also, the range for which the model closely estimates Emax is found. Variation in Emax with change of junction depth Xj is investigated. The electric field, Ex, as it varies with depth in the channel is investigated, and compared to the Jain and Balk approximation. The deviations suggest that the model must break down for short channels.

Application of power MOSFETs in spaceborne power converters was simulated by exposing devices to low-dose-rate ionizing radiation. Both radiation-hardened and nonhardened devices were tested with constant and switched gate biases during irradiation. In addition, some of the devices were under load. The threshold-voltage shifts were strongly bias dependent. The threshold-voltage shift of the nonhardened parts was approximately dose-rate independent, while the hardened parts exhibited significant dose-rate dependence. A pre-anneal dose-rate dependence was found for the interface-state buildup of the switched and positively biased devices, but the results for the switched devices were qualitatively different than those for the positively biased devices. The buildup of interface trapped charge was found to be the primary contributor to mobility degradation, which results in reduced drive capability and slower operation of the devices. These results indicate that new methods need to be utilized to accurately predict the performance of power MOSFETs in space environments.

The effects of ionizing radiation on the breakdown-voltage degradation of power-MOSFET termination structures were examined through two-dimensional simulation. A wide variety of sensitivity to surface-charge density was found for various devices employing floating field rings and/or equipotential field plates. Termination structures that were both insensitive to surface charge and possessed a high breakdown voltage were identified. The results were compared with measurements made on selected structures. The principal ionizing radiation damaging mechanisms in MOS devices are discussed. Modifications made to an existing simulation program in order to simulate these complex field ring and field plate structures are described. Background information into how these termination structures improve the breakdown voltage and their sensitivities to positive interface charge buildup is investigated.

Thesis (M. Tech. Engineering: Electrical--Vaal University of Technology / A high-power Mosfet was incorporated as a switching device into the efficient Class E configuration, where the switching device switches current through itself either completely on or completely off at high frequencies. The first objective of this project was to demonstrate the effectiveness of a phase-lock loop circuit in generating stable high frequencies when connected in an indirect frequency synthesizer configuration. The indirect frequency synthesizer has established itself as a versatile frequency generator capable of generating high frequencies based on a lower stable reference frequency. The frequency generation stage incorporates a phaselock loop circuit, a frequency divider and a stable reference frequency section. The phase-lock loop section incorporates the TTL based 74HC 4046 that is based upon the common CMOS 4046 integrated circuit. The frequency divider section is built around the CMOS-based 4526 whilst the reference frequency section incorporates the CMOS-based 4060. The frequency synthesizer produced a range of frequencies from 50 kHz to 8 MHz in 50 kHz steps. The output voltage was constant at 5,5 V. The second objective was to show that the complementary emitter follower is indeed a worthy Mosfet gate drive circuit at high frequencies. The Mosfet driver stage produced a voltage signal of at least 11 V, being able to source and sink relatively high peaks of current, especially at high frequencies. Voltage amplification occurred through the use of multiple CMOS-based 40106 inverters. The complementary emitter follower, known for its low output impedance and its ability to source and sink large amounts of current, was an important component in the final Mosfet gate section.

by Tse Man Siu. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1988. / Bibliography: leaves 203-210.

Hiu Yung Wong. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2001. / Includes bibliographical references (leaves 104-111). / Abstracts in English and Chinese. / Abstract --- p.i / Acknowledgments --- p.iii / List of Figures --- p.ix / List of Tables --- p.xiii / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Motivation and Objectives --- p.1 / Chapter 1.2 --- Contributions --- p.3 / Chapter 1.3 --- Organization of the Thesis --- p.4 / Chapter 2 --- Devices and Fabrication Processes --- p.5 / Chapter 2.1 --- Introduction --- p.5 / Chapter 2.2 --- BJTs --- p.6 / Chapter 2.2.1 --- Structure and Modeling of BJTs --- p.6 / Chapter 2.2.2 --- Standard BJT Process and BJT Characteristics --- p.7 / Chapter 2.3 --- MOSFETs and Complementary MOS (CMOS) --- p.8 / Chapter 2.3.1 --- Structure and Modeling of MOSFETs --- p.8 / Chapter 2.3.2 --- Standard n-well CMOS Process and MOSFETs Charac- teristics --- p.11 / Chapter 2.4 --- BiCMOS Technology --- p.13 / Chapter 2.5 --- Summary --- p.14 / Chapter 3 --- Matching Properties --- p.15 / Chapter 3.1 --- Introduction --- p.15 / Chapter 3.2 --- Importance of Matched Devices in IC Design --- p.15 / Chapter 3.2.1 --- What is Matching? --- p.15 / Chapter 3.2.2 --- Low-power Systems --- p.16 / Chapter 3.2.3 --- Device Size Downward Scaling --- p.16 / Chapter 3.2.4 --- Analog Circuits and Analog Computing --- p.17 / Chapter 3.3 --- Measurement of Mismatch --- p.18 / Chapter 3.3.1 --- Definitions and Statistics of Mismatch --- p.18 / Chapter 3.3.2 --- Types of Mismatches --- p.20 / Chapter 3.3.3 --- Matching Properties of MOSFETs --- p.23 / Chapter 3.3.4 --- Matching Properties of BJTs and CLBTs --- p.27 / Chapter 3.4 --- Summary --- p.30 / Chapter 4 --- CMOS Compatible Lateral Bipolar Transistors (CLBTs) --- p.31 / Chapter 4.1 --- Introduction --- p.31 / Chapter 4.2 --- Structure and Operation --- p.32 / Chapter 4.3 --- DC Model of CLBTs --- p.34 / Chapter 4.4 --- Residual Gate Effect in Accumulation --- p.35 / Chapter 4.5 --- Main Characteristics of CLBTs --- p.37 / Chapter 4.5.1 --- Low Early Voltage --- p.37 / Chapter 4.5.2 --- Low Lateral Current Gain at High Current Levels --- p.38 / Chapter 4.5.3 --- Other Issues --- p.39 / Chapter 4.6 --- Enhanced CLBTs with Cascode Circuit --- p.40 / Chapter 4.7 --- Applications --- p.41 / Chapter 4.8 --- Design and Layout of CLBTs --- p.42 / Chapter 4.9 --- Experimental Results of Single pnp CLBT； nMOSFET and pMOSFET --- p.44 / Chapter 4.9.1 --- CLBT Gains --- p.46 / Chapter 4.9.2 --- Gate Voltage Required for Pure Bipolar Action --- p.47 / Chapter 4.9.3 --- I ´ؤ V and Other Characteristics of Bare pnp CLBTs --- p.49 / Chapter 4.9.4 --- Transfer Characteristics of a Cascoded pnp CLBT --- p.50 / Chapter 4.9.5 --- Transfer Characteristics of an nMOSFET --- p.51 / Chapter 4.9.6 --- Transfer Characteristics of Cascoded and Bare CLBTs Operating as pMOSFETs --- p.52 / Chapter 4.10 --- Summary --- p.53 / Chapter 5 --- Experiments on Matching Properties --- p.54 / Chapter 5.1 --- Introduction --- p.54 / Chapter 5.2 --- Objectives --- p.55 / Chapter 5.3 --- Technology --- p.57 / Chapter 5.4 --- Design of Testing Arrays --- p.57 / Chapter 5.4.1 --- nMOSFET Array --- p.57 / Chapter 5.4.2 --- pnp CLBT Array --- p.59 / Chapter 5.5 --- Design of Input and Output Pads (I/O Pads) --- p.62 / Chapter 5.6 --- Shift Register --- p.62 / Chapter 5.7 --- Experimental Equipment --- p.63 / Chapter 5.8 --- Experimental Setup for Matching Properties Measurements --- p.65 / Chapter 5.8.1 --- Setup for Measuring the Mismatches of the Devices --- p.65 / Chapter 5.8.2 --- Testing Procedures --- p.68 / Chapter 5.8.3 --- Data Analysis --- p.68 / Chapter 5.9 --- Matching Properties --- p.69 / Chapter 5.9.1 --- Matching Properties of nMOSFETs --- p.69 / Chapter 5.9.2 --- Matching Properties of CLBTs --- p.71 / Chapter 5.9.3 --- Matching Properties of pMOSFETs --- p.73 / Chapter 5.9.4 --- "Comments on the Matching Properties of CLBT, nMOSFET, and pMOSFET" --- p.76 / Chapter 5.9.5 --- "Mismatch in CLBT, nMOSFET, and pMOSFET Cur- rent Mirrors" --- p.77 / Chapter 5.10 --- Summary --- p.79 / Chapter 6 --- Conclusion --- p.80 / Chapter A --- Floating Gate Technology --- p.82 / Chapter A.1 --- Floating Gate --- p.82 / Chapter A.2 --- Tunnelling --- p.83 / Chapter A.3 --- Hot Electron Effect --- p.85 / Chapter A.4 --- Summary --- p.86 / Chapter B --- A Trimmable Transconductance Amplifier --- p.87 / Chapter B.1 --- Introduction --- p.87 / Chapter B.2 --- Trimmable Transconductance Amplifier using Floating Gate Com- patible Lateral Bipolar Transistors (FG-CLBTs) --- p.87 / Chapter B.2.1 --- Residual Gate Effect and Collector Current Modulation --- p.89 / Chapter B.2.2 --- Floating Gate CLBTs --- p.92 / Chapter B.2.3 --- Electron Tunnelling --- p.93 / Chapter B.2.4 --- Hot Electron Injection --- p.94 / Chapter B.2.5 --- Experimental Results of the OTA --- p.94 / Chapter B.2.6 --- Experimental Results of the FGOTA --- p.96 / Chapter B.3 --- Summary --- p.97 / Chapter C --- AMI-ABN 1.5μm n-well Process Parameters (First Batch) --- p.98 / Chapter D --- AMI-ABN 1.5μm n-well Process Parameters (Second Batch) --- p.101 / Bibliography --- p.104

by Fong Hon Hang = 超薄二氧化硅的固定電荷分佈和電擊穿特性 / 方漢鏗. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2000. / Includes bibliographical references. / Text in English; abstracts in English and Chinese. / by Fong Hon Hang = Chao bo er yang hua gui de gu ding dian he fen bu he dian ji chuan te xing / Fang Hankeng. / ABSTRACT --- p.i / ACKNOWLEDGEMENTS --- p.iii / TABLE OF CONTENT --- p.iv / LIST OF FIGURES --- p.ix / LIST OF TABLES --- p.xiv / LIST OF SYMBOLS --- p.xv / Chapter Chapter1 --- Background of the thesis work / Chapter 1.1 --- Introduction --- p.1 / Chapter 1.2 --- Stability of charge on oxide --- p.1 / Chapter 1.3 --- Defects in SiO2/Si --- p.2 / Chapter 1.4 --- Objectives of the thesis work --- p.4 / Chapter 1.5 --- Organization of the thesis --- p.5 / Bibliography for Chapter1 --- p.6 / Chapter Chapter2 --- Theory of X-ray Photoelectron Spectroscopy (XPS) and Surface Charge Spectroscopy (SCS) / Chapter 2.1 --- Introduction --- p.7 / Chapter 2.2 --- X-ray photoelectron spectrometry (XPS) --- p.8 / Chapter 2.2.1 --- Binding energy reference for semiconductors --- p.10 / Chapter 2.2.2 --- Measurement of surface Fermi level --- p.15 / Chapter 2.2.3 --- XPS quantitative analysis --- p.17 / Chapter 2.2.3.1 --- Electron Inelastic Mean free Path --- p.16 / Chapter 2.2.3.2 --- Atomic concentration of a homogeneous material --- p.17 / Chapter 2.2.3.3 --- Determination of overlayer thickness --- p.19 / Chapter 2.3 --- Surface charge Spectroscopy (SCS) --- p.21 / Chapter 2.3.1 --- Principle of the SCS technique --- p.21 / Chapter 2.3.2 --- Control of the dielectric surface potential --- p.21 / Chapter 2.3.3 --- Dielectric layer surface potential --- p.22 / Chapter 2.3.4 --- Surface band bending --- p.23 / Chapter 2.3.5 --- Limitation of the dielectric layer thickness --- p.24 / Chapter 2.4 --- Applications of SCS on Metal-Oxide Semiconductor (MOS) --- p.24 / Chapter 2.4.1 --- Measurements of interface state density (Dit) --- p.24 / Chapter 2.4.2 --- Determination of density of fixed-oxide charges --- p.27 / Bibliography for Chapter2 --- p.28 / Chapter Chapter3 --- Instrumentation & methodology / Chapter 3.1 --- X-ray Photoelectron Spectroscopy (XPS) --- p.30 / Chapter 3.1.1 --- General description of the Kratos AXIS - HS XPS system --- p.30 / Chapter 3.1.2 --- X-ray source --- p.32 / Chapter 3.1.3 --- AXIS - HS electron analyzer and transfer lens system --- p.35 / Chapter 3.1.4 --- Laser alignment facility --- p.38 / Chapter 3.1.5 --- In-lens (Micro XPS) aperture --- p.38 / Chapter 3.1.6 --- Iris (Lens input aperture) --- p.39 / Chapter 3.1.7 --- Magnetic immersion lenses --- p.39 / Chapter 3.1.8 --- Lateral resolutions --- p.41 / Chapter 3.1.9 --- Charge neutralizer --- p.53 / Chapter 3.1.10 --- XPS imaging capability --- p.58 / Chapter 3.1.11 --- Angle-resolved X-ray photoelectron spectroscopy (ARXPS) --- p.58 / Chapter 3.1.12 --- Ion sputtering system and depth profiling --- p.59 / Chapter 3.2 --- Methodology for surface charging --- p.59 / Chapter 3.3 --- Sample preparation --- p.61 / Bibliography for Chapter3 --- p.62 / Chapter Chapter4 --- Fixed-oxide charge Qf(z) of thermally-grown SiO2/Si(100) / Chapter 4.1 --- Introduction --- p.63 / Chapter 4.2 --- Experimental results on oxide surface potential as a function of oxide thickness --- p.64 / Chapter 4.3 --- Calculation of fixed-oxide charge distribution --- p.69 / Chapter 4.3.1 --- Gauss's law --- p.69 / Chapter 4.3.2 --- Density of fixed-oxide charge --- p.70 / Chapter 4.4 --- Applications --- p.78 / Bibliography for chapter4 --- p.80 / Chapter Chapter5 --- Observation of dielectric electrical breakdown phenomena of SiO2/Si structure by SCS / Chapter 5.1 --- Introduction to electrical breakdown analysis in device electronics --- p.81 / Chapter 5.2 --- Experimental --- p.82 / Chapter 5.3 --- Results --- p.82 / Chapter 5.3.1 --- Analysis on 1000A Sio2/Si --- p.82 / Chapter 5.3.1.1 --- Variation of C 1s under charging --- p.82 / Chapter 5.3.1.2 --- Stochastic breakdown of SiO2 --- p.84 / Chapter 5.3.2 --- Analysis on 19k SiO2/Si --- p.91 / Chapter 5.4 --- Discussion --- p.93 / Chapter 5.4.1 --- Model of stochastic breakdown of SiO2/Si --- p.93 / Chapter 5.4.2 --- Variation of Si 2p under charging --- p.95 / Chapter 5.5 --- Summary --- p.96 / Bibliography for Chapter5 --- p.99 / Chapter Chapter6 / Conclusion --- p.100