No description available.

Thesis (PhD (Electric and Electronic Engineering))--University of Stellenbosch, 2007. / There is increasing use of commercial components in space technology and it is important to recognize that the space radiation environment poses the risk of permanent malfunction due to radiation. Therefore, the integrated circuits used for spacecraft electronics must be resistant to radiation. The effect of using the MOSFET device in a radiation environment is that the gate oxide becomes ionized by the dose it absorbs due to the radiation induced trapped charges in the gate-oxide. The trapped charges in the gate-oxide generate additional space charge fields at the oxide-substrate interface. After a sufficient dose, a large positive charge builds up, having the same effect as if a positive voltage was applied to the gate terminal. Therefore, the transistor source to drain current can no longer be controlled by the gate terminal and the device remains on permanently resulting in device failure. There are four processes involved in the radiation response of MOS devices. First, the ionizing radiation acts with the gate oxide layer to produce electron-hole pairs. Some fraction of the electron-hole pairs recombine depending on the type of incident particle and the applied gate to substrate voltage, i.e. the electric field. The mobility of the electron is orders of magnitude larger than that of the holes in the gate oxide, and is swept away very quickly in the direction of the gate terminal. The time for the electrons to be swept away is on the order of 1ps. The holes that escape recombination remain near their point of origin. The number of these surviving holes determines the initial response of the device after a short pulse of radiation. The cause of the first process, i.e. the presence of the electric field, is the main motivation for design method described in this dissertation. The second process is the slow transport of holes toward the oxide-silicon interface due to the presence of the electric field. When the holes reach the interface, process 3, they become captured in long term trapping sites and this is the main cause of the permanent threshold voltage shift in MOS devices. The fourth process is the buildup of interface states in the substrate near the interface The main contribution of this dissertation is the development of the novel Switched Modular Redundancy (SMR) method for mitigating the effects of space radiation on satellite electronics. The overall idea of the SMR method is as follows: A charged particle is accelerated in the presence of an electric field. However, in a solid, electrons will move around randomly in the absence of an applied electric field. Therefore if one averages the movement over time there will be no overall motion of charge carriers in any particular direction. On applying an electric field charge carriers will on average move in a direction aligned with the electric field, with positive charge carriers such as holes moving in the direction of field, and negative charge carriers moving in the opposite direction. As is the case with process one and two above. It is proposed in this dissertation that if we apply the flatband voltage (normaly a zero bias for the ideal NMOS transistor) to the gate terminal of a MOS transistor in the presence of ionizing radiation, i.e. no electric field across the gate oxide, both the free electrons and holes will on average remain near their point of origin, and therefore have a greater probability of recombination. Thus, the threshold voltage shift in MOS devices will be less severe for the gate terminal in an unbiased condition. The flatband conditions for the real MOS transistor is discussed in appendix E. It was further proposed that by adding redundancy and applying a resting policy, one can significantly prolong the useful life of MOS components in space. The fact that the rate of the threshold voltage shift in MOS devices is dependant on the bias voltage applied to the gate terminal is a very important phenomenon that can be exploited, since we have direct control and access to the voltage applied to the gate terminal. If for example, two identical gates were under the influence of radiation and the gate voltage is alternated between the two, then the two gates should be able to withstand more total dose radiation than using only one gate. This redundancy could be used in a circuit to mitigate for total ionizing dose. The SMR methodology would be to duplicate each gate in a circuit, then selectively only activating one gate at a time allowing the other to anneal during its off cycle. The SMR algorithm was code in the “C” language. In the proposed design methodology, the design engineer need not be concerned about radiation effects when describing the hardware implementation in a hardware description language. Instead, the design engineer makes use of conventional design techniques. When the design is complete, it is synthesized to obtain the gate level netlist in edif format. The edif netlist is converted to structural VHDL code during synthesis. The structural VHDL netlist is fed into the SMR “C” algorithm to obtain the identical redundant circuit components. The resultant file is also a structural VHDL netlist. The generated VHDL netlist or SMR circuit can then be mapped to a Field Programmable Gate Array (FPGA). Spacecraft electronic designers increasingly demand high performance microprocessors and FPGAs, because of their high performance and flexibility. Because FPGAs are reprogrammable, they offer the additional benefits of allowing on-orbit design changes. Data can be sent after launch to correct errors or to improve system performance. System including FPGAs covers a wide range of space applications, and consequently, they are the object of this study in order to implement and test the SMR algorithm. We apply the principles of reconfigurable computing to implement the Switched Modular Redundancy Algorithm in order to mitigate for Total Ionizing Dose (TID) effects in FPGA’s. It is shown by means of experimentation that this new design technique provides greatly improved TID tolerance for FPGAs. This study was necessary in order to make the cost of satellite manufacturing as low as possible by making use of Commercial off-the-shelf (COTS) components. However, these COTS components are very susceptible to the hazards of the space environment. One could also make use of Radiation Hard components for the purpose of satellite manufacturing, however, this will defeat the purpose of making the satellite manufacturing cost as low as possible as the cost of the radiation hard electronic components are significantly higher than their commercial counterparts. Added to this is the undesirable fact that the radiation hard components are a few generations behind as far as speed and performance is concerned, thus providing even greater motivation for making use of Commercial components. Radiation hardened components are obtained by making use of special processing methods in order to improve the components radiation tolerance. Modifying the process steps is one of the three ways to improve the radiation tolerance of an integrated circuit. The two other possibilities are to use special layout techniques or special circuit and system architectures. Another method, in which to make Complementary Metal Oxide Silicon (CMOS) circuits tolerant to ionizing radiation is to distribute the workload among redundant modules (called Switched Modular Redundancy above) in the circuit. This new method will be described in detail in this thesis.

Fluorescence based analysis is a fundamental research technique used in the life sciences. However, conventional fluorescence intensity measurements are prone to misinterpretation due to illumination and fluorophore concentration non-uniformities. Thus, there is a growing interest in time-resolved fluorescence detection, whereby the characteristic fluorescence decay time-constant (or lifetime) in response to an impulse excitation source is measured. The sensitivity of a sample’s lifetime properties to the micro-environment provides an extremely powerful analysis tool. However, current fluorescence lifetime analysis equipment tends to be bulky, delicate and expensive, thereby restricting its use to research laboratories. Progress in miniaturisation of biological and chemical analysis instrumentation is creating low-cost, robust and portable diagnostic tools capable of high-throughput, with reduced reagent quantities and analysis times. Such devices will enable point-of-care or in-the-field diagnostics. It was the ultimate aim of this project to produce an integrated fluorescence lifetime analysis system capable of sub-nano second precision with an instrument measuring less than 1cm3, something hitherto impossible with existing approaches. To accomplish this, advances in the development of AlInGaN micro-LEDs and high sensitivity CMOS detectors have been exploited. CMOS allows electronic circuitry to be integrated alongside the photodetectors and LED drivers to produce a highly integrated system capable of processing detector data directly without the need for additional external hardware. In this work, a 16x4 array of single-photon avalanche diodes (SPADs) integrated in a 0.35μm high-voltage CMOS technology has been implemented which incorporates two 9-bit, in-pixel time-gated counter circuits, with a resolution of 400ps and on-chip timing generation, in order to directly process fluorescence decay data. The SPAD detector can accurately capture fluorescence lifetime data for samples with concentrations down to 10nM, demonstrated using colloidal quantum dot and conventional fluorophores. The lifetimes captured using the on-chip time gated counters are shown to be equivalent to those processed using commercially available external time-correlated single-photon counting (TCSPC) hardware. A compact excitation source, capable of producing sub-nano second optical pulses, was designed using AlInGaN micro-LEDs bump-bonded to a CMOS driver backplane. A series of driver array designs are presented which are electrically contacted to an equivalent array of micro-LEDs emitting at a wavelength of 370nm. The final micro-LED driver design is capable of producing optical pulses of 300ps in width (full width half maximum, FWHM) and a maximum DC optical output power of 550μW, this is, to the best of our knowledge, the shortest reported optical pulse from a CMOS driven micro-LED device. By integrating an array of CMOS SPAD detectors and an array of CMOS driven AlInGaN micro-LEDs, a complete micro-system for time-resolved fluorescence analysis has been realised. Two different system configurations are evaluated and the ability of both topologies to accurately capture lifetime data is demonstrated. By making use of standard CMOS foundry technologies, this work opens up the possibility of a low-cost, portable chemical/bio-diagnostic device. These first-generation prototypes described herein demonstrate the first time-resolved fluorescence lifetime analysis using an integrated micro-system approach. A number of possible design improvements have been identified which could significantly enhance future device performance resulting in increased detector and micro-LED array density, improved time-gate resolution, shorter excitation pulse widths with increased optical output power and improved excitation light filtering. The integration of sample handling elements has also been proposed, allowing the sample of interest to be accurately manipulated within the micro-environment during investigation.

This thesis reports the study of metal oxide semiconductors for the application of photoelectrochemical water splitting with a particular emphasis on both anion and cation-doped zinc oxides. A study of the mechanisms of visible light absorption in both anion and cation-doped ZnO semiconductors, the potentials of metal oxide materials modified by impurities as one of the ideal photocatalysts in harvesting solar light has been explored. X-ray photoelectron spectroscopy (XPS) and UV-Vis spectroscopes have been performed to establish the electronic structures of anion and cation-doped ZnO. Aluminium impurities in ZnO thin films reveal the relationship between the bandgap broadening and the so-called Burstein Moss effect. Both cadmium and sulphur dopants were incorporated in ZnO either as powders by the solid state synthesis or as thin films by spray pyrolysis technique. Cadmium and sulphur dopants demonstrate effective electronic bandgap reduction and an increasing absorption of visible light. Furthermore, the incorporation of cadmium and sulphur in ZnO were prepared as photoanodes and evaluated in a custom-built photoelectrochemical workstation for the measurement of photon energy conversion efficiencies.

This thesis focuses on the development of a low power energy harvesting system specifically targeted for wireless sensor nodes (WSN) and wireless body area network (WBAN) applications. The idea for the system is derived from the operation of a micro-grid and therefore is termed as a pico-grid and it is capable of simultaneously delivering power from multiple and multitype energy harvesters to the load at the same time, through the proposed parallel load sharing mechanism achieved by a voltage droop control method. Solar panels and thermoelectric generator (TEG) are demonstrated as the main energy harvesters for the system. Since the magnitude of the output power of the harvesters is time-varying, the droop gain in the droop feedback circuitry should be designed to be dynamic and self-adjusted according to this variation. This ensures that the maximum power is capable to be delivered to the load at all times. To achieve this, the droop gain is integrated with a light dependent resistor (LDR) and thermistor whose resistance varies with the magnitude of the source of energy for the solar panel and TEG, respectively. The experimental results demonstrate a successful variation droop mechanism and all connected sources are able to share equal load demands between them, with a maximum load sharing error of 5 %. The same mechanism is also demonstrated to work for maximum power point tracking (MPPT) functionality. This concept can potentially be extended to any other types of energy harvester. The integration of energy storage elements becomes a necessity in the pico-grid, in order to support the intermittent and sporadic nature of the output power for the harvesters. A rechargeable battery and supercapacitor are integrated in the system, and each is accurately designed to be charged when the loading in the system is low and discharged when the loading in the system is high. The dc bus voltage which indicates the magnitude of the loading in the system is utilised as the signal for the desired mode of operation. The constructed system demonstrates a successful operation of charging and discharging at specific levels of loading in the system. The system is then integrated and the first wearable prototype of the pico-grid is built and tested. A successful operation of the prototype is demonstrated and the load demand is shared equally between the source converters and energy storage. Furthermore, the pico-grid is shown to possess an inherent plug-and-play capability for the source and load converters. Few recommendations are presented in order to further improve the feasibility and reliability of the prototype for real world applications. Next, due to the opportunity of working with a new semiconductor compound and accessibility to the fabrication facilities, a ZnON thin film diode is fabricated and intended to be implemented as a flexible rectifier circuit. The fabrication process can be done at low temperature, hence opening up the possibility of depositing the device on a flexible substrate. From the temperature dependent I-V measurements, a novel method of extracting important parameters such as ideality factor, barrier height, and series resistance of the diode based on a curve fitting method is proposed. It is determined that the ideality factor of the fabricated diode is high (> 2 at RT), due to the existence of other transport mechanism apart from thermionic emission that dominates the conduction process at lower temperature. It is concluded that the high series resistance of the fabricated diode (3.8 kΩ at RT) would mainly hinder the performance of the diode in a rectifier circuit.

Point functionalized carbon nanotubes have recently demonstrated the ability to serve as single-molecule biosensors. Operating as single-molecule Field-Effect Transistors (smFET), the sensors have been used to explore activity ranging in scope from DNA hybridization kinetics to DNA polymerase functionality. High signal levels and an all-electronic label-free transduction mechanism make the smFET an attractive candidate for next-generation medical diagnostics platforms and high-bandwidth basic science research studies. In this work, carbon nanotubes are integrated onto a custom designed CMOS chip. Integration enables arraying many devices for measurement, providing the requisite scale-up for any commercial application of smFETs. Integration also provides substantial benefits towards achieving high bandwidths through the reduction of electrical parasitics. In a first exploitation of these high-bandwidth measurement capabilities, integrated devices are electrically characterized over a 1-MHz bandwidth. Functionalization through electrochemical oxidation of the devices is observed with microsecond temporal resolution, revealing complex reaction pathways with resolvable scattering signatures. High rate random telegraph noise (RTN) is observed in certain oxidized devices, further illustrating the temporal resolution of the integrated sensing platform.

This thesis consists of three main parts, starting with the use of improved nitridation processes to grow acceptable quality gate oxides on silicon carbide (SiC)[1]–[7], to the comprehensive investigation of basic electron-hole generation process in 4H SiC-based metal–oxide–semiconductor (MOS) capacitors [8], [9], and concluding with the experimental demonstration and analysis of nonvolatile characteristics of 4H SiC-based memory devices [10]–[15]. In the first part of the thesis, two improved versions of nitridation techniques have been introduced to alleviate oxide-growth rate and toxicity problems. Using a combination of nitridation and oxidation processes, a sandwich technique (nitridation–oxidation–nitridation) has been proposed and verified to solve the lengthy and expensive oxide-growing process in direct nitric oxide (NO) gas [1]. The nitrogen source from the toxic-NO gas has been replaced by using a nontoxic nitrous oxide (N2O) gas. The best combination of process parameters in this gas is oxide-growing temperature at 1300oC with 10% N2O [2], [3]. The quality of nitrided gate oxides obtained by this technique is lower than the sandwich technique [6], [13]. Using 4H SiC-based MOS with nitrided gate oxides grown by either of the abovementioned nitridation techniques, the fundamentals of electron-hole generation have been investigated using high-temperature capacitance–transient measurements. The contributions of carrier generation, occurring at room temperature, in the bulk and at the SiC–SiO2 interface are evaluated and compared using a newly developed method [8], [9]. The effective bulk-generation rates are approximately equal for both types of nitrided oxides, whereas the effective surface-generation rates have been shown to exhibit very strong dependencies on the methods of producing the nitrided gate oxide. Based on analysis, the prevailing generation component in a SiC-based MOS capacitor with nitrided gate oxide is at SiC–SiO2 interface located below the gate. Utilizing the understanding of electron-hole generation in SiC, the nonvolatile characteristics of memory device fabricated on SiC have been explored. The potential of developing a SiC-based one-transistor one-capacitor (1T/1C) nonvolatile-dynamic memory (NDM) has been analyzed using SiC-based MOS capacitors as storage elements or test structures. Three possible leakage mechanisms have been evaluated [10]–[16]: (1) leakage via MOS capacitor dielectric, (2) leakage due to electron-hole generation in a depleted MOS capacitor, and (3) junction leakage due to generation current occurred at a reverse-biased pn junction surrounding the drain region of a select metal–oxide– semiconductor field–effect–transistor (MOSFET). Among them, leakage through capacitor oxide remains an important factor that could affect the nonvolatile property in the proposed device, whereas others leakage mechanisms are insignificant. Based on the overall results, the potential of developing a SiC-based 1T/1C NDM is encouraging.

Fabrication techniques and process integration considerations for amorphous oxide semiconductor (AOS) thin-film transistors (TFTs) constitute the central theme of this dissertation. Within this theme three primary areas of focus are pursued. The first focus involves formulating a general framework for assessing passivation. Avoiding formation of an undesirable backside accumulation layer in an AOS bottom-gate TFT is accomplished by (i) choosing a passivation layer in which the charge neutrality level is aligned with (ideal case) or higher in energy than that of the semiconductor channel layer charge neutrality level, and (ii) depositing the passivation layer in such a manner that a negligible density of oxygen vacancies are present at the channel-passivation layer interface. Two AOS TFT passivation schemes are explored. Sputter-deposited zinc tin silicon oxide (ZTSO) appears promising for suppressing the effects of negative bias illumination stress (NBIS) with respect to ZTO and IGZO TFTs. Solution-deposited silicon dioxide is used as a barrier layer to subsequent PECVD silicon dioxide deposition, yielding ZTO TFT transfer curves showing that the dual-layer passivation process does not significantly alter ZTO TFT electrical characteristics. The second focus involves creating an adaptable back-end process compatible with flexible substrates. A detailed list of possible via formation techniques is presented with particular focus on non-traditional and adaptable techniques. Two of the discussed methods, "hydrophobic surface treatment" and "printed local insulator," are demonstrated and proven effective. The third focus is printing AOS TFT channel layers in order to create an adaptable and additive front-end integrated circuit fabrication scheme. Printed zinc indium aluminum oxide (ZIAO) and indium gallium zinc oxide (IGZO) channel layers are demonstrated using a SonoPlot piezoelectric printing system. Finally, challenges associated with printing electronic materials are discussed. Organic-based solutions are easier to print due to their ability to "stick" to the substrate and form well-defined patterns, but have poor electrical characteristics due to the weakness of organic bonds. Inorganic aqueous-based solutions demonstrate good electrical performance when deposited by spin coating, but are difficult to print because precise control of a substrate's hydrophillic/hydrophobic nature is required. However, precise control is difficult to achieve, since aqueous-based solutions either spread out or ball up on the substrate surface. Thickness control of any printed solution is always problematic due to surface wetting and the elliptical thickness profile of a dispensed solution. / Graduation date: 2013

Transparent oxide semiconductors (TOSs) are materials that exhibit electrical conduction and optical transparency. The traditional applications of these materials are transparent conducting oxides in flat-panel displays, light-emitting diodes, solar cells, and imaging sensors. Recently, significant research has been driven to extend state-of-the-art applications such as thin-film transistors (TFTs). A new and rapidly developing field is emerging, called transparent electronics. This thesis advances transparent electronics through developing a new technique to fabricate TOSs and demonstrating their applications to active semiconductor devices such as diodes and TFTs. Ion beam assisted evaporation (IBAE) is used to deposit two common TOSs: zinc oxide (ZnO) and indium oxide (In2O3). The detailed material study is carried out through various characterization of their electrical properties, chemical composition, optical properties, crystal structure, intrinsic stress, topology, and morphology, as well as an investigation of thin-film property as a function of the deposition parameters: ion flux and energy, and deposition rate. The study proves that IBAE technique provides the capability for fabricating TOSs with controllable properties. By utilizing the newly developed semiconducting ZnO, p-NiO/i-ZnO/n-ITO and n-ITO/i-ZnO/p-NiO heterostructure photodiodes with a low leakage are proposed and assessed. Analysis of their current-voltage characteristics and current transient behaviour reveals that the dominant source of leakage current stems from the deep defect states in the intrinsic zinc oxide layer, where its dynamic response at low signal levels is limited by the charge trapping. The exploration of the photoconduction mechanism and spectral response confirms that such photodiodes are potentially applicable for ultraviolet (UV) sensors. The comparative study of both device structures provides further insights into the leakage current mechanisms, p-i interface properties, and quantum efficiency. Secondly, with the novel semiconducting In2O3, TFTs are fabricated and evaluated. The device performance is optimized by addressing the source/drain contact issue, lowering the intrinsic channel resistance, and improving the dielectric/channel interface. The best n-channel TFT has a high field-effect mobility of ~30 cm^2/Vs, a high current ON/OFF ratio of ~10^8, and a sub-threshold slope of 2.0 V/decade. More important, high-performance indium oxide TFTs here are integrated with the silicon dioxide and silicon nitride gate dielectrics by conventional plasma-enhanced chemical vapour deposition, which makes indium oxide TFT a competitive alternative for next generation TFTs to meet the technical requirements for flat-panel displays, large area imager arrays, and radio frequency identification tags. The stability study shows that indium oxide TFTs are highly stable with a very small threshold voltage shift under both a long-term constant voltage and long-term current stress. The dynamic behaviour indicates factors that affect the operation speed of such TFTs. A descriptive model is proposed to link the material properties and the processing issues with the device performance to facilitate further research and development of TOS TFTs. The research described in this thesis is one of the first investigations of the fabrication of TOSs by the IBAE and their applications to a variety of thin-film devices, particularly UV sensors and TFTs.

Transparent oxide semiconductors (TOSs) are materials that exhibit electrical conduction and optical transparency. The traditional applications of these materials are transparent conducting oxides in flat-panel displays, light-emitting diodes, solar cells, and imaging sensors. Recently, significant research has been driven to extend state-of-the-art applications such as thin-film transistors (TFTs). A new and rapidly developing field is emerging, called transparent electronics. This thesis advances transparent electronics through developing a new technique to fabricate TOSs and demonstrating their applications to active semiconductor devices such as diodes and TFTs. Ion beam assisted evaporation (IBAE) is used to deposit two common TOSs: zinc oxide (ZnO) and indium oxide (In2O3). The detailed material study is carried out through various characterization of their electrical properties, chemical composition, optical properties, crystal structure, intrinsic stress, topology, and morphology, as well as an investigation of thin-film property as a function of the deposition parameters: ion flux and energy, and deposition rate. The study proves that IBAE technique provides the capability for fabricating TOSs with controllable properties. By utilizing the newly developed semiconducting ZnO, p-NiO/i-ZnO/n-ITO and n-ITO/i-ZnO/p-NiO heterostructure photodiodes with a low leakage are proposed and assessed. Analysis of their current-voltage characteristics and current transient behaviour reveals that the dominant source of leakage current stems from the deep defect states in the intrinsic zinc oxide layer, where its dynamic response at low signal levels is limited by the charge trapping. The exploration of the photoconduction mechanism and spectral response confirms that such photodiodes are potentially applicable for ultraviolet (UV) sensors. The comparative study of both device structures provides further insights into the leakage current mechanisms, p-i interface properties, and quantum efficiency. Secondly, with the novel semiconducting In2O3, TFTs are fabricated and evaluated. The device performance is optimized by addressing the source/drain contact issue, lowering the intrinsic channel resistance, and improving the dielectric/channel interface. The best n-channel TFT has a high field-effect mobility of ~30 cm^2/Vs, a high current ON/OFF ratio of ~10^8, and a sub-threshold slope of 2.0 V/decade. More important, high-performance indium oxide TFTs here are integrated with the silicon dioxide and silicon nitride gate dielectrics by conventional plasma-enhanced chemical vapour deposition, which makes indium oxide TFT a competitive alternative for next generation TFTs to meet the technical requirements for flat-panel displays, large area imager arrays, and radio frequency identification tags. The stability study shows that indium oxide TFTs are highly stable with a very small threshold voltage shift under both a long-term constant voltage and long-term current stress. The dynamic behaviour indicates factors that affect the operation speed of such TFTs. A descriptive model is proposed to link the material properties and the processing issues with the device performance to facilitate further research and development of TOS TFTs. The research described in this thesis is one of the first investigations of the fabrication of TOSs by the IBAE and their applications to a variety of thin-film devices, particularly UV sensors and TFTs.