abstract: Global industrialization and urbanization have led to increased levels of air pollution. The costs to society have come in the form of environmental damage, healthcare expenses, lost productivity, and premature mortality. Measuring pollutants is an important task for identifying its sources, warning individuals about dangerous exposure levels, and providing epidemiologists with data to link pollutants with diseases. Current methods for monitoring air pollution are inadequate though. They rely on expensive, complex instrumentation at limited fixed monitoring sites that do not capture the true spatial and temporal variation. Furthermore, the fixed outdoor monitoring sites cannot warn individuals about indoor air quality or exposure to chemicals at worksites. Recent advances in manufacturing and computing technology have allowed new classes of low-cost miniature gas sensor to emerge as possible alternatives. For these to be successful however, there must be innovations in the sensors themselves that improve reliability, operation, and their stability and selectivity in real environments. Three novel gas sensor solutions are presented. The first is the development of a wearable personal exposure monitor using all commercially available components, including two metal oxide semiconductor gas sensors. The device monitors known asthma triggers: ozone, total volatile organic compounds, temperature, humidity, and activity level. Primary focus is placed on the ozone sensor, which requires special circuits, heating algorithm, and calibration to remove temperature and humidity interferences. Eight devices are tested in multiple field tests. The second is the creation of a new compact optoelectronic gas sensing platform using colorimetric microdroplets printed on the surface of a complementary-metal-oxide-semiconductor (CMOS) imager. The nonvolatile liquid microdroplets provide a homogeneous, uniform environment that is ideal for colorimetric reactions and lensless optical measurements. To demonstrate one type of possible indicating system gaseous ammonia is detected by complexation with Cu(II). The third project continues work on the CMOS imager optoelectronic platform and develops a more robust sensing system utilizing hydrophobic aerogel particles. Ammonia is detected colorimetrically by its reaction with a molecular dye, with additives and surface treatments enhancing uniformity of the printed films. Future work presented at the end describes a new biological particle sensing system using the CMOS imager. / Dissertation/Thesis / Doctoral Dissertation Materials Science and Engineering 2020

Emerging transparent semiconducting oxide (TSO) materials have achieved their initial commercial success in the display industry. Due to the advanced electrical performance, TSOs have been adopted either to improve the performance of traditional displays or to demonstrate the novel transparent and flexible displays. However, due to the lack of feasible p-type TSOs, the applications of TSOs is limited to unipolar (n-type TSOs) based devices. Compared with the prosperous n-type TSOs, the performance of p-type counterparts is lag behind. However, after years of discovery, several p-type TSOs are confirmed with promising performance, for example, tin monoxide (SnO). By using p-type SnO, excellent transistor field-effect mobility of 6.7 cm2 V-1 s-1 has been achieved. Motivated by this encouraging performance, this dissertation is devoted to further evaluate the feasibility of integrating p-type SnO in p-n junctions and complementary metal oxide semiconductor (CMOS) devices. CMOS inverters are fabricated using p-type SnO and in-situ formed n-type tin dioxide (SnO2). The semiconductors are simultaneously sputtered, which simplifies the process of CMOS inverters. The in-situ formation of SnO2 phase is achieved by selectively sputtering additional capping layer, which serves as oxygen source and helps to balance the process temperature for both types of semiconductors. Oxides based p-n junctions are demonstrated between p-type SnO and n-type SnO2 by magnetron sputtering method. Diode operating ideality factor of 3.4 and rectification ratio of 103 are achieved. A large temperature induced knee voltage shift of 20 mV oC-1 is observed, and explained by the large band gap and shallow states in SnO, which allows minor adjustment of band structure in response to the temperature change. Finally, p-type SnO is used to demonstrating the hybrid van der Waals heterojunctions (vdWHs) with two-dimensional molybdenum disulfide (2D MoS2) by mechanical exfoliation. The hybrid vdWHs show excellent rectifying performance. Due to the ultra-thin nature of MoS2, the operation of hybrid vdWHs is gate-tunable, and we further discover such gate-tunability depends on the layer number of MoS2, i.e., the screening effect. The detailed study in such hybrid vdWHs provides valuable information for understanding the switching performance of junctions contain 2D materials.

京都大学 / 0048 / 新制・課程博士 / 博士(工学) / 甲第19737号 / 工博第4192号 / 新制||工||1646(附属図書館) / 32773 / 京都大学大学院工学研究科物質エネルギー化学専攻 / (主査)教授 阿部 竜, 教授 陰山 洋, 教授 田中 庸裕 / 学位規則第4条第1項該当 / Doctor of Philosophy (Engineering) / Kyoto University / DFAM

京都大学 / 0048 / 新制・課程博士 / 博士(工学) / 甲第21110号 / 工博第4474号 / 新制||工||1695(附属図書館) / 京都大学大学院工学研究科電子工学専攻 / (主査)教授 木本 恒暢, 教授 藤田 静雄, 教授 白石 誠司 / 学位規則第4条第1項該当 / Doctor of Philosophy (Engineering) / Kyoto University / DFAM

The semiconductor industry scaling has mainly been driven by Moore's law, which states that the number of transistors on a single chip should double every year and a half to two years. Beyond 2011, when the channel length of the Metal Oxide Field effect transistor (MOSFET) approaches 16 nm, the scaling of the planar MOSFET is predicted to reach its limit. Consequently, a departure from the current planar MOSFET on bulk silicon substrate is required to push the scaling limit further while maintaining electrostatic control of the gate over the channel. Alternative device structures that allow better control of the gate over the channel such as reducing short channel effects, and minimizing second order effects are currently being investigated. Such novel device architectures such as Fully-Depleted (FD) planar Silicon On Insulator (SOI) MOSFETS, Triple gate SOI MOSFET and Gate-All-Around Nanowire (NW) MOSFET utilize Silicon on Insulator (SOI) substrates to benefit from the bulk isolation and reduce second order effects due to parasitic effects from the bulk. The doping of the source and drain regions and the redistribution of the dopants in the channel greatly impact the electrical characteristics of the fabricated device. Thus, in nano-scale and reduced dimension transistors, a tight control of doping levels and formation of pn junctions is required. Therefore, deeper understanding of the lateral component of the diffusion mechanisms and interface effects in these lower dimensional structures compared to the bulk is necessary. This work focuses on studying the dopant diffusion mechanisms in Silicon nanomembranes (2D), nanoribbons (â 1.Xâ D), and nanowires (1D). This study also attempts to benchmark the 1D and 2D diffusion against the well-known bulk (3D) diffusion mechanisms. / Master of Science

付記する学位プログラム名: 京都大学卓越大学院プログラム「先端光・電子デバイス創成学」 / 京都大学 / 新制・課程博士 / 博士(工学) / 甲第24623号 / 工博第5129号 / 新制||工||1980(附属図書館) / 京都大学大学院工学研究科電子工学専攻 / (主査)教授 木本 恒暢, 教授 川上 養一, 准教授 浅野 卓 / 学位規則第4条第1項該当 / Doctor of Philosophy (Engineering) / Kyoto University / DFAM

Developing high efficiency solar cells for lower manufacturing costs has been a key objective for photovoltaic researchers to drive down the levelized cost of energy for solar power. In this pursuit, III-V compound semiconductor based solar cells have steadily shown performance improvement at approximately 1% (absolute) increase per year, with a recent record efficiency of 46% under concentrator and 32% under AM0. However, the expensive cost has made it challenging for III-V solar cells to compete with the mainstream Silicon (Si) technology. Novel approaches to lower down the cost per watt for III-V solar cells will position them to be among the key contenders in the renewable energy sector. Integration of such high-efficiency III-V multijunction solar cells on significantly cheaper and large area Si substrate has the potential to address the future LCOE roadmaps by unifying the high-efficiency merits of III-V materials with low-cost and abundance of Si. However, the 4% lattice mismatch, thermal mismatch, polar on non-polar epitaxy makes the direct growth of GaAs on Si challenging, rendering the metamorphic cell sensitive to dislocations. The focus of this dissertation is to investigate heterogeneously integrated 1J GaAs solar cells on Si substrate using germanium (Ge) as an intermediate buffer layer that will address mitigation of defects and dislocations between GaAs active cell structure and Ge “virtual” substrate on Si. The all-epitaxial molecular beam epitaxy (MBE)-grown thin (<1 μm) hybrid GaAs/Ge “virtual” buffer approach provided 1J GaAs cell efficiency of ~10% on Si, as compared with cell structures with thick 3 μm GaAs buffers. Solar cell results were further corroborated with material analysis to provide a clear path for the reduction of performance limiting dislocations. The thin “Ge-on-Si” virtual buffer was then investigated comprehensively to understand the impact of the heterostructure on device performance. The growth, structural, morphological, and electrical transport properties of epitaxial thin-film Ge, grown by solid source MBE on Si using a two-step growth process, were investigated. High-resolution x-ray diffraction analysis demonstrated ~0.10% tensile strained Ge epilayer, owing to the thermal expansion coefficient mismatch between Ge and Si, and negligible epilayer lattice tilt due to misfit dislocations at the Ge/Si heterointerface. Micro-Raman spectroscopic analysis further corroborated the strain-state of the Ge thin-film on Si. Cross-sectional transmission electron microscopy revealed the formation of a 90° Lomer dislocation network at the Ge/Si heterointerface, suggesting the rapid and complete relaxation of the Ge epilayer during growth. Atomic force micrographs exhibited smooth surface morphologies with surface roughness < 2 nm. Hall mobility measurements, performed within a temperature range of 77 K to 315 K, and the modelling thereof indicated that ionized impurity scattering limited carrier mobility in the thin Ge epilayer. Additionally, capacitance- and conductance-voltage measurements were performed after fabricating the metal-oxide-semiconductor capacitors (MOS-Cs) in order to determine the effect of epilayer dislocation density on interfacial defect states (Dit), bulk trap density, and the energy distribution of Dit as a function of temperature for electronic device applications. Deep level transient spectroscopy was used to identify the location (within the Ge bandgap) of electrically active trap levels; however, no significant trap levels were detected. Finally, the extracted Dit values were benchmarked against previously reported Dit data for Ge MOS devices, as a function of threading dislocation density within the Ge layer. The results obtained in this work were found to be comparable with other Ge MOS devices integrated on Si via alternative buffer schemes. The understanding gained from this comprehensive study of Ge-on-Si will help optimize the 1J GaAs on Si via thin Ge buffer approach, to enable a future of high efficiency low cost solar cells for terrestrial applications. / Master of Science / The global energy landscape is projected to change remarkably in the coming decades with dwindling carbon based resource reserves and escalating energy demands, necessitating large-scale adoption of cleaner alternatives, such as solar energy. However, for widespread commercial and domestic adoption of photovoltaics, the cost of solar generated electricity must become competitive with non-renewable resources such as oil or coal. Thus, achieving high efficiency solar cells and driving down cell costs are key research objectives of the photovoltaic (PV) community in order to become more self-sufficient in the energy sector. In this pursuit, III-V compound semiconductor-based solar cells have steadily outperformed all other PV technologies, but cost-prohibitive for terrestrial deployment. Si is the undisputed standard in the PV industry; thus, to make a significant step forward in the pursuit of high efficiency solar cells, a promising approach will be to integrate the superior properties of compound semiconductors with the mature technology of Si. This research systematically investigates the integration of high efficiency III-V cells with low cost, abundant Si substrates via a germanium (Ge) layer to unify the performance merits of III-V cells with the cost benefits and superior mechanical and thermal properties of Si. Concurrently, Ge has also emerged as a strong candidate to boost transistor performance at low operating voltages, primarily owing to its superior carrier mobility and ease of integration into mainstream Si process flow. This research further delves into the structural and electrical properties of the Ge on Si structure. Overall, this research demonstrates the feasibility of the use of Ge directly integrated on Si for high efficiency solar cells and low-power electronic devices.

The aggressive scaling of silicon (Si) based complementary metal-oxide-semiconductor (CMOS) transistor over the past 50 years has resulted in an exponential increase in device density, which consequentially has increased computation power rapidly. This has pronounced the necessity to scale the device's supply voltage (VDD) in to order to maintain low-power device operation. However, the scaling of VDD can degrade drive current significantly due to the low carrier mobility of Si. To overcome the key challenges of dimensional and voltage scaling required for low-power electronic operation without degradation of device characteristics, the adoption of alternate channel materials with low bandgap with superior transport properties will play a crucial role to improve the computation ability of the standard integrated circuit (IC). The requirement of high-mobility channel materials allows the industry to harness the potential of III-V semiconductors and germanium. However, the adoption of such high mobility materials as bulk substrates remains cost-prohibitive even today. Hence, another key challenge lies in the heterogeneous integration of epitaxial high-mobility channel materials on the established cost-effective Si platform. Furthermore, dimensional scaling of the device has led to a change in architecture from the conventional planar MOSFET to be modified to a 3-D Tri-gate architecture which provides fully depleted characteristics by increasing the inversion layer area and hence, providing superior electrostatic control of the device channel to address short channel effects such as subthreshold slope (SS) and drain induced barrier lowering (DIBL). The Tri-gate configuration provides a steeper SS effectively reducing leakage current (IOFF), thereby decreasing dynamic power consumption and increasing device performance. Recently, Tantalum silicate (TaSiOx) a high-k dielectric has been shown to exhibit superior interfacial quality on multiple III-V materials. However, there is still ambiguity as to the potential of short-channel devices incorporating alternate channel (III-V) materials which is the basis of this research, to demonstrate the feasibility of future high-mobility n-channel InGaAs material integration on Si for high- speed, low-power, high performance CMOS logic applications. / Master of Science

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