The low dimensions of the state-of-the-art nanoscale transistors exhibit increasing quantum mechanical effects, which are no longer negligible. Gate tunneling current is one of such effects, that is responsible for high power consumption and high working temperature in microprocessors. This in turn put limits on further down scaling of devices. Therefore modeling and calculation of tunneling current is of a great interest. This work provides a review of existing models for the calculation of the gate tunneling current in MOSFETs. The quantum mechanical effects are studied with a model, based on a self-consistent solution of the Schrödinger and Poisson equations within the effective mass approximation. The calculation of the tunneling current is focused on models based on the calculation of carrier’s lifetime on quasi-bound states (QBSs). A new method for the determination of carrier’s lifetime is suggested and then the tunneling current is calculated for different samples and compared to measurements. The model is also applied to the extraction of the “tunneling effective mass” of electrons in ultrathin oxynitride gate dielectrics. Ultrathin gate dielectrics (tox<2 nm) consist of only few atomic layers. Therefore, atomic scale deformations at interfaces and within the dielectric could have great influences on the performance of the dielectric layer and consequently on the tunneling current. On the other hand the specific material parameters would be changed due to atomic level deformations at interfaces. A combination of DFT and NEGF formalisms has been applied to the tunneling problem in the second part of this work. Such atomic level ab initio models take atomic level distortions automatically into account. An atomic scale model interface for the Si/SiO2 interface has been constructed and the tunneling currents through Si/SiO2/Si stack structures are calculated. The influence of single and double oxygen vacancies on the tunneling current is investigated. Atomic level distortions caused by a tensile or compression strains on SiO2 layer as well as their influence on the tunneling current are also investigated. / Die vorliegende Arbeit beschäftigt sich mit der Berechnung von Tunnelströmen in MOSFETs (Metal-Oxide-Semiconductor Field Effect Transistors). Zu diesem Zweck wurde ein quantenmechanisches Modell, das auf der selbstkonsistenten Lösung der Schrödinger- und Poisson-Gleichungen basiert, entwickelt. Die Gleichungen sind im Rahmen der EMA gelöst worden. Die Lösung der Schrödinger-Gleichung unter offenen Randbedingungen führt zur Berechnung von Ladungsverteilung und Lebensdauer der Ladungsträger in den QBSs. Der Tunnelstrom wurde dann aus diesen Informationen ermittelt. Der Tunnelstrom wurde in verschiedenen Proben mit unterschiedlichen Oxynitrid Gatedielektrika berechnet und mit gemessenen Daten verglichen. Der Vergleich zeigte, dass die effektive Masse sich sowohl mit der Schichtdicke als auch mit dem Stickstoffgehalt ändert. Im zweiten Teil der vorliegenden Arbeit wurde ein atomistisches Modell zur Berechnung des Tunnelstroms verwendet, welche auf der DFT und NEGF basiert. Zuerst wurde ein atomistisches Modell für ein Si/SiO2-Schichtsystem konstruiert. Dann wurde der Tunnelstrom für verschiedene Si/SiO2/Si-Schichtsysteme berechnet. Das Modell ermöglicht die Untersuchung atom-skaliger Verzerrungen und ihren Einfluss auf den Tunnelstrom. Außerdem wurde der Einfluss einer einzelnen und zwei unterschiedlich positionierter neutraler Sauerstoffleerstellen auf den Tunnelstrom berechnet. Zug- und Druckspannungen auf SiO2 führen zur Deformationen in den chemischen Bindungen und ändern den Tunnelstrom. Auch solche Einflüsse sind anhand des atomistischen Modells berechnet worden.

Since metal-oxide-semiconductor (MOS) devices have been adopted into integrated circuits, the endless demands for higher performance and lower power consumption have been a primary challenge and a technology-driver in the semiconductor electronics. The invention of complementary MOS (CMOS) technology in the 1980s, and the introduction of voltage and physical dimension scaling in the 1990s would be good examples to keep up with the everlasting demands. In the 2000s, technology continuously evolves and seeks for more power efficiency ways such as high-k dielectrics, metal gate electrodes, strained substrates, and high mobility channel materials. As a gate dielectric, silicon dioxide (SiO₂), most widely used in CMOS integrated circuits, has many prominent advantages, including a high quality interface (e.g. Dit ~ low 1010 cm-2eV-1), a good thermal stability in contact with silicon (Si), a large energy bandgap and the large energy band offsets in reference to Si, and a high quality dielectric itself. As the thickness of SiO₂ keeps shrinking, however, SiO₂ is facing its physical limitations from the viewpoint of gate dielectric leakage currents and reliability requirements. High-k dielectric materials have attracted extensive attention in the last decade due to their great potential for maintaining further down-scaling in equivalent oxide thickness (EOT) and a low dielectric leakage current. HfO₂ has been considered as one of the most promising candidates because of a high dielectric constant (k ~ 20-25), a large energy band gap (~ 6 eV) and the large band offsets (> 1.5 eV), and a good thermal stability. To enhance carrier mobility, strained substrates and high mobility channel materials have attracted a great deal of attention, thus III-V compound semiconductor substrates have emerged as one of possible candidates, in spite of several technical barriers, being believed as barriers so far. The absence of high quality and thermodynamically stable native oxide, like SiO₂ on Si, has been one such hurdle to implement MOS systems on III-V substrates. However, recently, there have been a number of remarkable improvements on MOS applications on them, inspiring more vigorous research activities. In this research, HfO2-based MOS capacitors and metal-oxidesemiconductor field effect transistors (MOSFETs) with a thin germanium (Ge) interfacial passivation layer (IPL) on III-V compound substrates were investigated. It was found that a thin Ge IPL could effectively passivate the surface of III-V substrate, consequently providing a high quality interface and an excellent gate oxide scalability. N-channel MOSFETs on GaAs, InGaAs, and InP substrates were successfully demonstrated and a minimum EOT of ~ 9 Å from MOS capacitors was achieved. This research has begun with GaAs substrate, and then expanded to InGaAs, InP, InAs, and InSb substrates, which eventually helped to understand the role of a Ge IPL and to guide future research direction. Overall, MOS devices on III-V substrates with an HfO₂ gate dielectric and a Ge IPL have demonstrated feasibility and potential for further investigations. / text

A new quantum transport simulator -- Schrödinger Equation Monte Carlo in Three Dimensions (SEMC-3D) -- has been developed for simulating the carrier transport in nanoscale 3D MOSFET geometries. SEMC-3D self-consistently solves: (1) the 1D quantum transport equations derived from the SEMC method with open boundary conditions and rigorous treatment of various scattering processes including phonon and surface roughness scattering, (2) the 2D Schrödinger equations of the device cross sections with close boundary conditions to obtain the spatially varying subband structure along the conduction channel, and (3) the 3D Poisson equation of the whole device. Therefore, SEMC-3D can provide a physically accurate and electrostatically selfconsistent approach to the quantum transport in the subbands of 3D nanoscale MOSFETs. SEMC-3D has been used to simulate Si nanowire (NW) nMOSFETs to both demonstrate the capabilities of SEMC-3D, itself, and to provide new insight into transport phenomena in nanoscale MOSFETs, particularly with regards to interplay among scattering, quantum confinement and transport, and strain. / text

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L'industrie microélectronique est régie depuis plusieurs années par la loi de miniaturisation. En particulier, en technologie CMOS, les procédés de fabrication de l'oxyde permettant l'isolation électrique entre les transistors nécessitent sans cesse d'être améliorés pour répondre aux défis de cette loi. Ainsi, on est passé du procédé d'isolation par oxydation localisée de silicium (LOCOS) au procédé d'isolation par tranchées (STI). Cependant, ce dernier a montré pour les technologies en développement des limitations liées au remplissage non parfait par la silice de tranchées de moins en moins larges (Voiding) et au ''surpolissage'' des zones les plus larges (Dishing). Le procédé FIPOS (full isolation by porous oxidation of silicon) a été donc proposé comme solution alternative. Il est basé sur la formation sélective et localisée du silicium poreux qui est transformé ensuite en silice par un recuit oxydant. Cette piste prometteuse a constitué le point de départ de ce travail. Dans ce contexte, la thèse s'est focalisée sur deux axes principaux qui concernaient d'une part la maîtrise du procédé d'anodisation électrochimique pour la formation du silicium poreux et d'autre part l'optimisation du procédé d'oxydation. Dans une première partie de notre travail, l'analyse des caractéristiques courant-tension I-V menée sur le silicium durant son anodisation électrochimique a permis de montrer que la formation du silicium poreux dépend fortement de la concentration en dopants. Cette propriété nous a permis de développer une technique simple d'extraction du profil de dopage dans le silicium de type p par voie électrochimique. On a montré que la résolution en profondeur de cette technique est liée au niveau du dopage et s'approche de celle du SIMS (spectroscopie de masse d'ions secondaires) pour les fortes concentrations avec une valeur estimée à 60 nm/décade. Dans une deuxième partie, nous avons mis en évidence la formation localisée du silicium poreux oxydé. En effet, un choix judicieux du potentiel d'anodisation permet de rendre poreux sélectivement des régions fortement dopées implantées sur un substrat de silicium faiblement dopé. Ces régions sont ensuite transformées en oxyde par un recuit oxydant. Par ailleurs, les conditions optimales des processus d'oxydation et d'anodisation permettant d'obtenir un oxyde final de bonne qualité diélectrique sont analysées.

En dépit du développement rapide de la médecine, les maladies cardiovasculaires restent la première cause de mortalité dans le monde. En France, chaque année, plus de 50 000 personnes meurent subitement en raison d'arythmies cardiaques. L'identification des patients à risque élevé de décès soudain est toujours un défi. Pour détecter les arythmies cardiaques, actuellement Holter est généralement utilisé pour enregistrer les signaux électrocardiogramme (ECG) à 1~3 dérivations pendant 24h à 72h. Cependant l'utilisation de Holter est limitée parmi la population en raison de son encombrement (pas convivial) et de son coût. Un Holter mono puce portable nommé SoC-Holter qui permet d'enregistrer 1 à 4 dérivations est introduit. Le déploiement d'un réseau de capteurs sans fil exige que chaque SoC-Holter soit peu encombrant et peu cher, et consomme peu d'énergie. Afin de minimiser la consommation d'énergie et le coût du système, la technologie Complementary Metal Oxide Semiconductor (CMOS) (0.35μm) est utilisée pour la première implémentation de SoC-Holter. Puis une nouvelle méthode de détection basée sur Acquisition Comprimée (CS) est introduite pour résoudre les problèmes de consommation d'énergie et de capacité de stockage de SoC-Holter. Le principe premier de cette plate-forme est d'échantillonner les signaux ECG sous la fréquence de Nyquist 'sub-Nyquist' et par la suite de classer directement les mesures compressées en états normal et anormal. Minimiser le nombre de fils qui relient les électrodes à la plate-forme peut rendre l'utilisateur de SoC-Holter plus confortable, car deux électrodes sont très proches sur la surface du corps. La différence ECG enregistrée est analysée à l'aide de Vectocardiogramme (VCG). Les résultats expérimentaux montrent qu'une approche intégrée, à faible coût et de faible encombrement (SoC-Holter) est faisable. Le SoC-Holter consomme moins de 10mW en fonctionnement. L'estimation des paramètres du signal acquis est effectuée directement à partir de mesures compressées, éliminant ainsi l'étape de la reconstruction et réduisant la complexité et le volume des calculs. En outre, le système fournit les signaux ECG compressés sans perte d'information, de ce fait il réduit significativement la consommation d'énergie pour l'envoi de message et l'espace de stockage mémoire. L'effet de placement des électrodes est évalué sur la QRS complexe lorsqu'il a enregistré avec deux électrodes adjacentes. La méthode est basée sur l'algorithme de 'QRS-VCG loop alignment'. La méthode moindre carré est utilisée pour estimer la corrélation entre une boucle VCG observée et une boucle de référence en respectant les transformations de rotation et la synchronisation du temps. Les emplacements d'électrodes les moins sensibles aux interférences sont étudiés.

The objective of this research is to develop novel capacitive micromachined ultrasonic transducer (CMUT) arrays for intravascular ultrasonic (IVUS) imaging along with the fabrication processes to allow for monolithic integration of CMUTs with custom CMOS electronics for improved performance. The IVUS imaging arrays include dual-ring arrays for forward-looking volumetric imaging in coronary arteries and annular-ring arrays with dynamic focusing capabilities for side-looking cross sectional imaging applications. Both are capable of integration into an IVUS catheter 1-2 mm in diameter. The research aim of monolithic integration of CMUTs with custom CMOS electronics has been realized mainly through the use of sloped sidewall vias less than 5 µm in diameter, with only one additional masking layer as compared to regular CMUT fabrication. Fabrication of CMUTs has been accomplished with a copper sacrificial layer reducing isolation layers by 50%. Modeling techniques for computational efficient analysis of CMUT arrays were developed for arbitrary geometries and further expanded for use with larger signal analysis. Dual-ring CMUT arrays for forward-looking volumetric imaging have been fabricated with diameters of less than 2 mm with center frequencies at 10 MHz and 20 MHz, respectively, for an imaging range from 1 mm to 1 cm. These arrays, successfully integrated with custom CMOS electronics, have generated 3D volumetric images with only 13 cables necessary. Performance from optimized fabrication has reduced the bias required for a dual-ring array element from 80 V to 42 V and in conjunction with a full electrode transmit array, it was shown that the SNR can be improved by 14 dB. Simulations were shown to be in agreement with experimental characterization indicated transmit surface pressure in excess of 8 MPa. For side-looking IVUS, three versions of annular CMUT arrays with dynamic focusing capabilities have been fabricated for imaging 1 mm to 6 mm in tissue. These arrays are 840 µm in diameter membranes linked to form 8 ring elements with areas that deviate by less than 25 %. Through modeling and simulation undesirable acoustic cross between ring elements was reduced from -13 dB to -22 dB.

Amorphous oxide semiconductors (AOSs) are of great current interest for thin-film transistor (TFT) channel layer applications. In particular, indium gallium zinc oxide (IGZO) is under intense development for commercial applications because of its demonstrated high performance at low processing temperatures. The objective of the research presented in this thesis is to provide detailed assessments of device stability, temperature dependence, and related phenomena for IGZO-based TFTs processed at temperatures between 200 °C and 300 °C. TFTs tested exhibit an almost rigid shift in log₁₀(I[subscript D]) – V[subscript GS] transfer curves in which the turn-on voltage, V[subscript ON], moves to a more positive gate voltage with increasing stress time during constant-voltage bias-stress testing of IGZO TFTs. TFT stability is improved as the post-deposition annealing temperature increases over the temperature range of 200 – 300 ºC. The turn-on voltage shift induced by constant-voltage bias-stressing is at least partially reversible; V[subscript ON] tends to recover towards its initial value of V[subscript ON] if the TFT is left unbiased in the dark for a prolonged period of time and better recovery is observed for a longer recovery period. V[subscript ON] for a TFT can be set equal to zero after bias-stress testing if the TFT electrodes are grounded and the TFT is maintained in the dark for a prolonged period of time. Attempts to accelerate the recovery process by application of a negative gate bias at elevated temperature (i.e., 100 ºC) were unsuccessful, resulting in severely degraded subthreshold swing. An almost rigid log₁₀(I[subscript D]) – V[subscript GS] transfer curve shift to a lower (more negative) V[subscript ON] with increasing temperature is observed in the range of –50 °C to +50 °C, except for a TFT with an initial V[subscript ON] equal to zero, in which case the log₁₀(ID) – V[subscript GS] transfer curve is temperature-independent. A more detailed temperature-dependence assessment, however, indicates that the log₁₀(I[subscript D]) – V[subscript GS] transfer curve shift is not exactly rigid since the mobility is found to increase slightly with increasing temperature. A noticeable anomaly is observed in certain log₁₀(I[subscript D]) – VGS transfer curves, especially when obtained at elevated temperature (e.g., 30 and 50 ºC), in which I[subscript D] decreases precipitously near zero volts in the positive gate voltage sweep. This anomaly is attributed to a gate-voltage-step-involved detrapping and subsequent retrapping of electrons in the accumulation channel and/or channel/gate insulator interface. In fact, all IGZO TFT stability and temperature-dependence trends are attributed to channel interface and/or channel bulk trapping/detrapping. / Graduation date: 2009

Thesis (M.App.Sc.) - Carleton University, 2007. / Includes bibliographical references (p. 73-76). Also available in electronic format on the Internet.