The temperature sensor design discussed in this thesis, is meant mainly to monitor temperature at power outlets. Current variations in power cords have a direct impact on the surrounding temperature. Sensing these variations ,enables us to take necessary measures to prevent any hazards due to temperature rise. Thus, for this application we require a sensor with a moderate temperature error (_10C) over a sensing range of -200C to 1500C. Low power consumption and simple digitizing scheme alleviate measurement errors due to self heating effects of the sensor. A current starved inverter based ring oscillator was chosen for the sensor design in 130nm technology. The inverter delay variation with temperature is used for sensing. Linearity and process invariancy of these characteristics are fundamental to the sensor design. We observed through simulations, and confirmed by mathematical analysis, that the sensing characteristics are governed by bias current dependence on temperature. Control voltage for the bias circuitry of the oscillator determines current through the inverter stages. Hence, for linear sensing characteristics, a control voltage(Vc) just above the maximum threshold voltage of bias transistor is used. This enables generation of PTAT saturation current for current starved inverters, due to dominance of threshold voltage decrease with temperature over mobility decrease. I.Another limitation, process dependency of the sensing characteristics, was overcome through the proposed calibration based compensation technique. A changing Vc proportional to threshold voltage variation with process, process independent bias current and current temperature characteristics were obtained. This compensated for the process variation effects on frequency. Thus, a variable Vc was generated using a reference with low temperature sensitivity of 17.6_V=0C, and resistive divider combinations for various processes. Incorporating this compensation technique we achieved good linearity in sensor characteristics and a maximum temperature error of± 1.60C over the sensing range. The sensor consumes a low power of 0.29mW and also occupies minimal area.

En exploitant la fonction d’amplification intrinsèque fournie par les transistors UTBB FDSOI, nous avons présenté des ISFET ultra sensibles. L'intégration de la fonctionnalité de détection a été réalisée en back end of line (BEOL), ce qui offre les avantages d'une fiabilité et d'une durée de vie accrues du capteur, d'une compatibilité avec le processus CMOS standard et d'une possibilité d'intégration d'un circuit diviseur capacitif. Le fonctionnement des MOSFETs, sans une polarisation appropriée de la grille avant, les rend vulnérables aux effets de grilles flottantes indésirables. Le circuit diviseur capacitif résout ce problème en polarisant la grille avant tout en maintenant la fonctionnalité de détection sur la même grille par un couplage capacitif au métal commun du BEOL. Par conséquent, le potentiel au niveau du métal BEOL est une somme pondérée du potentiel de surface au niveau de la grille de détection et de la polarisation appliquée au niveau de la grille de contrôle. Le capteur proposé est modélisé et simulé à l'aide de TCAD-Sentaurus. Un modèle mathématique complet a été développé. Il fournit la réponse du capteur en fonction du pH de la solution (entrée du capteur) et des paramètres de conception du circuit diviseur capacitif et du transistor UTBB FDSOI. Dans ce cas, des résultats cohérents ont été obtenus des travaux de modélisation et de simulation, avec une sensibilité attendue de 780 mV / pH correspondant à un film de détection ayant une réponse de Nernst. La modélisation et la simulation du capteur proposé ont également été validées par une fabrication et une caractérisation du capteur de pH à grille étendue avec validation de son concept. Ces capteurs ont été développés par un traitement séparé du composant de détection de pH, qui est connecté électriquement au transistor uniquement lors de la caractérisation du capteur. Ceci permet une réalisation plus rapide et plus simple du capteur sans avoir besoin de masques et de motifs par lithographie. Les capteurs à grille étendue ont présenté une sensibilité de 475 mV/pH, ce qui est supérieur aux ISFET de faible puissance de l'état de l’art. Enfin, l’intégration de la fonctionnalité de détection directement dans le BEOL des dispositifs FDSOI UTBB a été poursuivie. Une sensibilité expérimentale de 730 mV/pH a été obtenue, ce qui confirme le modèle mathématique et la réponse simulée. Cette valeur est 12 fois supérieure à la limite de Nernst et supérieure aux capteurs de l'état de l’art. Les capteurs sont également évalués pour la stabilité, la résolution, l'hystérésis et la dérive dans lesquels d'excellentes performances sont démontrées. / Exploiting the intrinsic amplification feature provided by UTBB FDSOI transistors, we demonstrated ultrahigh sensitive ISFETs. Integration of the sensing functionality was made in the BEOL which gives the benefits of increased reliability and life time of the sensor, compatibility with the standard CMOS process, and possibility for embedding a capacitive divider circuit. Operation of the MOSFETs without a proper front gate bias makes them vulnerable for undesired floating body effects. The capacitive divider circuit addresses these issues by biasing the front gate simultaneously with the sensing functionality at the same gate through capacitive coupling to a common BEOL metal. Therefore, the potential at the BEOL metal would be a weighted sum of the surface potential at the sensing gate and the applied bias at the control gate. The proposed sensor is modeled and simulated using TCAD-Sentaurus. A complete mathematical model is developed which provides the output of the sensor as a function of the solution pH (input to the sensor), and the design parameters of the capacitive divider circuit and the UTBB FDSOI transistor. In that case, consistent results have been obtained from the modeling and simulation works, with an expected sensitivity of 780 mV/pH corresponding to a sensing film having Nernst response. The modeling and simulation of the proposed sensor was further validated by a proof of concept extended gate pH sensor fabrication and characterization. These sensors were developed by a separated processing of just the pH sensing component, which is electrically connected to the transistor only during characterization of the sensor. This provides faster and simpler realization of the sensor without the need for masks and patterning by lithography. The extended gate sensors showed 475 mV/pH sensitivity which is superior to state of the art low power ISFETs. Finally, integration of the sensing functionality directly in the BEOL of the UTBB FDSOI devices was pursued. An experimental sensitivity of 730 mV/pH is obtained which is consistent with the mathematical model and the simulated response. This is more than 12-times higher than the Nernst limit, and superior to state of the art sensors. Sensors are also evaluated for stability, resolution, hysteresis, and drift in which excellent performances are demonstrated.

Ce travail de thèse présente la conception d’un convertisseur Buck 3 états pour améliorer le comportement dynamique des tensions d’alimentations des microprocesseurs. La topologie du convertisseur est dans un premier temps, implémentée en technologie IBM CMOS 180 nm pour la validation de la structure 3 états. Le prototype réalisé utilise une tension d’entrée de 3.6V et génère une tension de sortie de 0.8V à 2V. Sa réponse aux transitoires de charge ne montre que 1 à 2% de surtension prouvant ainsi l’avantage du régulateur en dynamique. Le convertisseur 3 états est dans un deuxième temps intégré en technologie 28 nm CMOS HPM (cette technologie est essentiellement utilisée pour les microprocesseurs). Les résultats des tests effectués sur le prototype réalisé confirment les performances en économie d’énergie, de surface et de réponse dynamique. Ce prototype délivre en effet 0.5 à 1.2V en sortie pour 1.8V en entrée et présente un rendement maximal de 90%. Les mesures de régulation dynamique montrent qu’il permet d’obtenir moins de 5% de bruit sur le processeur et 10 mV/ns de commutation de tensio / This thesis work consists into the design of a 3 states buck converter targeting the improvement of dynamic regulation of microprocessors supplies. The topology of the converter is, at first, implemented in IBMCMOS 180 nm technology to validate the transient performances of the3 states regulator. The prototype in 180 nm, uses an input voltage of 3.6V and outputs a voltage in the range of 0.8V to 2V. Its response to load transients shows about 1% of undershoot and 2 % of overshoot, proving a good dynamic behavior for a simple structure compared to state of the art.The 3 states converter is then integrated in 28 nm CMOS HPM (technologymostly used for microprocessors desgn). The experimental results on the prototype confirm the performances in terms of energy and area savings, aswell as dynamic response. The chip delivers 0.5V to 1.2V from a 1.8V supply,and shows a 90% peak efficiency. The measurements of dynamic regulation show less than 5% of noise on the processor supply and 10 mV/ns outputvoltage switching for DVFS purpose.

No description available.

L’intégration ultime de convertisseurs à découpage repose sur deux axes de recherche. Le premier axe est de développer les convertisseurs à capacités commutées. Cette approche est compatible avec une intégration totale sur silicium, mais limitée en terme de densité de puissance. Le second axe est l’utilisation de convertisseurs à inductances, qui pâtissent d’imposants composants passifs. Une augmentation de la fréquence permet de réduire les valeurs des composants passifs. Cependant une augmentation de la fréquence implique une augmentation des pertes par commutation, ce qui est contrebalancé par l’utilisation d’une technologie de fabrication plus avancée. Ces technologies plus avancées souffrent quant à elles de limitations au niveau de leur tension d’utilisation. Convertir une tension de 3,3V vers une tension de 1,2V apparait donc comme un objectif ambitieux, particulièrement dans le cas où les objectifs de taille minimale et de rendement supérieur à 90 % sont visés. Un assemblage 3D des composants actifs et passifs permet de minimiser la surface du système. Un fonctionnement à haute fréquence est aussi considéré, ce qui permet de réduire les valeurs requises pour les composants passifs. Dans le contexte de l’alimentation « on-chip », la technologie silicium est contrainte par les fonctions numériques. Une technologie 40 nm CMOS de type « bulk » est choisie comme cas d’étude pour une tension d’entrée de 3,3 V. Les transistors 3,3 V présentent une figure de mérite médiocre, les transistors 1,2 V sont donc choisis. Ce choix permet en outre de présenter une meilleure compatibilité avec une future intégration sur puce. Une structure cascode utilisant trois transistors en série est étudiée est confrontée à une structure standard à travers des simulations et mesures. Une fréquence de +100MHz est choisie. Une technologie de capacités en tranchées est sélectionnée, et fabriquée sur une puce séparée qui servira d’interposeur et recevra la puce active et les inductances. Les inductances doivent être aussi fabriquées de manière intégrée afin de limiter leur impact sur la surface du convertisseur. Ce travail fournit un objet contenant un convertisseur de type Buck à une phase, avec la puce active retournée (« flip-chip ») sur l’interposeur capacitif, sur lequel une inductance est rapportée. Le démonstrateur une phase est compatible pour une démonstration à phases couplées. Les configurations standard et cascode sont comparées expérimentalement aux fréquences de 100 MHz et 200 MHz. La conception de la puce active est l’élément central de ce travail, l’interposeur capacitif étant fabriqué par IPDiA et les inductances par Tyndall National Institute. L’assemblage des différents sous-éléments est réalisé via des procédés industriels. Un important ensemble de mesures ont été réalisées, montrant les performances du convertisseur DC-DC délivré, ainsi que ses limitations. Un rendement pic de 91,5 % à la fréquence de 100 MHz a été démontré. / Ultimate integration of power switch-mode converter relies on two research paths. One path experiments the development of switched-capacitor converters. This approach fits silicon integration but is still limited in term of power density. Inductive DC-DC architectures of converters suffer by the values and size of passive components. This limitation is addressed with an increase in frequency. Increase in switching losses in switches leads to consider advanced technological nodes. Consequently, the capability with respect to input voltage is then limited. Handling 3.3 V input voltage to deliver an output voltage in the range 0.6 V to 1.2 V appears a challenging specification for an inductive buck converter if the smallest footprint is targeted at +90 % efficiency. Smallest footprint is approached through a 3D assembly of passive components to the active silicon die. High switching frequency is also considered to shrink the values of passive components as much as possible. In the context of on-chip power supply, the silicon technology is dictated by the digital functions. Complementary Metal-Oxide- Semiconductor (CMOS) bulk C40 is selected as a study case for 3.3 V input voltage. 3.3 V Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) features poor figure of merits and 1.2 V standard core, regular devices are preferred. Moreover future integration as an on-chip power supply is more compatible. A three-MOSFET cascode arrangement is experimented and confronted experimentally to a standard buck arrangement in the same technology. The coupled-phase architecture enables to reduce the switching frequency to half the operating frequency of the passive devices. +100MHz is selected for operation of passive devices. CMOS bulk C40 offers Metal-Oxide-Metal (MOM) and MOS capacitors, in density too low to address the decoupling requirements. Capacitors have to be added externally to the silicon die but in a tight combination. Trench-cap technology is selected and capacitors are fabricated on a separate die that will act as an interposer to receive the silicon die as well as the inductors. The work delivers an object containing a one-phase buck converter with the silicon die flip-chipped on a capacitor interposer where a tiny inductor die is reported. The one-phase demonstrator is suitable for coupled-phase demonstration. Standard and cascode configurations are experimentally compared at 100 MHz and 200 MHz switching frequency. A design methodology is presented to cover a system-to-device approach. The active silicon die is the central design part as the capacitive interposer is fabricated by IPDiA and inductors are provided by Tyndall National Institute. The assembly of the converter sub-parts is achieved using an industrial process. The work details a large set of measurements to show the performances of the delivered DC/DC converters as well as its limitations. A 91.5% peak efficiency at 100MHz switching frequency has been demonstrated.

The low dimensions of the state-of-the-art nanoscale transistors exhibit increasing quantum mechanical effects, which are no longer negligible. Gate tunneling current is one of such effects, that is responsible for high power consumption and high working temperature in microprocessors. This in turn put limits on further down scaling of devices. Therefore modeling and calculation of tunneling current is of a great interest. This work provides a review of existing models for the calculation of the gate tunneling current in MOSFETs. The quantum mechanical effects are studied with a model, based on a self-consistent solution of the Schrödinger and Poisson equations within the effective mass approximation. The calculation of the tunneling current is focused on models based on the calculation of carrier’s lifetime on quasi-bound states (QBSs). A new method for the determination of carrier’s lifetime is suggested and then the tunneling current is calculated for different samples and compared to measurements. The model is also applied to the extraction of the “tunneling effective mass” of electrons in ultrathin oxynitride gate dielectrics. Ultrathin gate dielectrics (tox<2 nm) consist of only few atomic layers. Therefore, atomic scale deformations at interfaces and within the dielectric could have great influences on the performance of the dielectric layer and consequently on the tunneling current. On the other hand the specific material parameters would be changed due to atomic level deformations at interfaces. A combination of DFT and NEGF formalisms has been applied to the tunneling problem in the second part of this work. Such atomic level ab initio models take atomic level distortions automatically into account. An atomic scale model interface for the Si/SiO2 interface has been constructed and the tunneling currents through Si/SiO2/Si stack structures are calculated. The influence of single and double oxygen vacancies on the tunneling current is investigated. Atomic level distortions caused by a tensile or compression strains on SiO2 layer as well as their influence on the tunneling current are also investigated. / Die vorliegende Arbeit beschäftigt sich mit der Berechnung von Tunnelströmen in MOSFETs (Metal-Oxide-Semiconductor Field Effect Transistors). Zu diesem Zweck wurde ein quantenmechanisches Modell, das auf der selbstkonsistenten Lösung der Schrödinger- und Poisson-Gleichungen basiert, entwickelt. Die Gleichungen sind im Rahmen der EMA gelöst worden. Die Lösung der Schrödinger-Gleichung unter offenen Randbedingungen führt zur Berechnung von Ladungsverteilung und Lebensdauer der Ladungsträger in den QBSs. Der Tunnelstrom wurde dann aus diesen Informationen ermittelt. Der Tunnelstrom wurde in verschiedenen Proben mit unterschiedlichen Oxynitrid Gatedielektrika berechnet und mit gemessenen Daten verglichen. Der Vergleich zeigte, dass die effektive Masse sich sowohl mit der Schichtdicke als auch mit dem Stickstoffgehalt ändert. Im zweiten Teil der vorliegenden Arbeit wurde ein atomistisches Modell zur Berechnung des Tunnelstroms verwendet, welche auf der DFT und NEGF basiert. Zuerst wurde ein atomistisches Modell für ein Si/SiO2-Schichtsystem konstruiert. Dann wurde der Tunnelstrom für verschiedene Si/SiO2/Si-Schichtsysteme berechnet. Das Modell ermöglicht die Untersuchung atom-skaliger Verzerrungen und ihren Einfluss auf den Tunnelstrom. Außerdem wurde der Einfluss einer einzelnen und zwei unterschiedlich positionierter neutraler Sauerstoffleerstellen auf den Tunnelstrom berechnet. Zug- und Druckspannungen auf SiO2 führen zur Deformationen in den chemischen Bindungen und ändern den Tunnelstrom. Auch solche Einflüsse sind anhand des atomistischen Modells berechnet worden.

A novel, non-volatile, organic capacitive memory device called p-i-n-metal-oxide-semiconductor (pinMOS) memory is demonstrated with multiple-bit storage that can be programmed and read out electrically and optically. The diode-based architecture simplifies the fabrication process, and makes further optimizations easy, and might even inspire new derived capacitive memory devices. Furthermore, this innovative pinMOS memory device features local charge up of an integrated capacitance rather than of an extra floating gate. Before the device can perform as desired, the leakage current due to the lateral charge up of the doped layers outside the active area needs to be suppressed. Therefore, in this thesis, lateral charging effects in organic light-emitting diodes (OLEDs) are studied first. By comparing the results from differently structured devices, the presence of centimeter-scale lateral current flows in the n-doped and p-doped layers is shown, which results in undesirable capacitance increases and thus extra leakage currents. Such lateral charging can be controlled via structuring the doped layers, leading to extremely low steady-state leakage currents in the OLED (here 10-7 mA/cm2 at -1 V). It is shown that these lateral currents can be utilized to extract the conductivity as well as the activation energy of each doped layer when modeled with an RC circuit model. Secondly, pinMOS memory devices that are based on the diode with structured doped layers are investigated. The memory behavior, which is demonstrated as capacitance switching for electrical signals, and light emission for optical signals, can be tuned either by the applied voltage or ultraviolet light illumination, respectively. The working mechanism is explained by the existence of quasi steady-states as well as the width variation of space charge zones. The pinMOS memory shows excellent repeatability, an endurance of more than 104 write-read-erase-read cycles, and currently already over 24 h retention time. Furthermore, an early-stage investigation on emulating synaptic plasticity reveals the potential of pinMOS memory for applications in neuromorphic computing. Overall, the results indicate that pinMOS memory in principle is promising for a variety of future applications in both electronic and photonic circuits. A detailed understanding of this new concept of memory device, for which this thesis lays an important foundation, is necessary to proceed with further enhancements.:1 Introduction 1 2 Fundamentals of organic semiconductors 5 2.1 Electronic states of a molecule 5 2.1.1 Atomic orbitals and molecular orbitals 5 2.1.2 Solid states 9 2.1.3 Singlet and triplet states 12 2.2 Charge transport 13 2.2.1 Charge carrier mobility 13 2.2.2 Charge carrier transport 14 2.3 Charge injection 17 2.3.1 Current limitation 17 2.3.2 Charge injection mechanisms 20 2.4 Doping 22 3 Organic junctions and devices 25 3.1 Metal-semiconductor junction 25 3.1.1 Schottky junction 25 3.1.2 Surface states 27 3.2 Metal-oxide-semiconductor capacitor 29 3.3 Junctions and diodes 31 3.3.1 PN junction and diode 31 3.3.2 PIN junction and diode 32 4 Organic non-volatile memory devices 35 4.1 Basic concepts 35 4.2 Organic resistive memory devices 37 4.2.1 Device architecture and switching behavior 38 4.2.2 Working mechanisms 38 4.3 Organic transistor-based memory devices 41 4.3.1 Organic field-effect transistor and memory devices based thereon 41 4.3.2 Floating gate memory 43 4.3.3 Charge trapping memory 45 4.4 Organic ferroelectric memory devices 46 4.4.1 Ferroelectric capacitor memory 47 4.4.2 Ferroelectric transistor memory 48 4.4.3 Ferroelectric diode memory 49 5 Experimental methods 53 5.1 Device fabrication 53 5.2 Device characterization 55 5.3 Materials 57 6 Lateral current flow in semiconductor devices having crossbar electrodes 61 6.1 Introduction 61 6.2 Device architecture 62 6.3 Characteristics comparison between unstructured and structured devices 63 6.3.1 Charging measurement 63 6.3.2 Current-voltage characteristics 64 6.3.3 Capacitance-frequency characteristics 67 6.4 Influence of conductivity of doped layers 69 6.4.1 Dependence on doped layers thickness 69 6.4.2 Dependence on temperature 73 6.5 Lateral charging simulation 74 6.5.1 Analytical description 74 6.5.2 RC circuit simulation 76 6.5.3 Parameters for doped layers gained by simulation 79 6.6 Pseudo trap analysis 81 6.6.1 The pseudo trap density of states determination 81 6.6.2 The pseudo trap analysis under simulated identical conditions 84 6.7 Summary 85 7 The pinMOS memory: novel diode-capacitor memory with multiple-bit storage 87 7.1 Introduction 87 7.2 Device architecture 88 7.2.1 Dependence on layout and pixel 89 7.2.2 Fundamental memory behavior characterization 93 7.3 Working mechanism 96 7.3.1 Working mechanism of quasi-steady states 97 7.3.2 Working mechanism of dynamic states 101 7.4 Tunability of the memory effect 105 7.4.1 Operation parameters 106 7.4.2 Photoinduced tunability 108 7.4.3 Intrinsic layer thickness 110 7.5 Potential in neuromorphic computing application 111 7.5.1 Extracting capacitance at 0 V sequentially 112 7.5.2 Mimicking the long-term plasticity (LTP) behavior 113 7.6 Summary 114 8 Optoelectronic properties of pinMOS memory 117 8.1 Introduction 117 8.2 Measurement setup 117 8.3 pinMOS memory emission intensity 118 8.4 Pulse characteristics and device brightness 119 8.5 Conclusion 124 9 Conclusion 125 Bibliography 129 List of Figures 145 List of Tables 151 List of Abbreviations 153 Publications and Conference 157 Acknowledgment 159 / Es wird ein neuartiges, organisches kapazitives Speicherelement demonstriert, das p-i-n-Metalloxid-Halbleiter (pinMOS) Speicher genannt wird und eine Mehrfachbitspeicherung besitzt, die elektrisch und optisch programmiert und ausgelesen werden kann. Die auf einer Diode basierende Architektur vereinfacht den Herstellungsprozess sowie die weitere Optimierung und könnte sogar Inspiration für neue kapazitive Speichermedien sein. Darüber hinaus basiert dieses innovative pinMOS Speicherelement auf der lokalen Aufladung einer integrierten Kapazität und nicht auf einem zusätzlichem “Floating Gate”. Bevor das Speicherelement wie gewünscht funktioniert, muss der Leckstrom, der durch die laterale Aufladung der dotierten Schichten außerhalb des aktiven Bereichs verursacht wird, unterdrückt werden. Deshalb werden in dieser Arbeit zuerst die lateralen Aufladungseffekte in organischen Leuchtdioden (OLEDs) untersucht. Beim Vergleich verschiedener Device-Strukturen wird die Existenz von lateralen Stromflüssen im Zentimeterbereich in den n- und p-dotierten Schichten gezeigt, was zu einer unerwünschten erhöhten Kapazität und folglich einem höheren Leckstrom führt. Diese laterale Aufladung kann durch die Strukturierung der dotierten Schichten kontrolliert werden, was zu extrem geringen Gleichgewichtsleckströmen in den OLEDs (10-7 mA/cm2 bei -1 V) resultiert. Es wird auch gezeigt, dass die lateralen Ströme genutzt werden können um die spezifische Leitfähigkeit sowie die Aktivierungsenergie der einzelnen dotierten Schichten zu extrahieren, wenn diese mit einem RC-Modell modelliert werden. Im zweiten Teil werden pinMOS Speicherelemente, die auf der Diode mit strukturierten dotierten Schichten basieren, untersucht. Das Speicherverhalten, dass durch Kapazitätsschaltung für elektrische Signale und als Lichtemission für optische Signale gezeigt wird, kann entweder durch die angelegte Spannung, beziehungsweise durch die Belichtung mit ultraviolettem Licht eingestellt werden. Die Wirkungsweise wird durch die Existenz quasistatischer Gleichgewichte sowie durch die Größenänderung der Raumladungszonen erklärt. Der pinMOS Speicher zeigt eine hervorragende Wiederholbarkeit, eine Beständigkeit über mehr als 104 Schreiben-Lesen-Löschen-Lesen Zyklen und aktuell schon eine Retentionszeit von über 24 h. Weiterhin offenbaren erste Versuche in der Nachahmung von Neuronaler Plastizität das Potenzial von pinMOS Speichern für Anwendungen im “Neuromorphic Computing”. Insgesamt deuten die Ergebnisse an, dass pinMOS Speicher prinzipiell vielversprechend für eine Vielzahl von zukünftigen Anwendungen in elektronischen und photonischen Schaltkreisen ist. Ein tiefgreifendes Verständnis von diesem Konzept neuartiger Speicherelemente, für das diese Arbeit eine wichtige Grundlage bildet, ist notwendig, um weitere Verbesserungen zu entwickeln.:1 Introduction 1 2 Fundamentals of organic semiconductors 5 2.1 Electronic states of a molecule 5 2.1.1 Atomic orbitals and molecular orbitals 5 2.1.2 Solid states 9 2.1.3 Singlet and triplet states 12 2.2 Charge transport 13 2.2.1 Charge carrier mobility 13 2.2.2 Charge carrier transport 14 2.3 Charge injection 17 2.3.1 Current limitation 17 2.3.2 Charge injection mechanisms 20 2.4 Doping 22 3 Organic junctions and devices 25 3.1 Metal-semiconductor junction 25 3.1.1 Schottky junction 25 3.1.2 Surface states 27 3.2 Metal-oxide-semiconductor capacitor 29 3.3 Junctions and diodes 31 3.3.1 PN junction and diode 31 3.3.2 PIN junction and diode 32 4 Organic non-volatile memory devices 35 4.1 Basic concepts 35 4.2 Organic resistive memory devices 37 4.2.1 Device architecture and switching behavior 38 4.2.2 Working mechanisms 38 4.3 Organic transistor-based memory devices 41 4.3.1 Organic field-effect transistor and memory devices based thereon 41 4.3.2 Floating gate memory 43 4.3.3 Charge trapping memory 45 4.4 Organic ferroelectric memory devices 46 4.4.1 Ferroelectric capacitor memory 47 4.4.2 Ferroelectric transistor memory 48 4.4.3 Ferroelectric diode memory 49 5 Experimental methods 53 5.1 Device fabrication 53 5.2 Device characterization 55 5.3 Materials 57 6 Lateral current flow in semiconductor devices having crossbar electrodes 61 6.1 Introduction 61 6.2 Device architecture 62 6.3 Characteristics comparison between unstructured and structured devices 63 6.3.1 Charging measurement 63 6.3.2 Current-voltage characteristics 64 6.3.3 Capacitance-frequency characteristics 67 6.4 Influence of conductivity of doped layers 69 6.4.1 Dependence on doped layers thickness 69 6.4.2 Dependence on temperature 73 6.5 Lateral charging simulation 74 6.5.1 Analytical description 74 6.5.2 RC circuit simulation 76 6.5.3 Parameters for doped layers gained by simulation 79 6.6 Pseudo trap analysis 81 6.6.1 The pseudo trap density of states determination 81 6.6.2 The pseudo trap analysis under simulated identical conditions 84 6.7 Summary 85 7 The pinMOS memory: novel diode-capacitor memory with multiple-bit storage 87 7.1 Introduction 87 7.2 Device architecture 88 7.2.1 Dependence on layout and pixel 89 7.2.2 Fundamental memory behavior characterization 93 7.3 Working mechanism 96 7.3.1 Working mechanism of quasi-steady states 97 7.3.2 Working mechanism of dynamic states 101 7.4 Tunability of the memory effect 105 7.4.1 Operation parameters 106 7.4.2 Photoinduced tunability 108 7.4.3 Intrinsic layer thickness 110 7.5 Potential in neuromorphic computing application 111 7.5.1 Extracting capacitance at 0 V sequentially 112 7.5.2 Mimicking the long-term plasticity (LTP) behavior 113 7.6 Summary 114 8 Optoelectronic properties of pinMOS memory 117 8.1 Introduction 117 8.2 Measurement setup 117 8.3 pinMOS memory emission intensity 118 8.4 Pulse characteristics and device brightness 119 8.5 Conclusion 124 9 Conclusion 125 Bibliography 129 List of Figures 145 List of Tables 151 List of Abbreviations 153 Publications and Conference 157 Acknowledgment 159

No description available.

No description available.

Time-Resolved diffuse optics is a powerful and safe technique to quantify the optical properties (OP) for highly scattering media such as biological tissues. The OP values are correlated with the compositions of the measured objects, especially for the tissue chromophores such as hemoglobin. The OP are mainly the absorption and the reduced scattering coefficients that can be quantified for highly scattering media using Time-Resolved Diffuse Optical Spectroscopy (TR-DOS) systems. The OP can be retrieved using Time-Resolved Diffuse Optical Imaging (TR-DOI) systems to reconstruct the distribution of the OP in measured media. Therefore, TR-DOS and TR-DOI can be used for functional monitoring of brain and muscles, and to diagnose some diseases such as detection and localization for breast cancer and blood clot. In general, TR-DOI systems are non-invasive, reliable, and have a high temporal resolution. TR-DOI systems have been known for their complexity, bulkiness, and costly equipment such as light sources (picosecond pulsed laser) and detectors (single photon counters). Also, TR-DOI systems acquire a large amount of data and suffer from the computational cost of the image reconstruction process. These limitations hinder the usage of TR-DOI for widespread potential applications such as clinical measurements. The goals of this research project are to investigate approaches to eliminate two main limitations of TR-DOI systems. First, building TR-DOS systems using custom-designed free-running (FR) and time-gated (TG) SPAD detectors that are fabricated in low-cost standard CMOS technology instead of the costly photon counting and timing detectors. The FR-TR-DOS prototype has demonstrated comparable performance (for homogeneous objects measurements) with the reported TR-DOS prototypes that use commercial and expensive detectors. The TG-TR-DOS prototype has acquired raw data with a low level of noise and high dynamic range that enable this prototype to measure multilayered objects such as human heads. Second, building and evaluating TR-DOI prototype that uses a computationally efficient algorithm to reconstruct high quality 3D tomographic images by analyzing a small part of the acquired data. This work indicates the possibility to exploit the recent advances in the technologies of silicon detectors, and computation to build low-cost, compact, portable TR-DOI systems. These systems can expand the applications of TR-DOI and TR-DOS into several fields such as oncology, and neurology. / Thesis / Doctor of Philosophy (PhD)