Microelectronics has shaped the world beyond what was thought possible at the time of its advent. One area of current research in this field is on the solid-state Si:P-based quantum computer (QC). In this machine, each qubit requires an individually addressed fast control-pulse for non-adiabatic drive and measure operations. Additionally, it is increasingly becoming important to be able to interface nanoelectronics with complementary metal-oxide-semiconductor (CMOS) technology. In this work, I have designed and demonstrated full-custom mixed-mode and full-digital fast control-pulse generators fabricated in a silicon-on-sapphire (SOS) CMOS commercial foundry process ?? a radio-frequency (RF) CMOS technology. These circuits are, fundamentally, fast monostable multivibrators. Initially, after the design specifications were decided upon, I characterized NFET and PFET devices and a n+-diffusion resistor from 500 nm and 250 nm commercial SOS-CMOS processes. Measuring their conductance curves at 300 300 K, 4.2 2 K, and sub-K (30 30 mK base to 1000 1000 mK) showed that they function with desirable behaviour although exhibiting some deviations from their 300 300 K characteristics. The mixed-mode first generation control-pulse generator was demonstrated showing that it produced dwell-time adjustable pulses with 100 100 ps rise-times at 300 K, 4.2 2 K, and sub-K with a power dissipation of 12 12 uW at 100 100 MHz. The full-digital second generation control-pulse generator was demonstrated showing accurately adjustable dwell-times settable via a control-word streamed synchronously to a shift-register. The design was based on a ripple-counter with provisions for internal or external clocking. This research has demonstrated that SOS-CMOS technology is highly feasible for the fabrication of control microelectronics for a Si:P-based QC. I have demonstrated full-custom SOS-CMOS mixed-mode and full-digital control circuits at 300 300 K, 4.2 2 K, and sub-K which suitable for qubit control.

High power Gallium Nitride (GaN) based field effect transistors are used in many high power applications from RADARs to communications. These devices dissipate a large amount of power and sustain high electric fields during operation. High power dissipation occurs in the form of heat generation through Joule heating which also results in localized hot spot formation that induces thermal stresses. In addition, because GaN is strongly piezoelectric, high electric fields result in large inverse piezoelectric stresses. Combined with residual stresses due to growth conditions, these effects are believed to lead to device degradation and reliability issues. This work focuses on studying these effects in detail through modeling of Heterostructure Field Effect Transistors (HFETs) and metal oxide semiconductor hetero-structure field effect transistor (MOSHFETs) under various operational conditions. The goal is to develop a thorough understanding of device operation in order to better predict device failure and eventually aid in device design through modeling. The first portion of this work covers the development of a continuum scale model which couples temperature and thermal stress to find peak temperatures and stresses in the device. The second portion of this work focuses on development of a micro-scale model which captures phonon-interactions at the device scale and can resolve local perturbations in phonon population due to electron-phonon interactions combined with ballistic transport. This portion also includes development of phonon relaxation times for GaN. The model provides a framework to understand the ballistic diffusive phonon transport near the hotspot in GaN transistors which leads to thermally related degradation in these devices.

The scaling down of Complementary Metal Oxide Semiconductor (CMOS) transistors requires replacement of conventional silicon dioxide layer with higher dielectric constant (K) material for gate dielectric. In order to reduce the gate leakage current, and also to maximize gate capacitance, ‘high K’ gate oxide materials such as Al2O3, ZrO2, HfO2, Ta2O5, TiO2, Er2O3, La2O3, Pr2O3, Gd2O3, Y2O3, CeO2 etc. and some of their silicates such as ZrxSi1–xOy, HfxSi1–xOy, AlxZr1–xO2 etc. are under investigation. A systematic consideration of the required properties of gate dielectrics indicates that the key guidelines for selecting an alternate gate dielectric are (a) permittivity, band gap and band alignment to silicon, (b) thermodynamic stability, (c) film morphology, (d) interface quality, (e) compatibility with the materials/process used in CMOS devices and (f) reliability. In this study titanium dioxide (TiO2) is chosen as an alternate to silicon dioxide (SiO2). This thesis work is aimed at the study of the influence of process parameters like deposition rate, substrate temperature and annealing temperature on the electrical properties like maximum capacitance, dielectric constant, fixed charge, interface trapped charge and leakage current. For making this analysis we have used p–type single crystal silicon (<100>) as substrates and employed direct current (DC) reactive magnetron sputtering method with Titanium metal as target and Oxygen as reactive gas. TiO2 thin films have been deposited with an expected thickness of 50 nm with different deposition rates starting from 0.8 nm/minute to 2 nm/minute with different substrate temperatures (ambient temperature to 500ºC). Some of the samples are annealed at 750ºC in oxygen atmosphere for 30 minutes. SENTECH make Spectroscopic Ellipsometer is used for analyzing the optical properties such as thickness, refractive index etc. The thicknesses of all the samples that are extracted from the Ellipsometry are varying from 35 ± 2 nm to 50 ± 5 nm. Agilent make 4284A model L−C−R meter along with KarlSUSS wafer probe station is used for the C − V measurements and Keithley make 6487 model Pico ammeter/Voltage source is used for the I−V measurements. MOS capacitors have been fabricated with Aluminium as top electrode to perform the bi directional Capacitance−Voltage and also Current−Voltage analysis. The X–ray diffraction studies on the samples deposited at 500ºC showed that the films are amorphous. Dielectric constant (K) and effective substrate doping concentration (Na), flat band voltage (VFB), hysteresis, magnitude of fixed charges (Qf) as well as interface states density (Dit') and Equivalent Oxide Thickness (EOT) are obtained from the bi directional C−V analysis. A maximum dielectric constant of 18 is achieved with annealed samples. The best value of fixed charge density we have achieved is 1.2 x1011 per cm2 corresponding to the deposition rate of 2.0 nm/minute and with 500ºC substrate temperature. The ranges of Qf values that we have obtained are varying from 1.2x 1011 − 1.0 x1012 per cm2. It was also found that, the samples deposited at higher substrate temperatures show lower Qf values than the samples deposited at lower temperatures. The same trend is observed in case of interface states density also. The range of Dit' values we have obtained are in the range of 1.0 x 1012 cm–2eV–1 to 9x1012 cm–2eV–1. The best value of Dit' we have obtained is 1.0x1012 cm–2 eV–1 for the sample deposited at 0.8 nm/minute deposition rate and with substrate temperature of 400ºC. From the flat band voltage values of different set of samples, it was found that the flat band voltage is decreasing and in turn trying to approach the analytical value for the films deposited at higher deposition rates. The minimum EOT that we have achieved is 11 nm that corresponds to the film, which is annealed at 750ºC in oxygen atmosphere. From the I−V analysis it was found that the leakage current density is increasing with increase in substrate temperature and the same trend is observed with annealed films also. The minimum leakage current density achieved is 1.72x10–6 A/cm2 at a gate bias of 1V (corresponding field of 0.3 MV/cm). From the time dependent dielectric breakdown analysis it was found that the leakage current is exhibiting a constant value during the entire voltage stress time of 23 minutes. From the I–V characteristics it was found that the leakage current is following the Schottky emission characteristics at lower electric fields (< 1MV/cm) and is following the Fowler–Nordheim tunneling mechanism at higher electric fields. Since our aim is to study the electrical properties of titanium dioxide thin films for the application as high K gate dielectric in microelectronic applications more emphasis is given on the electrical properties. The maximum dielectric constant we have achieved is in the comparable range of the values for this parameter. The leakage current density values obtained are higher than the required for the microelectronic devices, where as the interface state density values and fixed charge density values are in the same range of values that are reported with this particular oxide and more care has to be taken to minimize these parameters. The EOT values we have achieved are also falling into the range of values that it actually takes as it was reported in the literature.

Undoped body multi gate (MG) Metal Oxide Semiconductor Field Effect Transistors (MOSFET) are appearing as replacements for single gate bulk MOSFET in forthcoming sub-45nm technology nodes. It is therefore extremely necessary to develop compact models for MG transistors in order to use them in nano-scale integrated circuit design and simulation. There is however a sharp distinction between the electrostatics of traditional bulk transistors and undoped body devices. In bulk transistor, where the substrate is sufficiently doped, the inversion charges are located close to the surface and hence the surface potential solely controls the electrostatic integrity of the device. However, in undoped body devices, gate electric field penetrates the body center, and inversion charge exists throughout the body. In contrast to the bulk transistors, depending on device geometry, the potential of the body center of undoped body devices could be higher than the surface in weak inversion regime and the current flows through the center-part of the device instead of surface. Several crucial parameters (e.g. Sub-threshold slope) sometimes become more dependable on the potential of body center rather than the surface. Hence the body-center potential should also be modeled correctly along with the surface-potential for accurate calculation of inversion charge, threshold voltage and other related parameters of undoped body multi-gate transistors. Although several potential models for MG transistors have been proposed to capture the short channel behavior in the subthreshold regime but most of them are based on the crucial approximation of coverting the 2D Poisson’s equation into Laplace equation. This approximation holds good only at surface but breaks down at body center and in the moderate inversion regime. As a result all the previous models fail to capture the potential of body center Correctly and remain valid only in weak-inversion regime. In this work we have developed semiclassical compact models for potential distribution for double gate (DG) and cylindrical Gate-All-Around (GAA) transistors. The models are based on the analytical solution of 2D Poisson’s equation in the channel region and valid for both: a) weak and strong inversion regimes, b) long channel and short channel transistors, and, c) body surface and center. Using the proposed model, for the first time, it is demonstrated that the body potential versus gate voltage characteristics for the devices having equal channel lengths but different body thicknesses pass through a single common point (termed as crossover point). Using the concept of “crossover point” the effect of body thickness on the threshold voltage of undoped body multi-gate transistors is explained. Based on the proposed body potential model, a new compact model for the subthreshold swing is formulated. Some other parameters e.g. inversion charge, threshold voltage roll-off etc are also studied to demonstrate the impact of body center potential on the electrostatics of multi gate transistor. All the models are validated against professional numerical device simulator.

Cette étude porte sur l'intégration hybride de transistors à un électron (single-electron transistor, SET) dans un noeud technologique CMOS. Les SETs présentent de forts potentiels, en particulier en termes d'économies d'énergies, mais ne peuvent complètement remplacer le CMOS dans les circuits électriques. Cependant, la combinaison des composants SETs et MOS permet de pallier à ce problème, ouvrant la voie à des circuits à très faible puissance dissipée, et à haute densité d'intégration. Cette thèse se propose d'employer pour la réalisation de SETs dans le back-end-of-line (BEOL), c'est-à-dire dans l'oxyde encapsulant les CMOS, le procédé de fabrication nanodamascène, mis au point par C. Dubuc.

La croissance continue et rapide du trafic de données dans les infrastructures de télécommunications, impose des niveaux de débit de transmission ainsi que de puissance de traitement de l'information, que les capacités intrinsèques des systèmes et microcircuits électroniques ne seront plus en mesure d'assurer à brève échéance : le développement de nouveaux scenarii technologiques s'avère indispensable pour répondre à la demande de bande passante imposée notamment par la révolution de l'internet, tout en préservant une consommation énergétique raisonnable. Dans ce contexte, l'intégration hétérogène fonctionnelle sur silicium de dispositifs photoniques à émission par la surface de type VCSEL utilisant des miroirs large-bandes ultra-compacts à cristaux photoniques constitue une stratégie prometteuse pour surmonter l'impasse technologique actuelle, tout en ouvrant la voie à un développement rapide d'architectures et de systèmes de communications innovants dans le cadre du mariage entre photonique et micro-nano-électronique.

Microelectronics has shaped the world beyond what was thought possible at the time of its advent. One area of current research in this field is on the solid-state Si:P-based quantum computer (QC). In this machine, each qubit requires an individually addressed fast control-pulse for non-adiabatic drive and measure operations. Additionally, it is increasingly becoming important to be able to interface nanoelectronics with complementary metal-oxide-semiconductor (CMOS) technology. In this work, I have designed and demonstrated full-custom mixed-mode and full-digital fast control-pulse generators fabricated in a silicon-on-sapphire (SOS) CMOS commercial foundry process ?? a radio-frequency (RF) CMOS technology. These circuits are, fundamentally, fast monostable multivibrators. Initially, after the design specifications were decided upon, I characterized NFET and PFET devices and a n+-diffusion resistor from 500 nm and 250 nm commercial SOS-CMOS processes. Measuring their conductance curves at 300 300 K, 4.2 2 K, and sub-K (30 30 mK base to 1000 1000 mK) showed that they function with desirable behaviour although exhibiting some deviations from their 300 300 K characteristics. The mixed-mode first generation control-pulse generator was demonstrated showing that it produced dwell-time adjustable pulses with 100 100 ps rise-times at 300 K, 4.2 2 K, and sub-K with a power dissipation of 12 12 uW at 100 100 MHz. The full-digital second generation control-pulse generator was demonstrated showing accurately adjustable dwell-times settable via a control-word streamed synchronously to a shift-register. The design was based on a ripple-counter with provisions for internal or external clocking. This research has demonstrated that SOS-CMOS technology is highly feasible for the fabrication of control microelectronics for a Si:P-based QC. I have demonstrated full-custom SOS-CMOS mixed-mode and full-digital control circuits at 300 300 K, 4.2 2 K, and sub-K which suitable for qubit control.

Alors que la demande en électronique haute puissance et haute fréquence ne fait qu’augmenter, les semi-conducteurs classiques montrent leurs limites. Des approches basées soit sur des nouvelles architectures ou sur des matériaux à large bande interdite devraient permettre de les dépasser. Le diamant, avec ses propriétés exceptionnelles, semble être le semi-conducteur ultime pour répondre à ces attentes. Néanmoins, il souffre aussi de certaines limitations, en particulier d’une forte énergie d’ionisation du dopant de type p (bore) qui se traduit par une faible concentration de porteurs libres à la température ambiante. Des solutions innovantes s'appuyant sur un gaz 2D et /ou l’effet de champ ont été imaginées pour résoudre ce problème. Ce travail est axé sur deux de ces solutions : i) le diamant delta dopé au bore qui consiste en une couche fortement dopée entre deux couches intrinsèques, afin d’obtenir une conduction combinant une grande mobilité avec une grande concentration de porteurs et ii) le transistor à effet de champ métal oxide semiconducteur( MOSFET ), où l’état « on » et l’état « off » du canal sont obtenus grâce au contrôle électrostatique de la courbure de bandes à l' interface de diamant/oxyde. Pour ces deux structures, beaucoup de défis technologiques doivent être surmontés avant de pouvoir fabriquer un transistor. La dépendance en température de la densité surfacique de trous et de la mobilité de plusieurs couche de diamant delta dopées au bore a été étudiée expérimentalement et théoriquement sur une large gamme de température (6 K <T < 500 K). Deux types de conduction ont été détectés: métallique et non métallique. Une mobilité constante comprise entre 2 et 4 cm2/Vs a été mesurée pour toutes les couches delta métalliques quelle que soient leurs épaisseurs ou le substrat utilisé pour la croissance. Cette valeur particulière est discutée en comparaison à d'autres valeurs expérimentales reportées dans la littérature et aussi de calculs théoriques. Une conduction parallèle à travers les régions faiblement dopées qui encapsule la couche delta, a également été mise en évidence dans certains échantillons. Une très faible mobilité a été mesurée pour les couches delta non métalliques et a été attribuée à un mécanisme de conduction par saut. Des structures métal oxyde semi-conducteur utilisant de l'oxyde d'aluminium comme isolant et du diamant monocristallin (100) de type p en tant que semi-conducteur ont été fabriquées et étudiées par des mesures capacité tension C(V) et courant tension I(V). L'oxyde d'aluminium a été déposé en utilisant un dépôt par couche atomique (Atomic Layer Deposition : ALD) à basse température sur une surface oxygénée de diamant. Les mesures C(V) démontrent que les régimes d'accumulation , de déplétion et de déplétion profonde peuvent être contrôlés grâce à la tension de polarisation appliquée sur la grille. Un diagramme de bande est proposée et discutée pour expliquer le courant de fuite étonnamment élevé circulant en régime d’accumulation. Aucune amélioration significative de la mobilité n’a été observée dans les structures delta, même pour les plus fines d’entre elles (2 nm). Cependant, la démonstration du contrôle de l’état du canal de la structure MOS ouvre la voie pour la fabrication d’un MOSFET en diamant, même si un certain nombre de verrous technologiques subsistent. / As the demand in high power and high frequency electronics is still growing, standard semiconductors show their limits. Approaches based either on new archi- tectures or wide band gap materials should allow to overcome these limits. Diamond, with its outstanding properties, seems to be the ultimate semiconductor. Neverthe- less, it also suffers from limitations, especially the high ionization energy of the boron p-type dopant that results in a low carrier concentration at room temperature. In- novative solutions relying on 2D gas or/and field effect ionization has been imagined to overcome this problem. This work is focused on two of these solutions: i) boron delta-doping consisting in highly doped layer between two intrinsic layers, resulting in a conduction combining a high mobility with a large carrier concentration and ii) metal-oxide-semiconductor field effect transistor (MOSFET) where the conducting or insulating behavior of the channel is based on the electrostatic control of the band curvature at the oxide/semiconducting diamond interface. For both structures, a lot of technological challenges need to be surmounted before fabricating the related transistor. On one hand, the temperature dependence of the hole sheet density and mobility of several nano-metric scaled delta boron doped has been investigated experimentally and theoretically over a large temperature range (6 K <T< 500 K). Two types of conduction behaviors were detected : metallic and non metallic. A constant mobility between 2 and 4 cm2/V.s was found for all the metallic degenerated delta layers whatever its thickness or the substrate used for the growth. This particular value is discussed in comparison of other experimental values reported in literature and theoretical calculations. A parallel conduction through the low doped regions, in which the delta is embedded, has also been brought to light in certain cases. A very low mobility was measured for non metallic conduction delta layers and has been attributed to an hopping conduction mechanism which is discussed. On the other hand, metal-oxide-semiconductor structures with aluminum oxide as insulator and p−type (100) mono-crystalline diamond as semiconductor have been fabricated and investigated by capacitance versus voltage C(V) and current versus voltage I(V) measurements. The aluminum oxide dielectric was deposited using low temperature atomic layer deposition on an oxygenated diamond surface. The C(V) measurements demonstrate that accumulation, depletion and deep depletion regimes can be controlled by the bias voltage. A band diagram is proposed and discussed to explain the surprisingly high leakage current flowing in accumulation regimes. To sum up, no significant improvement of mobility has been observed in delta structures even for the thinnest one (2 nm). However, the MOS channel control demonstration opens the route for diamond MOSFET even if technological chal- lenges remain.

Les capteurs d'images en technologie CMOS se sont fortement développés grâce à l'avènement du multimédia à la fin des années 1990. Leurs caractéristiques optiques, ainsi que leur coût, les ont, en effet, destinés au marché “grand public”. Ces capteurs intègrent des fonctions analogiques et/ou numériques qui permettent la mise en œuvre de traitements au sein du pixel, autour du pixel, pour un groupe de pixels, en bout de colonne. Jusqu’à présent, les traitements intégrés dans le capteur sont de nature linéaire et consistent en général à réaliser des convolutions. Si ces traitements sont incontournables dans une chaîne de vision, ils sont toutefois limités et ne permettent pas à eux seuls de réaliser une application complexe du type reconnaissance d’objets dans une scène naturelle. Pour cela, des traitements non-linéaires associés à des classifieurs haut-niveau permettent de compléter les traitements linéaires en vue de répondre aux contraintes d’une application complexe. Dans ce contexte, nous montrons que les approches “mathématique-inspirées” et “neuro-inspirées” nécessitent toutes deux l'emploi de traitements non-linéaires basés sur les opérateurs "min" et "max". De ce fait, nous proposons un modèle architectural permettant d'intégrer dans le plan focal les traitements non-linéaires. Ce modèle est basé sur une topologie de PEs 4-connexes et présente un double avantage par rapport aux solutions classiques. D'une part pour ce qui concerne l'augmentation de la vitesse d'exécution des traitements non linéaires mais aussi pour les aspects de réduction de la consommation qui sont liés aux nombres d'accès aux mémoires externes dans le cas des systèmes numériques. Le circuit NLIP (Non Linear Image processing) qui a été conçu durant cette thèse comporte 64 x 64 pixels associés à 64 x 64 processeurs analogiques élémentaires. Chaque pixel a une taille de 40 m de côté et présente un facteur de remplissage de 18% ce qui garantit une bonne sensibilité. La fabrication du circuit a été réalisée en technologie CMOS 0.35 m et les tests fonctionnels réalisés ont permis de valider le modèle de rétine proposé / CMOS images sensors have grown significantly since the late 1990s in connection with the huge developments of multimedia applications. Their optical characteristics, as well as their cost, have, in fact targeted for the consumer market. These sensors include analog and / or digital functions that allow the implementation of treatments within the pixel around the pixel, for a group of pixels in the end of column. Until now, processing inside the sensor.Until now, image processing inside the CMOS sensor are linear and based on convolutions. If these treatments are essential in a chain of vision, they are however limited and do not allow themselves to make a complex application like objects recognition in a natural scene. For this, non-linear associated with high-level classifiers can complete linear processing to meet the demands of a complex application. In this context, we show that “mathematically inspired” and “neuron-inspired” approaches both require the use of non-linear operators based on the “min” and “max” treatments. Therefore, we propose an architectural model for integrating non-linear processes in the focal plane. This model is based on a topology of “4-connected” PE and has two advantages over conventional solutions. Firstly with regard to increasing the speed of execution of nonlinear treatments but also aspects of reduced consumption are related to access to external memory in the case of digital based systems. The NLIP circuit (Non Linear Image Processing), which was designed during this thesis has 64 x 64 pixels associated with 64 x 64 elementary analog processors. Each pixel has a size of 40 m from the side and has a fill factor of 18%, which ensures a good sensitivity. The fabrication of the circuit was carried out in CMOS technology 0.35 m and functional tests were used to validate the proposed model retina

For the past 40 years, relentless focus on Moore’s Law transistor scaling has provided ever-increasing transistor performance and density. In order to continue the technology scaling beyond 22nm node, it is clear that conventional bulk-MOSFET needs to be replaced by new device architectures, most promising being the Multiple-Gate MOSFETs (MuGFET). Intel in mid 2011 announced the use of bulk Tri-Gate FinFETs in 22nm high volume logic process for its next-gen IvyBridge Microprocessor. It is expected that soon other semiconductor companies will also adopt the MuGFET devices. As like bulk-MOSFET, an accurate and physical compact model is important for MuGFET based circuit design. Compact modeling effort for MuGFET started in late nineties with planar double gate MOSFET(DGFET),as it is the simplest structure that one can conceive for MuGFET devices. The models so far proposed for DG MOSFETs are applicable for common gate symmetric DG (SDG) MOSFETs where both the gates have equal oxide thicknesses. However, for practical devices at nanoscale regime, there will always be some amount of asymmetry between the gate oxide thicknesses due to process variations and uncertainties, which can affect device performance significantly. At the same time, Independently controlled DG(IDG) MOSFETs have gained tremendous attention owing to its ability to modulate threshold voltage and transconductance dynamically. Due to the asymmetric nature of the electrostatic, developing efficient compact models for asymmetric/independent DG MOSFET is a daunting task. In this thesis effort has been put to provide some solutions to this challenge. We propose simple surface-potential based compact terminal charge models, applicable for Asymmetric Double gate MOSFETs (ADG) in two configurations1) Common-gate 2) Independent-gate. The charge model proposed for the common-gate ADG (CDG) MOSFET is seamless between the symmetric and asymmetric devices and utilizes the unique so-far-unexplored quasi-linear relationship between the surface potentials along the channel. In this model, the terminal charges could be computed by basic arithmetic operations from the surface potentials and applied biases, and can be easily implemented in any circuit simulator and extendable to short-channel devices. The charge model proposed for independent ADG(IDG)MOSFET is based on a novel piecewise linearization technique of surface potential along the channel. We show that the conventional “charge linearization techniques that have been used over the years in advanced compact models for bulk and double-gate(DG) MOSFETs are accurate only when the channel is fully hyperbolic in nature or the effective gate voltages are same. For other bias conditions, it leads to significant error in terminal charge computation. We demonstrate that the amount of nonlinearity that prevails between the surface potentials along the channel for a particular bias condition actually dictates if the conventional charge linearization technique could be applied or not. We propose a piecewise linearization technique that segments the channel into multiple sections where in each section, the assumption of quasi-linear relationship between the surface potentials remains valid. The cumulative sum of the terminal charges obtained for each of these channel sections yield terminal charges of the IDG device. We next present our work on modeling the non-ideal scenarios like presence of body doping in CDG devices and the non-planar devices like Tri-gate FinFETs. For a fully depleted channel, a simple technique to include body doping term in our charge model for CDG devices, using a perturbation on the effective gate voltage and correction to the coupling factor, is proposed. We present our study on the possibility of mapping a non-planar Tri-gate FinFET onto a planar DG model. In this framework, we demonstrate that, except for the case of large or tall devices, the generic mapping parameters become bias-dependent and an accurate bias-independent model valid for geometries is not possible. An efficient and robust “Root Bracketing Method” based algorithm for computation of surface potential in IDG MOSFET, where the conventional Newton-Raphson based techniques are inefficient due to the presence of singularity and discontinuity in input voltage equations, is presented. In case of small asymmetry for a CDG devices, a simple physics based perturbation technique to compute the surface potential with computational complexity of the same order of an SDG device is presented next. All the models proposed show excellent agreement with numerical and Technology Computer-Aided Design(TCAD) simulations for all wide range of bias conditions and geometries. The models are implemented in a professional circuit simulator through Verilog-A, and simulation examples for different circuits verify good model convergence.