Thesis (Ph. D.)--University of Texas at Austin, 2007. / Vita. Includes bibliographical references.

WEb Services constituem uma tecnologia emergente utilizada para disponibilização de serviços na Web. Devido aos complexos processos de negócio existentes, esses serviços são combinados para que operem seguindo um fluxo de trabalho. Esse processo é chamado de composição de Web Services. Como no processo de desenvolvimento de um software tradicional, a atividade de teste é fundamental no processo de desenvolvimento da composição de Web Services. Neste trabalho é proposta uma estratégia de teste para a composição de Web Services, em que especificações de composições são transformadas para um modelo de teste de programas paralelos baseados em passagem de mensagens. É proposto o conceito de grupos de elementos requeridos para melhorar a cobertura dos critérios. Uma ferramenta de apoio à estratégia de teste foi desenvolvida. Alguns estudos experimentais para avaliar a aplicabilidade da estratégia proposta também são apresentados. Além disso, é proposto um método que utiliza redes de Petri para eliminar sincronizações não-executáveis no envio e recebimento de mensagens / WEb Services constitute an emerging technology for deploying services in the Web. Due to the complex business processes, these services are combined to operate, following a workflow. This process is named Web Services Composition. As in the development process of a traditional software, the testing activity is fundamental in the development process of Web Services Composition. This work proposes a test strategy for Web Services Composition, in that composition specifications are transformed into a test model of message-passing parallel programs. The concept of required elements groups is proposed to improve the criteria coverage. A tool that supports the test strategy was developed. Some experimental studies for evaluating the applicability of proposed strategy are also presented. Furthermore, it presents a method that uses Petri Nets to eliminate non-executable synchronizations in the sending and receiving of messages

This master thesis deals with the design and implementation of dynamic analyzer of parametrized contracts . In the first part of the thesis , the problematics of testing of parallel programs are discussed and issues when dealing with parallelism are described . Further , methods how to reveal concurrency bugs via dynamic analysis are described , in particular FastTrack and Contract validator. The second part of the thesis proposes an extension for RoadRunner framework and SearchBestie platform for contract validator with parameters.

Trends in computer engineering place renewed emphasis on increasing parallelism and heterogeneity. The rise of parallelism adds an additional dimension to the challenge of portability, as different processors support different notions of parallelism, whether vector parallelism executing in a few threads on multicore CPUs or large-scale thread hierarchies on GPUs. Thus, software experiences obstacles to portability and efficient execution beyond differences in instruction sets; rather, the underlying execution models of radically different architectures may not be compatible. Dynamic compilation applied to data-parallel heterogeneous architectures presents an abstraction layer decoupling program representations from optimized binaries, thus enabling portability without encumbering performance. This dissertation proposes several techniques that extend dynamic compilation to data-parallel execution models. These contributions include: - characterization of data-parallel workloads - machine-independent application metrics - framework for performance modeling and prediction - execution model translation for vector processors - region-based compilation and scheduling We evaluate these claims via the development of a novel dynamic compilation framework, GPU Ocelot, with which we execute real-world workloads from GPU computing. This enables the execution of GPU computing workloads to run efficiently on multicore CPUs, GPUs, and a functional simulator. We show data-parallel workloads exhibit performance scaling, take advantage of vector instruction set extensions, and effectively exploit data locality via scheduling which attempts to maximize control locality.

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Dû à la complexité des algorithmes de traitement d’images récents et dans le but d'accélérer la procédure de la conception des MPSoCs, méthodologies de prototypage rapide sont nécessaires pour fournir différents choix pour le programmeur de générer des programmes parallèles efficaces. Ce manuscrit présente les travaux menés pour proposer une méthodologie de prototypage rapide permettant la conception des architectures MPSOC ainsi que la génération automatique de système matériel / logiciel dédié un circuit reprogrammable (FPGA). Pour faciliter la programmation parallèle, l'approche MPSoC proposée est basée sur l’utilisation de Framework « CubeGen » qui permet la génération des différentes solutions envisageables pour réaliser des prototypes dans le domaine du traitement d’image. Ce document décrit une méthode basée sur le concept des squelettes générés en fonction des caractéristiques d'application afin d'exploiter tous les types de parallélisme des algorithmes réels. Un ensemble d’expérimentations utilisant des algorithmes courants permet d’évaluer les performances du flot de conception proposé équivalente à une architecture basé des processeurs hardcore et les solutions traditionnels basé sur cibles ASIC. / Due to the complexity of image processing algorithms and the restrictions imposed by MPSoC designs to reach their full potentials, automatic design methodologies are needed to provide guidance for the programmer to generate efficient parallel programs. In this dissertation, we present a MPSoC-based design methodology solution supporting automatic design space exploration, automatic performance evaluation, as well as automatic hardware/software system generation. To facilitate the parallel programming, the presented MPSoC approach is based on a CubeGen framework that permits the expression of different scenarios for architecture and algorithmic design exploring to reach the desired level of performance, resulting in short time development. The generated design could be implemented in a FPGA technology with an expected improvement in application performance and power consumption. Starting from the application, we have evolved our effective methodology to provide several parameterizable algorithmic skeletons in the face of varying application characteristics to exploit all types of parallelism of the real algorithms. Implementing such applications on our parallel embedded system shows that our advanced methods achieve increased efficiency with respect to the computational and communication requirements. The experimental results demonstrate that the designed multiprocessing architecture can be programmed efficiently and also can have an equivalent performance to a more powerful designs based hard-core processors and better than traditional ASIC solutions which are too slow and too expensive.

Faced with complex problems that involve scientific applications, researchers are looking for new ways to optimize the processing of these, using new concepts and paradigms for parallel and distributed programming. An emerging alternative to this scenario is the use of GPUs (Graphics Processing Unit) due to its high computational power. However, along with the benefits from the use of such techniques has been diverse and complex issues related to teaching and learning from them. Thus, researchers began to devote efforts to obtain better results in teaching these areas. So, the environments to support teaching of parallel programming have emerged. Such environments provide a set of tools for the development and testing of applications, thereby improving the educational experience. However, the current researches focuses on environments supporting teaching parallel programming for CPU architectures, not exist environments to teaching support teaching oriented architectures GPU. The absence of such environments has a negative impact, proven in various scientific researches. In this context, this work presents an environment for supporting parallel programming in GPU, called GPUHelp. The GPUHelp provides to users a complete solution for developing and codes test for GPU architectures, the CUDA and OpenCL, even for those users that do not have graphics cards on their computers, which was not possible before, given the need to graphics card compatible with such architectures. Evaluations have shown that GPUHelp is a feasible solution with different applicability scenarios in education and training on parallel programming GPU. / Frente às complexas dificuldades que envolvem as aplicações científicas, pesquisadores buscam novos meios de otimizar o processamento destas, utilizando-se de novos conceitos e paradigmas em programação paralela e distribuída. Uma alternativa emergente a este cenário, é a utilização de GPUs (Graphics Processing Unit) devido a seu alto poder computacional. Contudo, juntamente com os benefícios advindos da utilização de tais técnicas, tem-se diversas e complexas questões relacionadas ao ensino e aprendizado das mesmas. Desse modo, pesquisadores passaram a dedicar esforços para obter um melhor resultado no ensino destas áreas. Assim, surgiram os ambientes de apoio ao ensino de programação paralela. Tais ambientes provêem um conjunto de ferramentas para o desenvolvimento e teste de aplicações, aprimorando assim a experiência educacional. Entretanto, as pesquisas atuais focam em ambientes de apoio a programação paralela para arquiteturas de CPU, não existindo assim, ambientes de apoio voltados as arquiteturas de GPU. A inexistência de tais ambientes tem impacto negativo, durante o processo de aprendizado, comprovado em diferentes pesquisas científicas. Neste contexto, este trabalho apresenta um ambiente de apoio a programação paralela em GPU, intitulado GPUHelp. O GPUHelp proporciona aos usuários uma solução completa para o desenvolvimento e teste de códigos para arquiteturas de GPU, o CUDA e OpenCL, mesmo para aqueles usuários que não possuem placas gráficas em seus computadores, o que não era possível até então, visto a necessidade de uma placa gráfica compatível com tais arquiteturas. As avaliações realizadas demonstraram que o GPUHelp é uma solução viável com aplicabilidades distintas nos cenários de ensino e treinamento de programação paralela em GPU.

High power dissipation and on-chip temperature limit performance and affect reliability in modern microprocessors. For servers and data centers, they determine the cooling cost, whereas for handheld and mobile systems, they limit the continuous usage of these systems. For mobile systems, energy consumption affects the battery life. It can not be ignored for desktop and server systems as well, as the contribution of energy continues to go up in organizations’ budgets, influencing strategic decisions, and its implications on the environment are getting appreciated. Intelligent trade-offs involving these quantities are critical to meet the performance demands of many modern applications. Dynamic Voltage and Frequency Scaling (DVFS) offers a huge potential for designing trade-offs involving energy, power, temperature and performance of computing systems. In our work, we propose and evaluate DVFS schemes that aim at minimizing energy consumption while meeting a performance constraint, for both sequential and parallel applications. We propose a Petri net based program performance model, parameterized by application properties, microarchitectural settings and system resource configuration, and use this model to find energy efficient DVFS settings. We first propose a DVFS scheme using this model for sequential programs running on single core multiple clock domain (MCD) processors, and evaluate this on a MCD processor simulator. We then extend this scheme for data parallel (Single Program Multiple Data style) applications, and then generalize it for stream applications as well, and evaluate these two schemes on a full system CMP simulator. Our experimental evaluation shows that the proposed schemes achieve significant energy savings for a small performance degradation.