We present an energy conscious location-aware computing system that provides relevant information about the users current location. The location-aware computing system is initialized with a map (in the form of a graph) as well as audio files associated with several locations in the map. The system consists of: GPS receiver module, Serial port, Compact flash module, Stereo codec, Power manager module implementing three sub modules namely, GPS-to-real-world position conversion module (implements algorithm to convert GPS co-ordinates to graph nodes), Nearest-location-search module (implements modified Dijkstras algorithm), and User speed estimation module. The location-aware computing system receives the GPS co-ordinates for the current location from GPS receiver through the serial port. The system converts the GPS co-ordinates to map co-ordinates stored in the Compact Flash card. If the current location matches the landmarks of interest in the site, then the relevant audio details of the current location is played out to the user. The power manager sets the GPS co-ordinates update frequency to avoid keeping the system component on throughout the entire course of travel. The power manager implements an algorithm that works as follows: at any given location, the algorithm predicts the user speed by exponential average approach. The attenuation factor of this approach can be varied to account for the user speed history. The estimated speed is used to predict the time (say T) required to reach the next nearest location determined by Nearest-location-search module implementing modified Dijkstras algorithm. The subsystems are shut-down or switched to low-power mode for time T. After time T, the system will wake up and re-execute the algorithm.

Mobile terminals allow users to access service while on the move. This unique feature has driven the rapid growth in the mobile network industry, changing it from a new technology into a massive industry in less than two decades. In this thesis, an in-depth study of the handover effects of mobile WiMAX networks is carried out. The mobile WiMAX technology is first presented as literature study and then the technologies of handovers for previous generations are introduced in detail. Further, the hard handover of the mobile WiMAX is simulated by Network Simulator-2 (NS-2). In addition, the "ping-pang" effect of handover was investigated and the call blocking and dropping probabilities are implemented using MATLAB. The goal is to find out which parameters have the significant impact on the handover performance. The results showed that the threshold and hysteresis margin of the handover should be selected by considering the tradeoff between the "ping-pang" effect and the extra interference causing to neighboring cells due to the poor quality link. The handover latency of mobile WiMAX is below 50 ms with the traveling speed of mobile station up to 20 m/s.

The complexity of distributed computing systems has raised two unprecedented challenges for system management. First, various customers need to be assured by meeting their required service-level agreements such as response time and throughput. Second, system power consumption must be controlled in order to avoid system failures caused by power capacity overload or system overheating due to increasingly high server density. However, most existing work, unfortunately, either relies on open-loop estimations based on off-line profiled system models, or evolves in a more ad hoc fashion, which requires exhaustive iterations of tuning and testing, or oversimplifies the problem by ignoring the coupling between different system characteristics (ie, response time and throughput, power consumption of different servers). As a result, the majority of previous work lacks rigorous guarantees on the performance and power consumption for computing systems, and may result in degraded overall system performance. In this thesis, we extensively study adaptive performance/power management and power-efficient performance management for distributed computing systems such as information dissemination systems, power grid management systems, and data centers, by proposing Multiple-Input-Multiple-Output (MIMO) control and hierarchical designs based on feedback control theory. For adaptive performance management, we design an integrated solution that controls both the average response time and CPU utilization in information dissemination systems to achieve bounded response time for high-priority information and maximized system throughput in an example information dissemination system. In addition, we design a hierarchical control solution to guarantee the deadlines of real-time tasks in power grid computing by grouping them based on their characteristics, respectively. For adaptive power management, we design MIMO optimal control solutions for power control at the cluster and server level and a hierarchical solution for large-scale data centers. Our MIMO control design can capture the coupling among different system characteristics, while our hierarchical design can coordinate controllers at different levels. For power-efficient performance management, we discuss a two-layer coordinated management solution for virtualized data centers. Experimental results in both physical testbeds and simulations demonstrate that all the solutions outperform state-of-the-art management schemes by significantly improving overall system performance.

Recent increase in performance of High Performance Computing (HPC) systems has been followed by even higher increase in power consumption. Power draw of modern supercomputers leads to very high operating costs and reliability concerns. Furthermore, it has negative consequences on the environment. Accordingly, over the last decade there have been many works dealing with power/energy management in HPC systems. Since CPUs accounts for a high portion of the total system power consumption, our work aims at CPU power reduction. Dynamic Voltage Frequency Scaling (DVFS) is a widely used technique for CPU power management. Running an application at lower frequency/voltage reduces its power consumption. However, frequency scaling should be used carefully since it has negative effects on the application performance. We argue that the job scheduler level presents a good place for power management in an HPC center having in mind that a parallel job scheduler has a global overview of the entire system. In this thesis we propose power-aware parallel job scheduling policies where the scheduler determines the job CPU frequency, besides the job execution order. Based on the goal, the proposed policies can be classified into two groups: energy saving and power budgeting policies. The energy saving policies aim to reduce CPU energy consumption with a minimal job performance penalty. The first of the energy saving policies assigns the job frequency based on system utilization while the other makes job performance predictions. While for less loaded workloads these policies achieve energy savings, highly loaded workloads suffer from a substantial performance degradation because of higher job wait times due to an increase in load caused by longer job run times. Our results show higher potential of the DVFS technique when applied for power budgeting. The second group of policies are policies for power constrained systems. In contrast to the systems without a power limitation, in the case of a given power budget the DVFS technique even improves overall job performance reducing the average job wait time. This comes from a lower job power consumption that allows more jobs to run simultaneously. The first proposed policy from this group assigns CPU frequency using the job predicted performance and current power draw of already running jobs. The other power budgeting policy is based on an optimization problem which solution determines the job execution order, as well as power distribution among jobs selected for execution. This policy fully exploits available power and leads to further performance improvements. The last contribution of the thesis is an analysis of the DVFS technique potential for energyperformance trade-off in current and future HPC systems. Ongoing changes in technology decrease the DVFS applicability for energy savings but the technique still reduces power consumption making it useful for power constrained systems. In order to analyze DVFS potential, a model of frequency scaling impact on MPI application execution time has been proposed and validated against measurements on a large-scale system. This parametric analysis showed for which application/platform characteristic, frequency scaling leads to energy savings. / El aumento de rendimiento que han experimentado los sistemas de altas prestaciones ha venido acompañado de un aumento aún mayor en el consumo de energía. El consumo de los supercomputadores actuales implica unos costes muy altos de funcionamiento. Estos costes no tienen simplemente implicaciones a nivel económico sino también implicaciones en el medio ambiente. Dado la importancia del problema, en los últimos tiempos se han realizado importantes esfuerzos de investigación para atacar el problema de la gestión eficiente de la energía que consumen los sistemas de supercomputación. Dado que la CPU supone un alto porcentaje del consumo total de un sistema, nuestro trabajo se centra en la reducción y gestión eficiente de la energía consumida por la CPU. En concreto, esta tesis se centra en la viabilidad de realizar esta gestión mediante la técnica de Dynamic Voltage Frequency Scalingi (DVFS), una técnica ampliamente utilizada con el objetivo de reducir el consumo energético de la CPU. Sin embargo, esta técnica puede implicar una reducción en el rendimiento de las aplicaciones que se ejecutan, ya que implica una reducción de la frecuencia. Si tenemos en cuenta que el contexto de esta tesis son sistemas de alta prestaciones, minimizar el impacto en la pérdida de rendimiento será uno de nuestros objetivos. Sin embargo, en nuestro contexto, el rendimiento de un trabajo viene determinado por dos factores, tiempo de ejecución y tiempo de espera, por lo que habrá que considerar los dos componentes. Los sistemas de supercomputación suelen estar gestionados por sistemas de colas. Los trabajos, dependiendo de la política que se aplique y el estado del sistema, deberán esperar más o menos tiempo antes de ser ejecutado. Dado las características del sistema objetivo de esta tesis, nosotros consideramos que el Planificador de trabajo (o Job Scheduler), es el mejor componente del sistema para incluir la gestión de la energía ya que es el único punto donde se tiene una visión global de todo el sistema. En este trabajo de tesis proponemos un conjunto de políticas de planificación que considerarán el consumo energético como un recurso más. Estas políticas decidirán que trabajo ejecutar, el número de cpus asignadas y la lista de cpus (y nodos) sino también la frecuencia a la que estas cpus se ejecutarán. Estas políticas estarán orientadas a dos objetivos: reducir la energía total consumida por un conjunto de trabajos y controlar en consumo puntual de un conjunto puntual para evitar saturaciones del sistema en aquellos centros que puedan tener una capacidad limitada (permanente o puntual). El primer grupo de políticas intentará reducir el consumo total minimizando el impacto en el rendimiento. En este grupo encontramos una primera política que asigna la frecuencia de las cpus en función de la utilización del sistema y una segunda que calcula una estimación de la penalización que sufrirá el trabajo que va a empezar para decidir si reducir o no la frecuencia. Estas políticas han mostrado unos resultados aceptables con sistemas poco cargados, pero han mostrado unas pérdidas de rendimiento significativas cuando el sistema está muy cargado. Estas pérdidas de rendimiento no han sido a nivel de incremento significativo del tiempo de ejecución de los trabajos, pero sí de las métricas de rendimiento que incluyen el tiempo de espera de los trabajos (habituales en este contexto). El segundo grupo de políticas, orientadas a sistemas con limitaciones en cuanto a la potencia que pueden consumir, han mostrado un gran potencial utilizando DVFS como mecanismo de gestión. En este caso, comparado con un sistema que no incluya esta gestión, han demostrado mejoras en el rendimiento ya que permiten ejecutar más trabajos de forma simultánea, reduciendo significativamente el tiempo de espera de los trabajos. En este segundo grupo proponemos una política basada en el rendimiento del trabajo que se va a ejecutar y una segunda que considera la asignación de todos los recursos como un problema de optimización lineal. Esta última política es la contribución más importante de la tesis ya que demuestra un buen comportamiento en todos los casos evaluados. La última contribución de la tesis es un estudio del potencial de DVFS como técnica de gestión de la energía en un futuro próximo, en función de un estudio de las características de las aplicaciones, de la reducción de DVFS en el consumo de la CPU y del peso de la CPU dentro de todo el sistema. Este estudio indica que la capacidad de DVFS de ahorrar energía será limitado pero sigue mostrando un gran potencial de cara al control del consumo energético.

Switching power converters are an indispensable part of every battery-operated consumer electronic product, nourishing regulated voltages to various subsystems. In these circuits, sensing the inductor current is not only necessary for protection and control but also is critical to be done in a lossless and accurate fashion for state-of-the-art advanced control techniques, which are devised to optimize transient response, increase the efficiency over a wide range of loads, eliminate off-chip compensation networks, and integrate the power inductor. However, unavailability of a universal, integrable, lossless, and accurate current-sensing technique impedes the realization of those advanced techniques and limit their applications. Unfortunately, use of a conventional series sense resistor is not recommended in high-performance, high-power switching regulators where more than 90% efficiency is required because of their high current levels. A handful of lossless current-sensing techniques are available but their accuracies are significantly lower than the traditional sense resistor scheme. Among available lossless but not accurate techniques, an off-chip, filter-based method that uses a tuned filter across the inductor to estimate current flow and its accuracy is dependent on the inductance and its equivalent series resistance (ESR) was selected for improvement because of its inherent continuous and low-noise operation. A schemes is proposed to adapt the filter technique for integration by automatically adjusting bandwidth and gain of an on-chip programmable gm-C filter to the off-chip power inductor during the system start-up through measuring the inductance and its ESR with on-chip generated test currents. The IC prototype in AMI s 0.5-um CMOS process achieved overall DC and AC gain errors of 8% and 9%, respectively, at 0.8 A DC load and 0.2 A ripple currents for inductors from 4 uH-14 uH and ESR from 48 mOhm to 384 mOhm when lossless, state-of-the-art schemes achieve 20 40% error and only when the nominal specifications of power component (power MOSFET or inductor) are known. Moreover, the proposed circuit improved the efficiency of a test bed current-mode controlled switching regulator by more than 2.6% at 0.8 A load compared to the traditional sense resistor technique with a 50 mOhm sense resistor.

As time goes by rapid development of 3D graphics technique and 3C portable product output, 3D graphics have been widely applied to handheld devices, such as notebooks, PDAs, and smart cellular phones. Generally, to process 3D graphics applications in mobile devices, processor needs strong capability of handling large computational-intensive workloads. Complex computation consumes a great quantity of electric power. But the lifetime of handheld device battery is limited. Therefore, the cost, to satisfy this demand, will be shortening the supply time of device battery. Moreover, Moore¡¦ law said that the number of transistors in a chip is double in every eighteen months. But these days the advance in manufacturing batteries still cannot get up with the advance in developing processors. In addition, the improvement of chip size has led to more small, supply voltage of kernel processor in portable device. Considering system efficiency and battery lifetime simultaneously increase the difficulty of designing power management scheme. So, how to manage power effectively has become one of the important key for designing handheld products. For 3D graphics system, dynamic voltage and frequency scaling (DVFS) is one of good solutions to implement power management policy. DVFS needs an efficient online prediction method to predict the workload of frames and then appropriately adjust voltage and frequency for saving energy consumption. Consequently, a lot of related papers have proposed different prediction policy to predict the executing workload of 3D graphics system. For instance, the existing prediction policies include signature-based[1], history-based[3] and proportion-integral-derivative (PID)[14] methods, but most of designers put power management in software, i.e. processors. This solution not only slows power management to get the information about executing time of graphic processing unit (GPU), but also increases the operating overhead of CPU in handheld system. In this paper, we propose a power management workload prediction scheme with a framework of using proportion-integral (PI) controller to be a master controller and fuzzy controller to be a slave controller, and then implement it into hardware circuit. Taking advantage of fuzzy conception in fuzzy controller is to adjust the proportional parameter in PI controller, the shortage of traditional PI controller that demands on complicated try-and-error method to look for a good proportional and integral parameters can be avoided so that the adaption and forecasting accuracy can be improved. Besides, Uniform Window-size Predictor 1 (UW1) is also implemented as an assistant manner. Using UW1 predictor appropriately can improve the prediction trend to catch up with the trend of real workload. Experimental results show that our predictor improves prediction accuracy about 3.8% on average and saves about 0.02% more energy compared with PI predictor[18]. Circuit area and power consumption only increases 6.8% percent and 1.4% compared with PI predictor. Besides, we also apply our predictor to the 3D first person game, Quake II, in the market. The result shows that our predictor is indeed an effective prediction policy. The adaption can put up with the intense workload variation of real game and adjust voltage and frequency precisely to decrease power consumption and meet the purpose of energy saving.

Because of the shortage of domestic energy resources in Taiwan, more than 97% of the energy has to be imported. The energy price has been increased dramatically during recent years due to the limited supply of conventional primary fossil energy resources. With the economic development and upgrade of people living standard, the electricity power consumption is increased significantly. To solve the problem, different strategies of energy conservation and CO2 emission reduction have been promoted by government to reduce that the peak loading growth and achieve better usage of electricity with more effective load management. This thesis proposes a digital smart meter which integrates the energy metering IC, microprocessor and hybrid communication schemes (Power Line Carrier/ZigBee/RS-485). The load control module and communication module are included in the smart meter to support various application functions. The embedded power management system (PMS) is also proposed to integrate with the smart meter to perform the demand response according to the real-time pricing and load management for residential and commercial customers. The master station can supervise the real-time power consumption of various load components to analyze the power consumption model of customers served and execute the demand load control. The actual demonstration system of embedded PMS has been set up to verify the function of energy management so that the customers have better understanding of power consumption by each appliance. In the future, the implementation of intelligent load control with an emergency load shedding of capability can help utility companies to achieve virtual power generation to enhance the power systems reliability. The customers may also reduce the electricity charge by executing demand response function, which disconnects the electricity service for non essential loads for either system emergency or high electricity peak pricing

In modern life, 3D graphics system is widely applied to portable product like Notebook, PDA and smart phone. Unlike desktop system, the capacity of batteries of these embedded systems is finite. Furthermore, rapid improvement of IC process leads to quick growth in the transistor count of a chip. According to above-mentioned reason and the complex computation of 3D graphics system, the power consumption will be very large. To efficiently lengthen the lifetime of battery, power management is an indispensable technique. Dynamic voltage and frequency scaling (DVFS) is one of the popular power management policy. In the scheme of DVFS, an accurate workload predictor is needed to predict the workload of every frame. According to these predictions a specific voltage and frequency level is applied to each frame of the 3D graphics system. The number of the voltage/frequency levels and the voltage/frequency of each level are fixed, the voltage/frequency table is decided according to the application of power management. Whenever the workload predictor completes the workload prediction of next frame, the voltage/frequency level of next frame will be found by looking up the voltage/frequency table. In this thesis, we propose a power management scheme with a framework composed of mainly Kalman filter and an auxiliary fuzzy controller to predict the workload of next frame. This scheme amends the shortcomings of traditional Kalman filter that needs to know the system features beforehand. And we propose a brand new concept named ¡¨delayed display¡¨ to massively reduce the miss rate of prediction without changing the framework of predictor.

This paper presents a novel power management analysis method to reduce the power consumption for the non-contact vital sign sensor. The sensor consisting of the class-E power amplifier (PA), low noise amplifier (LNA), single pole double through (SPDT) switch, and circularly polarized antenna (CPA) is integrated on the Flame Retardant Class 4 (FR-4) epoxy-glass laminate substrate. The appropriate pulse width and pulse period are determined to decrease the power consumption and accurately detect the human physiological signals (respiration and heartbeat). A simple direct down-conversion architecture with a tunable phase shifter is utilized to eliminate the null detection point and the direct current (DC) offset. The overall power consumption of the proposed sensor with the novel power management technique is only 40 % of the conventional system with the DC bias, which can be utilized for the green energy application.

The power management technique is employed in the direct down-conversion non-quadrature microwave Doppler radar transceiver for the non-contact vital sign detection based on 0.18 µm CMOS technology. The overshoot and undershoot types of the transient waveform distortion and the simultaneous switching noise (SSN) caused by the high speed pulse signal will severely influence the accuracy for the vital sign detection, so that this investigation clearly analyzes the pulse period, pulse width, rise/fall times and the voltage levels of the pulse bias. In the circuit design, the low power current-reused (CRU) power amplifier (PA) can maintain enough output power by using the crucial double primary transformer (DPTF) and balun. The presented LNA with a differential inductor can provide the noise matching needed and increase the transducer gain in order to achieve the optimal power consumption and the transducer gain in the Rx mode. The excellent isolation between the Tx and Rx mode is obtained with the new parallel directed switch. The overall power consumption of the presented transceiver with the optimal pulse bias is 60% lower than the conventional transceiver with the direct current (DC) bias, and the null detection point and DC offset can be eliminated by the tunable phase shifter.