Power-amplifier efficiency is a significant issue for the overall efficiency of most wireless system. Therefore, currently there are different kind of Switched mode power amplifiers are developed which are showing very high efficiency also at higher frequencies but all of these amplifiers are subjected to drive with the constant envelope signals. Whereas, for the increasing demand of high data rate transmissions in wireless communication there are some new modulation schemes are introduced and which are generating no more a constant envelope signal but a high peak to average power signal. Therefore, recently a new technique is proposed called the burst mode operation for operating the switched mode power amplifiers efficiently while driven by a high peak to average power signal.   The purpose of this master thesis work was to review the theory of this burst mode operation and some basic investigations of this theory on switched mode power amplifiers were performed in simulation environments. The amplifiers of class D, inverse D, DE and J are studied. The thesis work was mainly carried out by ADS and partly in MATLAB SIMULINK environment. Since this burst mode operation is a completely new technique therefore a new Harmonic balance simulation setups in ADS and Microwave Office are developed to generate the RF burst signals.   A Class J amplifier based on LDMOS technique is measured by a 16 carrier multi-tone signal having peak to average power ratio of 7 dB and achieved the drain efficiency of 50% with -30 dBc linearity at 946 MHz.

Noise contribution in nonlinear systems is very different from that in linear systems. The noise effects in nonlinear systems can be complicated and not obvious to predict. In this thesis, the focus was on the noise contribution in nonlinear systems when measuring with the nonlinear vector network analyzer (NVNA). An additional noise source together with a single sinewave signal was fed into the input of the amplifier and the performance was studied. The input power of the amplifier is considered to be the sum of the noise power and the signal power. The variation of the 1 dB compression point and the third order interception point as functions of the added noise power were studied. From the measured results in this thesis, the 1 dB compression point referred to the output power will decrease when increasing the added noise power at the input of the amplifier. The contribution of the added noise to the 1 dB compression point of an amplifier is considered dual: with the added noise the linear regression lines of the AM/AM curves are changed, and due to hard clipping the useful output power is reduced. As a result of those two effects, the added noise made the compression start at a lower power level. When the added noise reaches a certain level, the 1 dB compression point is hard to measure. Thus when performing nonlinear measurements, the noise effects should be taken into considerations and further studies are required to get better understanding of the system’s behavior in noisy environment.

The purpose with the report is to show that it is possible to design a class-D amplifier, using a programmable FPGA mounted on a developing card from Xess and a H-bridge. The FPGA was programmed in VHDL which is the language the software from Xilinx use to implement a logical function into the FPGA The logical function corresponds to a modeling of the music signal and the modeling can be described as a comparator which compare the music signal with a triangle wave and as a out signal produce a pulse width modulated (PWM) signal. The report is also a review and evaluating of two different modulating technologies, AD- modeling and BD-modeling. A detailed part about how the H-bridge was designed and how it works. The result of this project is a working audio amplifier to a significant lower price than the products in todays market.

Radio frequency (RF) communications are limited to a number of frequency bands scattered over the radio spectrum. Applications over such bands increasingly require more versatile, data extensive wireless communications that leads to the necessity of high bandwidth efficient interfaces, operating over wideband frequency ranges. Whether for a base station or mobile device, the regulations and adequate transmission of such schemes place stringent requirements on the design of transmitter front-ends. Increasingly strenuous and challenging hardware design criteria are to be met, especially so in the design of power amplifiers (PA), the bottle neck of the transmitter’s design tradeoff between linearity and power efficiency. The power amplifier exhibits a nonideal behavior, characterized by both nonlinearity and memory effects, heavily affecting that tradeoff, and therefore requiring an effective linearization technique, namely Digital Predistortion (DPD). The effectiveness of the DPD is highly dependent on the modeling scheme used to compensate for the PA’s nonideal behavior. In fact, its viability is determined by the scheme’s accuracy and implementation complexity. Generic behavioral models for nonlinear systems with memory have been used, considering the PA as a black box, and requiring RF designers to perform extensive testing to determine the minimal complexity structure that achieves satisfactory results. This thesis first proposes a direct systematic approach based on the parallel Hammerstein structure to determine the exact number of coefficients needed in a DPD. Then a physical explanation of memory effects is detailed, which leads to a close-form expression for the characteristic behavior of the PA entirely based on circuit properties. The physical expression is implemented and tested as a modeling scheme. Moreover, a link between this formulation and the proven behavioral models is explored, namely the Volterra series and Memory Polynomial. The formulation shows the correlation between parameters of generic behavioral modeling schemes when applied to RF PAs and demonstrates redundancy based on the physical existence or absence of modeling terms, detailed for the proven Memory polynomial modeling and linearization scheme.

In wireless communication systems, multiple standards have been implemented to meet the past and present demands of different applications. This proliferation of wireless standards, operating over multiple frequency bands, has increased the demand for radio frequency (RF) components, and consequently power amplifiers (PA) to operate over multiple frequency bands. In this research work, a systematic approach for the synthesis of a novel dual-band matching network is proposed and applied for effective design of PA capable of maintaining high power efficiency at two arbitrary widely spaced frequencies. The proposed dual-band matching network incorporates two different stages. The first one aims at transforming the targeted two complex impedances, at the two operating frequencies, to a real one. The second stage is a dual-band filter that ensures the matching of the former real impedance to the termination impedance to 50 Ohm. Furthermore, an additional transmission line is incorporated between the two previously mentioned stages to adjust the impedances at the second and third harmonics without altering the impedances seen at the fundamental frequencies. Although simple, the harmonic termination control is very effective in enhancing the efficiency of RF transistors, especially when exploiting the Class J design space. The proposed dual-band matching network synthesis methodology was applied to design a dual-band power amplifier using a packaged 45 W gallium nitride (GaN) transistor. The power amplifier prototype maintained a peak power efficiency of about 68% at the two operating frequencies, namely 800 MHz and 1.9 GHz. In addition, a Volterra based digital predistortion technique has been successfully applied to linearize the PA response around the two operating frequencies. In fact, when driven with multi-carrier wideband code division multiple access (WCDMA) and long term evolution (LTE) signals, the linearized amplifier maintained an adjacent channel power ratio (ACPR) of about 50 dBc and 46 dBc, respectively.

High linearity transmitters and receivers should be used to efficiently utilize the available channel bandwidth. Power consumption is also a critical factor that determines the battery life of portable devices and wireless sensors. Three base-band and RF building blocks are designed with the focus of high linearity and low power consumption. An architectural attenuation-predistortion linearization scheme for a wide range of operational transconductance amplifiers (OTAs) is proposed and demonstrated with a transconductance-capacitor (Gm-C) filter. The linearization technique utilizes two matched OTAs to cancel output harmonics, creating a robust architecture. Compensation for process variations and frequency-dependent distortion based on Volterra series analysis is achieved by employing a delay equalization scheme with on-chip programmable resistors. The distortion-cancellation technique enables an IM3 improvement of up to 22dB compared to a commensurate OTA without linearization. A proof-of-concept lowpass filter with the linearized OTAs has a measured IM3 < -70dB and 54.5dB dynamic range over its 195MHz bandwidth. Design methodology for high efficiency class D power amplifier is presented. The high efficiency is achieved by using higher current harmonic to achieve zero voltage switching (ZVS) in class D power amplifier. The matching network is used as a part of the output filter to remove the high order harmonics. Optimum values for passive circuit elements and transistor sizes have been derived in order to achieve the highest possible efficiency. The proposed power amplifier achieves efficiency close to 60 percent at 400 MHz for -2dBm of output power. High efficiency class A power amplifier using dynamic biasing technique is presented. The power consumption of the power amplifier changes dynamically according to the output signal level. Effect of dynamic bias on class A power amplifier linearity is analyzed and the results were verified using simulations. The linearity of the dynamically biased amplifier is improved by adjusting the preamplifier gain to guarantee constant overall gain for different input signal levels.

This thesis improved the structure of traditional envelope elimination and restoration transmitter by replacing the analog components of envelope detector and limiter using digital processing technique of polar transformation. Envelope signal was modulated by delta-sigma modulation, which could suppress the quantization noise and would be good for integrated circuit design. The front end analog circuits of transmitter used high efficiency class-S and class-E power amplifiers to amplify envelope and phase signal separately and finally combined them at the output of class-E power amplifier. The RF transmitters using polar modulation had advantages of high efficiency and linearity when transmitting high PAPR-valued digital modulation signals. For example, when transmitting the QPSK-modulated signal with 900MHz carrier and 1Msps data rate, the transmitter was measured with efficiency as high as 60%, ACPR above 34dB, and EVM less than 6.5%.

In modern wireless communication systems, new modulation types are introduced in order to support more users by considering spectral efficiency. These new signals are ensitive to nonlinearity when they have high peak to average ratio. The main part in the system that causes nonlinearity is the power amplifier. For power amplifiers, between linearity and efficiency, there is a trade-off. However, by using predistortion techniques, both linearity and efficiency can be obtained. In this thesis, various predistortion methods are explained and memory polynomial digital predistortion is studied because of its great advantages. The results are obtained by simulations through MATLAB and experiments. An open loop test bench is built up with real amplifier. During experimental procedure, as input two tone signal, 8psk modulated signal and pi/2 bpsk modulated signal are used. Predistortion with memory and memoryless predistortion performances are compared and superiority of the predistortion with memory is shown. Predistortion performance with respect to memory depth and polynomial order is also studied. Moreover, predistortion model range is investigated through evaluation of performance by applying predistorter function estimated at a specific bandwidth and power to other signals having different bandwidth and power. Besides these works, the details of predistortion algorithm and the problems that can be countered in practice are explained.

This thesis focuses on the design and implementation of a three-level Class D audio amplifier by applying recently developed sliding-mode quantized control. The designed controller, which consists of the analog filters and logic circuit, switches an H-bridge Class-D amplifier with a lowpass LC filter and operates it in the sliding mode, in order to achieve desired stability and high fidelity in the audio band. The experimental result shows that the lowest THD+N (total harmonic distortion plus noise) can be as low as 0.02% at 1 kHz. The performance is better than most of the available commercial products.

High-efficiency performance is one of the most important requirements of power amplifiers (PAs) for wireless applications. However, the design of highly efficient CMOS PAs for watt-level applications is a challenging task. This dissertation focuses on the development of the design method for highly efficient CMOS PAs to overcome the fundamental difficulties presented by CMOS technology. In this dissertation, the design method and analysis for a high-power and highefficiency class-E CMOS PA with a fully integrated transformer have been presented. This work is the first effort to set up a comprehensive design methodology for a fully integrated class-E CMOS PA including effects of an integrated transformer, which is very crucial for watt-level power applications. In addition, to improve efficiency of cascode class-E CMOS PAs, a charging acceleration technique is developed. The method accelerates a charging speed to turn off the common-gate device in the off-state, thus reducing the power loss. To demonstrate the proposed cascode class-E PA, a prototype CMOS PA was implemented in a 0.18-μm CMOS process. Measurements show an improvement of approximately 6% in the power added efficiency. The proposed cascode class-E PA structure is suitable for the design of high-efficiency class-E PAs while it reduces the voltage stress across the device.