Yes / RF power amplifiers in mobile WiMAX transceivers operate in an inherently nonlinear manner. It is possible to amplify the signal in the linear region, and avoid distortion, using output power back-off; however, this approach may suffer significant reduction in efficiency and power output. This paper investigates the use of Doherty techniques instead of back-off, to simultaneously achieve good efficiency and acceptable linearity. A 3.5 GHz Doherty RFPA has been designed and optimized using a large signal model simulation of the active device, and performance analysis under different drive levels. However, the Doherty EVM is generally poor for mobile WiMAX. Linearity may be improved by further digital pre-distortion, and a simple pre-distortion method using forward and reverse AM-AM and AM-PM modeling. Measurements on the realized amplifier show that this approach satisfies the EVM requirements for WiMAX base stations. It exhibits a PAE over 60%, and increases the maximum linear output power to 43 dBm, whilst improving the EVM.

Modern RF and millimeter-wave communication links call for high-efficiency front end systems with high output power and high linearity to meet minimum transmission requirements. Advanced modulation techniques, such as orthogonal frequency-division multiplexing (OFDM) require a large power amplifier (PA) dynamic range due to the high peak-to-average power ratio (PAPR). This thesis provides the analysis, design, and experimental verification of a high-efficiency, high-linearity S-band Doherty power amplifier (DPA) based on the Class F PA. Traditional Class F PAs use harmonically tuned output matching networks to obtain up to 88.4% power-added efficiency (PAE) theoretically, however the amplifier experiences poor linearity performance due to switched mode operation, typically yielding less than 30dB C/I ratio [1]. The DPA overcomes this linearity limitation by using an auxiliary amplifier to boost output power when the amplifier is subject to a high input power due to its limited conduction cycle. The DPA also provides improved saturated output power back-off performance to maintain high PAE during operation. The DPA presented in this thesis optimizes PAE while maintaining linearity by employing harmonically tuned Class F amplifier topology on a primary and an auxiliary amplifier. A Class F PA is first designed and fabricated to optimize output network linearity – this is followed by a DPA design based on the fabricated Class F PA. A GaN HEMT Class F PA and DPA operating at 2.2GHz are implemented with the PAs measuring 40% and 45% PAE respectively while maintaining a 30dB carrier-to-intermodulation (C/I) ratio on a two-tone test. The PAE is characterized at maximum 21dBm input power per tone and 20MHz tone spacing. When subject to a single 24dBm continuous wave input tone, the Class F PA and DPA output 37dBm and 35.5dBm respectively. The PAs presented in the thesis provide over 30dB C/I ratio up to 21dBm input tones while maintaining over 40% PAE suitable for base station applications.

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Gallium Nitride (GaN) technology is capable of very high power levels but suffers from high non-linearity. With the advent of 5G technologies, high linearity is in greater demand due to complex modulation schemes and crowded RF (Radio Frequency) spectrum. Because of the non-linearity issue, GaN power amplifiers have to be operated at back-off input power levels. Operating at back-off reduces the efficiency of the power amplifier along-with the output power. This research presents a technique to linearize GaN amplifiers. The linearity can be improved by splitting a large device into multiple smaller devices and biasing them individually. This leads to the cancellation of the IMD3 (Third-order Intermodulation Distortion) components at the output of the FETs and hence higher linearity performance. This technique has been demonstrated in Silicon technology but has not been previously implemented in GaN. This research work presents for the first time the implementation of this technique in GaN Technology. By the application of this technique, improvement in IMD3 of 4 dBc has been shown for a 0.8-1.0 GHz PA (Power Amplifier), and 9.5 dBm in OIP3 (Third-order Intercept Point) for an S-Band GaN LNA, with linearity FOM (IP3/DC power) reaching up to 20. Large-signal simulation and analysis have been done to demonstrate linearity improvement for two parallel and four parallel FETs. A simulation methodology has been discussed in detail using commercial CAD software. A power sampler element is used to compute the IMD3 currents coming out of various FETs due to various bias currents. Simulation results show by biasing one device in Class AB and others in deep Class AB, IMD3 components of parallel FETs can be made out of phase of each other, leading to cancellation and improvement in linearity. Improvement up to 20 dBc in IMD3 has been reported through large-signal simulation when four parallel FETs with optimum bias were used. This technique has also been demonstrated in simulation for an X-Band MMIC PA from 8-10 GHz in GaN technology. Improvements up to 25-30 dBc were shown using the technique of biasing one device with Class AB and other with deep class AB/class B. The proposed amplifier achieves broadband linearization over the entire frequency compared to state-of-the-art PA's. The linearization technique demonstrated is simple, straight forward, and low cost to implement. No additional circuitry is needed. This technique finds its application in high dynamic range RF amplifier circuits for communications and sensing applications. / Doctor of Philosophy / Power amplifiers (PAs) and Low Noise Amplifiers (LNAs) form the front end of the Radio Frequency (RF) transceiver systems. With the advent of complex modulation schemes, it is becoming imperative to improve their linearity. Through this dissertation, we propose a technique for improving the linearity of amplifier circuits used for communication systems. Meanwhile, Gallium Nitride (GaN) is becoming a technology of choice for high-power amplifier circuits due to its higher power handling capability and higher breakdown voltage compared with Gallium Arsenide (GaAs), Silicon Germanium (SiGe) and Complementary Metal-Oxide-Semiconductor (CMOS) technologies. A circuit design technique of using multiple parallel GaN FETs is presented. In this technique, the multiple parallel FETs have independently controllable gate voltages. Compared to a large single FET, using multiple FETs and biasing them individually helps to improve the linearity through the cancellation of nonlinear distortion components. Experimental results show the highest linearity improvement compared with the other state-of-the-art linearization schemes. The technique demonstrated is the first time implementation in GaN technology. The technique is a simple and cost-effective solution for improving the linearity of the amplifier circuits. Applications include base station amplifiers, mobile handsets, radars, satellite communication, etc.

As the oil industry continues to drill deeper to reach previously untapped wells, the operating environments for electronic systems become harsher, especially due to high temperatures. It is essential to design electronic circuits and systems to be able to withstand these extreme temperatures. The proposed power amplifier (PA) has been designed for a downhole communication system operating at an ambient temperature of 230oC. GaN technology was chosen primarily due to its ability to function at a high junction temperature. The proposed PA was designed with Qorvo's T2G6003028-FL HEMT as it operates reliably at a high junction temperature (T_J) and also the package offers low junction to case thermal resistance . The proposed PA can operate reliably up to an ambient temperature of 230oC using passive cooling opposed to active cooling. At 230 C it operates in class A with a peak PAE of 25.03%, maximum output power of 1.66 W, peak gain of 24.5 dB, center frequency of 255 MHz with 1dB ripple in the passband over a 60 MHz bandwidth, 1dB output compression of approximately 32 dBm, and OIP3 of 37.9dBm. CW measurements were taken for all parameters. / Master of Science

Ever since the FCC allocated 7.5 GHz (from 3.1 GHz to 10.6 GHz) for ultra wideband (UWB) technology, interest has been renewed in both academic and industrial circles to exploit this vast spectrum for short range, high data rate wireless applications. The great potential of UWB lies in the fact that it can co-exist with the already licensed spectrum users and can still pave the way for a wide range of applications. However, this wide bandwidth complicates the circuit level implementation of key RF blocks like the power amplifier (PA), transmit/receive switch, low noise amplifier (LNA) and mixers in an UWB transceiver. Though expensive technologies like SiGe or GaAs have been used for transceiver realizations, the ultimate goal is to have a single-chip, low-cost solution which can only be achieved by using CMOS technology. Nevertheless, some of the inherent limitations of CMOS like lower fT of transistors make the design of UWB circuits in CMOS an extremely challenging task. Two proposals- Multi-Band OFDM and Direct-Sequence CDMA have been put before the IEEE 802.15.3a task group to decide on the industry standard for the commercial deployment of this technology. Though the debate on which standard is better has not been resolved, proponents of both the groups have already begun to develop prototypes of their respective proposals. This thesis describes the design of a key RF block in the UWB transceiver - the Power Amplifier. For the first part of this work, a PA suitable for MB-OFDM specifications was designed and fabricated in TSMC 0.18um CMOS technology. The class-AB PA is able to cover the lower UWB frequency band from 3.1 GHz to 4.75 GHz and delivers an output power of -2 dBm at 4 GHz. Simulated results show a gain of 19±2 dB achieved over the entire band and the PA consumes 36.54 mW from a 1.8V supply. In the second part of this work, a PA that meets the DS-CDMA specifications was designed and fabricated. This PA operates in the class-AB regime, delivering an output power of -4.2 dBm with input-1dB compression point at -22 dBm. Complete design and implementation was done using TSMC 0.18um CMOS technology and it consumes a very low power of 25 mW, while realizing a flat gain of 19±1 dB across the whole band of operation. All the above mentioned results are from simulations in SpectreRF and measurements are yet to be taken. Additional features like power ON/OFF scheme and output impedance control has also been incorporated in the design. / Master of Science

Millimeter wave (mm-Wave) has become increasingly popular frequency band for next-generation high-speed wireless communications. In mm-Wave, the wireless channel path loss is severe, demanding a high output power in transmitters (Tx) to meet a required SNR in receivers (Rx). Due to the intractable speed-power tradeoff ingrained in silicon processes, however, achieving a high power at mm-Wave, particularly over W-band (> 90 GHz), is challenging in silicon power amplifiers. To relieve the output power burden, phased-arrays are widely adopted in mm-Wave wireless communication systems -- namely, by leveraging a parallel power combining in the space domain, inherent in the phased arrays, the required output power per array element can be reduced significantly with increasing array size. In large arrays ( > 100's -- 1000's number of arrays), the required output power per element could be small, typically around several 10's mW or less in silicon-based phased arrays. In such small-to-medium scale output power level, the static power dissipations by transistor knee voltage and passive components could be a significant portion of the output power, decreasing power efficiency of power amplifiers drastically. This poses a significant concern on the power efficiency of the large-scale silicon-based phased arrays in mm-Wave. Another critical problem in mm-Wave wireless systems design is the increase of passive reactive components loss caused by worsening skin depth effect and increasing dielectric loss through silicon substrate. This essentially degrades the reactive components quality factor (Q) and limits frequency selectivity of the silicon-based mm-Wave systems. This thesis tackles these two major technical challenges to provide high frequency selectivity with maintaining high power efficiency for future mm-Wave wireless systems over W-band and beyond. First, various high-efficiency techniques such as impedance tuning with a reactive component at a cascoding stage in conventional stacked power amplifiers or load-pull based inter-stage matching technique, rather than conventional conjugate matching, have been applied to W-band CMOS and SiGe BiCMOS amplifiers to improve power efficiency with 5-10 dBm output power level, suitable for a large phased array applications, as detailed in Chapter 2 and 3. Second, a 4-tap finite impulse response (FIR) filter based receiver architecture is presented in Chapter 4. The FIR filtered receiver leverages a sinc-pulse type frequency nulls built-in in the transmission-line based FIR filter's frequency response to increase frequency selectivity. The proposed FIR filtered receiver achieves > 40-dB image rejection by placing an image signal at the null frequency at D-band, one of the largest image rejection performance at the highest frequency band reported so far. / Ph. D. / Due to recent advances in Silicon based solid-state technologies, the interest towards the millimeter wave (mm-Wave) frequency band has been emerging for next-generation high-speed wireless communication applications. One of the most significant parameters in a communication system would be the output power of a transmitter. However, the output power is limited especially at mm-wave frequencies. A phased array is one of the viable solutions to overcome this burden by utilizing a parallel power combing in the space domain. The required output power per element can be relieved, typically around several tens of mill watts or less. There are two major factors limiting the output power, which are the high loss of passive and active devices. This dissertation presents solutions to overcome these challenges. In addition, a 4-tap finite impulse response (FIR) filter based receiver architecture is introduced, which rejects unwanted image signals in heterodyne systems by utilizing sinc-pulse type frequency nulls. The proposed FIR filter achieves more than 40 dB of image rejection at D-band (110-170 GHz), which is one of the highest filtering performance in the millimeter-wave frequency band.

There has been increased interest in exploring high frequency (mm-wave) spectrum (particularly the 30 and 60 GHz ranges), and utilizing silicon-based technology for reduced-cost monolithic millimeter integrated circuits (MMIC), for applications such as WLAN, inter-vehicle communication (IVC) automotive radar and local multipoint distribution system (LMDS). Although there has been a significant increase in silicon-based implementations recently, this area still has significant need for research and development. For example, one microwave/mm-wave front-end component that has seen little development in silicon is the power amplifier (PA). Two potential technologies exist for providing a solution for low-cost microwave/mm-wave power amplifiers: 1) Silicon-Germanium (SiGe) HBT and 2) Complementary metal-oxide semiconductor (CMOS). SiGe HBT has become a viable candidate for PA development since it exhibits higher gain and higher breakdown voltage limits compared to CMOS, while remaining compatible with BiCMOS technology. Also, SiGe is potentially lower in cost compared to other compound semiconductor technologies that are currently used in power amplifier design. Hence, this research focuses on design of millimeter-wave power amplifiers in SiGe HBT technology. The work presented in this thesis will focus on design of different power amplifiers for millimeter-wave operating frequencies. Amplifiers present the fundamental trade-off between linearity and efficiency. Applications at frequencies highlighted above tend to be point-to-point, and hence high linearity is required at the cost of lowered efficiency for these power amplifiers. The designed power amplifiers are fully differential topologies based on finite ground coplanar waveguide (FGC) transmission line technology, and have on-chip matching networks and bias circuits. The selection and design of FGC lines is supported through full-wave EM simulations. Tuned single stub matching networks are realized using FGC technology and utilized for input and output matching networks. Two 30-GHz range SiGe HBT PA designs were carried out in Atmel SiGe2RF and IBM BiCMOS 8HP IC technologies. The designs were characterized first by simulations. The performance of the Atmel PA design was characterized using microwave/mm-wave on wafer test measurement setup. The IBM 8HP design is awaiting fabrication. The measured results indicated high linearity, targeted output power range, and expected efficiency performance were achieved. This validates the selection of SiGe HBT as the technology of choice of high frequency point-to-point applications. The results show that it is possible to design power amplifiers that can effectively work at millimeter-wave frequencies at lower cost for applications such as mm-wave WLAN and IVC where linearity is important and required transmitted power is much lower than in cellular handset power amplifiers. Moreover, recommendations are made for future research steps to improve upon the presented designs. / Master of Science

Over the last few decades, the susceptibility of integrated circuits to electrostatic discharge (ESD) induced damages has justified the use of dedicated on-chip protection circuits. Design of robust protection circuits remains a challenging task because ESD failure mechanisms have become more acute as device dimensions continue to shrink. A lack of understanding of the ESD phenomena coupled with the increased sensitivity of smaller devices and time-to-market demands has led to a trial-and-error approach to ESD-protected circuit design. Improved analysis capabilities and a systematic design approach are essential to accomplish the challenging task of providing adequate protection to core circuit(s). The design of ESD protection circuitry for RFIC's has been relatively slow to evolve, compared to their digital counterparts, and is now emerging as a new design challenge in RF and high-speed mixed-signal IC development. Sub-circuits which are not embedded in a single System-on-Chip (SOC), such as RF Power amplifiers (PAs), are of particular concern as they are more susceptible to the various ESD events. This thesis presents the development of integrated ESD protection circuitry for two RFIC Power Amplifier designs. A prototype PA for 2.4 GHz Wireless Local Area Network (WLAN) applications was redesigned to provide protection to the RF input and the PA Control pins. A relatively new technique known as the L-C tank approach was used to protect the RFinput while a standard diode ring approach was used to protect the control line. The protection techniques studied were subsequently extended to a completely protected three-stage PA targeting 1.9 GHz Digitally Enhanced Cordless Telephone (DECT) applications. An on-chip shunt-L-series-C input matching network was used to provide ESD protection to the input pin of the DECT PA. A much more area efficient (as compared to the diode ring technique) Zener diode approach was used to protect the control and signal lines. The PA's RF performance was virtually unaffected by the addition of the protection circuits. Both PAs were designed in a commercially available 0.5 ìm SiGe-HBT process. The partially protected WLAN PA was fabricated and packaged in a 3mm x 3mm Fine Pitch Quad Flat Package FQFP-N 12 Lead package and had a measured ESD protection rating of ± 1kV standard Human Body Model (HBM) ESD test. The simulated DECT PA demonstrated +1.5kV/-4kV HBM performance. / Master of Science