This thesis considers the use of the tone reservation (TR) technique in orthogonal frequency division multiplexing (OFDM) systems. The nonlinear distortion is usually introduces by the high power amplifiers (HPA) used in wireless communications systems. It orders to reduce the inter-modulation distortion (IMD) in OFDM systems. In addition to the original peak-to-average power ratio (PAPR)-reduction criterion, we propose signal-to-distortion plus noise power ratio (SDNR) criterion and distortion power plus inverse of signal power (DIS) criterion. Based on these criteria, the cross-entropy (CE) algorithm is introduced to determine desired values of the peak reduction carriers (PRCs) to improve the bit error rate (BER) of nonlinearly distorted. Computational complexity is always the major concern of PAPR technique. Therefore, the real-valued PRCs and the modified transform decomposition (MTD) method are introduced here to dramatically decrease complexity of inverse fast Fourier transform (IFFT) operation with slightly performance loss. The simulation results show that the proposed criteria provide a better BER performance and a lower computational complexity.

In modern wireless communication systems, advanced modulation techniques are used to support more users by handling high data rates and to increase the utilization efficiency of the limited RF spectrum. These techniques are sensitive to the nonlinear distortions due to their high peak to average power ratios. Main source of nonlinear distortion in transmitter topologies are power amplifiers that determine the overall efficiency and linearity of the transmitter. To increase linearity without sacrificing efficiency, power amplifier linearization techniques may be a choice. Baseband predistortion technique is known to be one of the optimum methods due to its relatively low complexity and its convenience for adaptation. In this thesis, different memoryless baseband signal predistortion methods are investigated and analyzed by simulations. Look-Up Table(LUT) and Polynomial approaches are compared and LUT approach is found to be better in performance. Parameters, like indexing, training sequences and training duration are evaluated. An open loop testbench is built with a real amplifier and a different LUT predistortion method that is based on amplifier modeling is offered. It is evaluated by using two tone test and adjacent channel power suppression with 8PSK data. Also, some Look-Up Table parameters are re-investigated with the proposed method. The performances of the proposed method in dierent amplifier classes are observed. Along with these studies, a list of prerequisites for design of a predistortion system is determined.

The explosive growth of the wireless market has increased the demand for low-cost, highly-integrated CMOS wireless transceivers. However, the implementation of CMOS RF power amplifiers remains a formidable challenge. The objective of this research is to demonstrate the feasibility of CMOS RF power amplifiers by compensating for the RF performance disadvantages of CMOS technology. This dissertation proposes a parallel-combining transformer (PCT) as an impedance-matching and output-combining network. The results of a comprehensive analysis show that the PCT is a suitable solution for watt-level output power generation in cellular applications. To achieve high output power and high efficiency, the work presented here entailed the design of a class-E switching power amplifier in a 0.18-μm CMOS technology for GSM applications and, with the suggested power amplifier design technique, successfully demonstrated a fully-integrated RF front-end consisting of a power amplifier and an antenna switch. This dissertation also proposed an efficiency enhancement technique at power back-off. In an effort to save current in the power back-off while satisfying the EVM requirements, a class-AB linear power amplifier was implemented in a 0.18-μm CMOS technology for WLAN and WiMAX applications using a PCT as well as an operation class shift between class-A and class-B. Thus, the research in this dissertation provides low-cost CMOS RF power amplifier solutions for commercial products used in mobile wireless communications.

The objective of this research is to analyze and improve linearity of envelope elimination and restoration (EER) radio frequency (RF) power amplifiers. Envelope elimination and restoration was compared to other efficiency enhancement techniques and determined to likely be the most suitable solution for implementation of multimode, multiband portable RF transmitters. Distortion, stemming from dynamic power-supply modulation of RF transistors in EER RF power amplifiers was identified as one of the key challenges to the development of commercially viable EER transmitters. This dissertation presents a study of phase distortion in RF power amplifiers (PAs) with emphasis on identification of the origins of phase distortion in EER RF power amplifiers. Circuit-level techniques for distortion mitigation are also presented. Memory effects in conventional power amplifiers are investigated through the accurate measurement and analysis of phase asymmetry of out-of-band distortion components. Novel physically-based power amplifier model is developed for attributing measured memory effects to their physical origin. The amount of linearity correction, obtained through pre-distortion for a particular RF power amplifier, is then correlated to the behavior of the memory effects in the corresponding PA. Heterojunction field-effect transistor and heterojunction bipolar transistor amplifiers are used for investigation of voltage-dependent phase distortion in handset EER RF PAs. The distortion is found to stem from vector addition of signals, generated in nonlinear circuit elements of the PA. Specifically, nonlinear base-collector capacitance and downconversion of distortion components from second harmonic frequency are found to be the dominant sources of phase distortion. Shorting of second harmonic is proposed as a way to reduce the distortion contribution of the downconverted signal. Phase distortion is reduced by 50%, however a slight degradation in the amplitude distortion is observed. Push-pull architecture is proposed for EER RF power amplifiers to cancel distortion components, generated in the nonlinear base-collector capacitance. Push-pull implementation enables a 67% reduction in phase distortion, accompanied by a 1-2 dB reduction in amplitude distortion in EER RF power amplifiers. This work, combined with other studies in the field, will help advance the development of multimode, multiband portable RF transmitters, based on the envelope elimination and restoration architecture.

With more and more integration of analog and RF circuits in scaled CMOS technologies, process variation is playing a critical role which makes it difficult to achieve all the performance specifications across all the process corners. Moreover, at scaled technology nodes, due to lower voltage and current handling capabilities of the devices, they suffer from reliability issues that reduce the overall lifetime of the system. Finally, traditional static style of designing analog and RF circuits does not result in optimal performance of the system. A new design paradigm is emerging toward digitally assisted analog and RF circuits and systems aiming to leverage digital correction and calibration techniques to detect and compensate for the manufacturing imperfections and improve the analog and RF performance offering a high level of integration. The objective of the proposed research is to design digital friendly and performance tunable adaptive analog/RF circuits and systems with digital enhancement techniques for higher performance, better process variation tolerance, and more reliable operation and developing strategy for testing the proposed adaptive systems. An adaptation framework is developed for process variation tolerant RF systems which has two parts – optimized test stimulus driven diagnosis of individual modules and power optimal system level tuning. Another direct tuning approach is developed and demonstrated on a carbon nanotube based analog circuit. An adaptive switched mode power amplifier is designed which is more digital-intensive in nature and has higher efficiency, improved reliability and better process resiliency. Finally, a testing strategy for adaptive RF systems is shown which reduces test time and test cost compared to traditional testing.

With the growing trend of wireless electronics, frequency spectrum is crowded with different applications. High data transfer rate solutions that operate in license-exempt frequency spectrum range are sought. The most promising candidate is the 60 GHz multi-giga bit transfer rate millimeter wave circuit. In order to provide a cost-effective solution, circuits designed in CMOS are implemented in a single SOC. In this work, a modeling technique created in Cadence shows an error of less than 3dB in magnitude and 5 degree in phase for a single transistor. Additionally, less than 3dB error of power performance for the PA is also verified. At the same time, layout strategies required for millimeter wave front-end circuits are investigated. All of these combined techniques help the design converge to one simulation platform for system level simulation. Another aspect enabling the design as a single SOC lies in integration. In order to integrate digital and analog circuits together, necessary peripheral circuits must be designed. An on-chip voltage regulator, which steps down the analog power supply voltage and is compatible with digital circuits, has been designed and has demonstrated an efficiency of 65 percent with the specific area constraint. The overall output voltage ripple generated is about 2 percent. With the necessary power supply voltage, gate voltage bias circuit designs have been illustrated. They provide feasible solutions in terms of area and power consumption. Temperature and power supply sensitivities are minimized in first two designs. Process variation is further compensated in the third design. The third design demonstrates a powerful solution that each aspect of variations is well within 10%. As the DC conditions are achieved on-chip for both the digital and analog circuits, digital and analog circuits must be connected together with a DAC. A high speed DAC is designed with special layout techniques. It is verified that the DAC can operate at a speed higher than 3 Gbps from the pulse-shaping FIR filter measurement result. With all of these integrated elements and modeling techniques, a high data transfer rate CMOS RF SOC operating at 60 GHz is possible.

Ce travail concerne la linéarisation des amplificateurs de haute puissance en utilisant la pré-distorsion numérique. L’amplificateur de haute puissance est un composant non-linéaire. La pré-distorsion numérique adaptative en bande de base est un technique efficace pour linéariser ses non-linéarités et ses effets de mémoire. Les modèles de la pré-distorsion numérique de basse complexité sont étudiés dans cette thèse. Un algorithme est proposé pour déterminer une structure optimale de modèle uni-étage ou multi-étage en prenant compte du compromis entre la précision de modélisation et la complexité. La structure cascadée, qui est avantageuse en complexité comparé avec celle d'uni-étage, est étudiée avec des méthodes d'identifications différentes. En termes d'implémentations expérimentales, l'étude d'impact des choix de gain différents est approfondie dans cette thèse. Toutes les études ont été évaluées par un amplificateur de puissance Doherty / This dissertation contributes to the linearization techniques of high power amplifier using digital predistortion method. High power amplifier is one of the most nonlinear components in radio transmitters. Unfortunately, for most current types of power amplifiers, a good efficiency is obtained at the price of a poor linearity especially with modern communication waveforms. Baseband adaptive digital predistortion is a powerful technique to linearize the power amplifiers and allows to push the power amplifier operation point towards its high efficiency region. Linearization of power amplifiers using digital predistortion with low complexities is the focus of this dissertation. An algorithm is proposed to determine an optimal model structure of single-stage or multi-stage predistorter according to a trade-off between modeling accuracy and model complexity. Multi-stage cascaded digital predistortions are studied with different identification methods, which have advantages on complexity of model identification compared with single-stage structure. The linearization performances are validated by experimental implementations on test bench. In terms of experimental implementations, this dissertation studies the impact of different gain choices on linearized power amplifier. All studies are evaluated with a Doherty power amplifier

abstract: As wireless communication enters smartphone era, more complicated communication technologies are being used to transmit higher data rate. Power amplifier (PA) has to work in back-off region, while this inevitably reduces battery life for cellphones. Various techniques have been reported to increase PA efficiency, such as envelope elimination and restoration (EER) and envelope tracking (ET). However, state of the art ET supply modulators failed to address high efficiency, high slew rate, and accurate tracking concurrently. In this dissertation, a linear-switch mode hybrid ET supply modulator utilizing adaptive biasing and gain enhanced current mirror operational transconductance amplifier (OTA) with class-AB output stage in parallel with a switching regulator is presented. In comparison to a conventional OTA design with similar quiescent current consumption, proposed approach improves positive and negative slew rate from 50 V/µs to 93.4 V/µs and -87 V/µs to -152.5 V/µs respectively, dc gain from 45 dB to 67 dB while consuming same amount of quiescent current. The proposed hybrid supply modulator achieves 83% peak efficiency, power added efficiency (PAE) of 42.3% at 26.2 dBm for a 10 MHz 7.24 dB peak-to-average power ratio (PAPR) LTE signal and improves PAE by 8% at 6 dB back off from 26.2 dBm power amplifier (PA) output power with respect to fixed supply. With a 10 MHz 7.24 dB PAPR QPSK LTE signal the ET PA system achieves adjacent channel leakage ratio (ACLR) of -37.7 dBc and error vector magnitude (EVM) of 4.5% at 26.2 dBm PA output power, while with a 10 MHz 8.15 dB PAPR 64QAM LTE signal the ET PA system achieves ACLR of -35.6 dBc and EVM of 6% at 26 dBm PA output power without digital pre-distortion (DPD). The proposed supply modulator core circuit occupies 1.1 mm2 die area, and is fabricated in a 0.18 µm CMOS technology. / Dissertation/Thesis / Doctoral Dissertation Electrical Engineering 2017

CoordenaÃÃo de AperfeiÃoamento de Pessoal de NÃvel Superior / Cooperation diversity and orthogonal frequency division multiplexing (OFDM) are two key technologies for the modern wireless communication systems. The cooperative communication systems considered through this work use the OFDM technology and they are composed of: one transmitter with a nonlinear power amplifier (PA), one or more amplify-and-forward (AF) relays, also having a nonlinear PAs, and one destination node. In this dissertaion, it is initially proposed an optimal receiver, in the signal to noise ratio (SNR) sense, for a nonlinear cooperative AF system. The proposed receiver uses the maximum ratio combining (MRC) diversity technique to combine the received signas, assuming that both the source-destination and source-relay-destination links are available. In the sequel, closed-form expressions for the instantaneous SNR and outage probability of the considered system are developed. The outage analysis is then extended to the case of a multi-hop system, that is, with multiple serial relays. Finally, an outage analysis is also proposed for a nonlinear AF OFDM system using a Selection Combining receiver, considering two cases: one relay and multiple parallel relays. Numerical simulation results are presented through the work, evaluating the performance of the proposed receiver and theoretical expressions. / A diversidade cooperativa e a multiplexaÃÃo por divisÃo de frequÃncias ortogonais (Orthogonal Frequency Division Multiplexing - OFDM) sÃo duas das principais tecnologias para os sistemas de comunicaÃÃo sem fio modernos. Os sistemas de comunicaÃÃo cooperativos considerados neste trabalho de dissertaÃÃo utilizam a tecnologia OFDM e possuem: uma fonte com amplificador de potÃncia nÃo linear, um ou mais repetidores (relays) do tipo amplifica-e-encaminha (Amplify-and-Forward - AF), tambÃm com amplificadores de potÃncia (Power Amplifier - PA) nÃo lineares, e um nà destino. PropÃe-se inicialmente um receptor Ãtimo, no sentido da razÃo sinal ruÃdo (Signal-to-Noise Ratio - SNR) para um sistema OFDM cooperativo nÃo linear. Usando a tÃcnica de diversidade por combinaÃÃo de razÃo mÃxima (Maximal Ratio Combining - MRC) para tratar os sinais recebidos, o receptor proposto considera tanto as informaÃÃes oriundas do caminho direto (fonte-destino) como as provenientes do repetidor. Posteriormente, sÃo apresentadas expressÃes para o cÃlculo da SNR instantÃnea e da probabilidade de outage do sistema proposto. Fez-se ainda, uma proposta de expressÃo para o cÃlculo da probabilidade de outage do sistema considerando mÃltiplos relays em sÃrie. Por fim, propÃe-se expressÃes para o cÃlculo da probabilidade de outage do sistema utilizando receptor Selection Combining para um e para mÃltiplos relays dispostos paralelamente. Resultados de simulaÃÃo sÃo apresentados durante todo o trabalho, evidenciando o desempenho do receptor e das expressÃes propostas.

Ce travail porte sur la conception d'un amplificateur de puissance à 79 GHz et la co-intégration de l'amplificateur de puissance et l'antenne en technologie silicium SiGe. L'objectif de la thèse est de développer un module radiofréquence à l'émission pour des applications radar à 79 GHz. Ce module sera composé d'un amplificateur de puissance, d'une antenne et du circuit d'adaptation PA/Antenne. L'inter-étage entre le PA et l'antenne est une source supplémentaire d'atténuation du signal, d‟autant plus rédhibitoire en technologie intégrée pour des fréquences aussi élevées. En réalisant une conception commune, ou co-design, de l'antenne et de l'amplificateur de puissance (PA), nous pouvons, à terme, nous affranchir du traditionnel inter-étage d'adaptation d'impédance entre ces deux blocs. Plus précisément, il convient de dimensionner l'antenne afin qu'elle présente a la sortie du PA l'impédance optimale que requiert son rendement en puissance maximum. / This work focuses on the design of a power amplifier (PA) at 79 GHz and the co-integration of the PA and the antenna on SiGe technology. The objective of this thesis is to develop a RF front-end block for radar applications at 79 GHz. This block is compound of a power amplifier, antenna and PA/Antenna inter-stage matching. The inter-stage between the PA and the antenna adds supplementary losses in the global performances, especially prohibitive in integrated technology for high frequencies. The co-design of the antenna and the PA allows to suppress the traditional inter-stage impedance matching between these two blocks. More specifically, it is suitable to design the antenna with the appropriate output impedance of the PA which gives optimal performances for maximum power and efficiency.