In today's digital world, information and communication technology accounts for 3% and 2% of the global power consumption and CO2 emissions respectively. This alarming figure is on an upward trend, as future telecommunications systems and handsets will become even more power hungry since new services with higher bandwidth requirements emerge as part of the so called 'future internet' paradigm. In addition, the mobile handset industry is tightly coupled to the consumer need for more sophisticated handsets with greater battery lifetime. If we cannot make any significant step to reducing the energy gap between the power hungry requirements of future handsets, and what battery technology can deliver, then market penetration for 4G handsets can be at risk. Therefore, energy conservation must be a design objective at the forefront of any system design from the network layer, to the physical and the microelectronic counterparts. In fact, the energy distribution of a handset device is dominated by the energy consumption of the RF hardware, and in particular the power amplifier design. Power amplifier design is a traditional topic that addresses the design challenge of how to obtain a trade-off between linearity and efficiency in order to avoid the introduction of signal distortion, whilst making best use of the available power resources for amplification. However, the present work goes beyond this by investigating a new line of amplifiers that address the green initiatives, namely green power amplifiers. This research work explores how to use the Doherty technique to promote efficiency enhancement and thus energy saving. Five different topologies of RF power amplifiers have been designed with custom-made signal splitters. The design core of the Doherty technique is based on the combination of a class B, class AB and a class C power amplifier working in synergy; which includes 90-degree 2-way power splitter at the input, quarter wavelength transformer at the output, and a new output power combiner. The frequency range for the amplifiers was designed to operate in the 3.4 - 3.6 GHz frequency band of Europe mobile WiMAX. The experimental results show that 30dBm output power can be achieved with 67% power added efficiency (PAE) for the user terminal, and 45dBm with 66% power added efficiency (PAE) for base stations which marks a 14% and 11% respective improvement over current stateof- the-art, while meeting the power output requirements for mobile WiMAX applications.

Les travaux présentés dans ce mémoire de thèse portent sur la linéarisation large bande d'amplificateurs de puissance par prédistorsion analogique. Ce travail vise à réduire la pollution spectrale provoquée par leur comportement non-linéaire lors d'une transmission satellite. Ce travail de thèse débute par une présentation des amplificateurs de puissance utilisés dans les émetteurs, en exposant les conséquences de leur comportement non-linéaire sur la qualité du signal. Pour pallier à cela, les techniques de linéarisation couramment utilisées ont été recensées, en mettant l'accent sur leurs avantages et inconvénients. C'est sur la base de cet état de l'art qu'une structure de prédistorsion analogique a pu être identifiée. Il s'agit d'une structure en réflexion à base de diodes Schottky, dont une partie de ce mémoire est consacrée à l'analyse de leur comportement non-linéaire. Appuyée par des résultats de simulations et des mesures effectuées sur maquettes, cette analyse nous a conduit à la mise en œuvre de la structure en réflexion dans le cadre de la linéarisation d'un amplificateur à tube à onde progressive (ATOP) en bande Ku. Nos travaux se sont ensuite tournés vers une nouvelle structure plus innovante, basée sur la mise en cascade de deux circuits de prédistorsion. La structure proposée bénéficie d'une configuration plus flexible et plus précise que la précédente, ce qui nous a permis d'obtenir de meilleurs résultats en matière d'amélioration de la linéarité. La dernière partie de ce travail de thèse est dédiée à l'approche expérimentale de deux méthodes numériques de prédistorsion en bande de base. L'intérêt de cette approche repose sur l'évaluation expérimentale de l'amélioration possible de la linéarité de l'ATOP et la comparaison avec les résultats obtenus par prédistorsion analogique. / The research reported in this PhD Thesis is focused on power amplifier wideband linearization by analog predistortion. This work aims to reduce the spectral regrowth due to their nonlinear response over the satellite transmission. This dissertation starts with a presentation of power amplifiers used in transmitters. Through it, we expose their nonlinearity effects on the signal quality. To overcome those effects, the lattest linearization methods were reviewed, highlighting their strengths and weaknesses. Based on this state of art, an analog predistortion structure was identified. It relates to a reflective structure made up of Schottky diodes, of which a part of this thesis is devoted to the analysis of its nonlinear behavior. Drawn on simulations and measurements, this analysis led us to the implementation of the reflective structure for the purpose of a traveling wave tube amplifier linearization over the Ku band. Our work was then directed towards to a new more innovative structure built on two predistortion circuits wired in series. This new structure gets a more flexible and accurate configuration compared to the previous one and allowed us to obtain better results regarding linearity improvement. The last part of this thesis work is dedicated to an experimental approach of two base band digital predistortion methods. The aim of this approach rests on the achievable enhancement of TWTA linearity and the comparison between the results obtained with the analog predistortion.

Les véhicules aériens sans pilote (UAV), souvent appelés drones, trouvent de nombreuses applications dans la vie. Les applications de drones nécessitent plusieurs indicateurs de performance essentiels tels que la couverture, la force du signal, la latence et la mobilité dans des scénarios. Par conséquent, l'utilisation des communications sans fil dans les drones est essentielle pour répondre à toutes les exigences. En raison des connexions au haut débit entre les drones et les utilisateurs pour transférer des données de haut volume à haute résolution, les dernières générations sans fil, comme la norme LTE, sont privilégiées. Il est évident que l'intégration de blocs de radiofréquence (RF) est essentielle pour construire un système sur puce et réduire la taille des drones. Dans ce contexte, cette thèse vise à développer un amplificateur de puissance (PA) innovant avec haute performance reconfigurable entièrement intégré qui adresse les différents besoins imposés par le standard LTE à utiliser dans les applications des UAV. Le PA entièrement intégré en CMOS 65 nm a pour objectif de fournir une puissance de sortie élevée et résoudre le compromis entre la linéarité et l’efficacité. Un transformateur à quatre enroulements est implémenté pour configurer le fonctionnement en multi modes du PA. La technique « segmented bias » permet au PA d’améliorer la linéarité. Le PA obtient non seulement des performances élevées en RF, mais démontre également un potentiel pour l'adopter dans la bande 5G inférieure. / Unmanned aerial vehicles (UAVs), often known as drones, have been finding numerous applications in life. Drones applications need several essential performance indicators such as coverage, signal strength, latency, and mobility under scenarios. Therefore, the use of wireless communications in drones is critical to address all requirements. Because of high-speed connections between drones and users to transfer high-resolution high-volume data, latest wireless generations, namely the LTE standard, are privileged. It is straightforward that the integration of RF blocks is essential to build a system-on-chip and shrink the size of drones. To answer the above question, this thesis aims to develop a fully integrated reconfigurable high-performance innovated PA that supports 4G LTE standard to be used in UAVs’ applications. The fully integrated 65-nm CMOS power amplifier (PA) provides a watt-level output power, addresses the linearity/efficiency trade-off. A four-winding transformer is implemented to configure the multi-mode operation of the PA. The “segmented bias” technique allows the PA to increase the linearity. The PA not only obtains high radiofrequency performances but also demonstrates a potential to adopt it design in the lower 5G band.

Le travail présenté dans ce manuscrit a pour objet l’étude et le développement d’un banc de caractérisation généraliste appliqué à l’extraction du modèle comportemental d’amplificateur TPM-NIM (Two-Path Memory Nonlinear Integral). Ce modèle qui dispose d’une des architectures les plus abouties au laboratoire XLIM requiert une instrumentation microonde haut de gamme, très onéreuse, hors de portée de la majorité des concepteurs pour sa mise en œuvre expérimentale. L’objectif est donc de proposer des principes de mesure originaux permettant d’identifier le modèle TPM-NIM avec une instrumentation standard. Dans ces travaux, deux bancs sont présentés : tout d’abord, un banc de caractérisation développé autour d’une instrumentation de pointe disposant des meilleures propriétés pour extraire le modèle. Puis, un banc construit autour d’une instrumentation standard mais incluant des méthodes de traitement et de mesure novatrices. Ces deux bancs ont été utilisés avec plusieurs véhicules de tests et il ressort que le second permet de diminuer le bruit des mesures de phase tout en réduisant le coût total des équipements. Enfin, une dernière partie est consacrée à la comparaison du modèle TPM-NIM avec deux modèles comportementaux classiques mettant en avant sa polyvalence. / The work presented in this manuscript is devoted to the study and development of a general characterization bench applied to the extraction of the TPM-NIM (Two-Path Memory Nonlinear Integral) amplifier behavioral model. This model, has one of the most advanced architectures at the XLIM laboratory. It requires a high-end microwave instrumentation, overpriced and beyond reach for most of the designers for its experimental implementation. The aim is to propose some original measurements principles allowing the TPM-NIM model’s identification with a standard instrumentation. Two benches are presented in these works : firstly, a characterization bench, developed using a high performance instrumentation with the best properties to extract the model. Then, a bench, built with a standard instrumentation but through innovative processing and measurement methods. These two benches have been used with several test vehicles and it appears that the second one decreases the noise of phase measurements while reducing the equipment’s total cost. Finally, a last part is dedicated to the comparison of the TPM-NIM model with two classic behavioral models by emphasizing its versatility.

<p>In this thesis, a parsimoniously parameterized digital predistorter is derived for linearization of the IQ modulation mismatch and the amplifier imperfection in the signal generator [1]. It is shown that the resulting predistorter is linear in its parameters, and thus they may be estimated by the method of least-squares. Spectrally pure signals are an indispensable requirement when the signal generator is to be used as part of a test bed. Due to the non-linear characteristic of the IQ modulator and power amplifier, distortion will be present at the output of the signal generator. The device under test was the IQ modulation mismatch and power amplifier deficiencies in the signal generator.</p><p>In [2], the dynamic range of low-cost signal generators are improved by employing model based digital pre-distortion and the designed predistorter seems to give some improvement of the dynamic range of the signal generator.</p><p>The goal of this project is to implement and verify the theory parts [1] using data program (Matlab) to improve the dynamic range of the signal generator. The design digital pre-distortion that is implemented in software so that the dynamic range of the signal generator output after predistortion is superior to that of the output prior to it. In this project, we have observed numerical<strong> </strong>problems in the proposed theory and we have found other methods to solve the problem.</p><p>The polynomial model is commonly used in power amplifier modeling and predistorter design. However, the conventional polynomial model exhibits numerical instabilities when higher order terms are included, we have used the conventional and orthogonal polynomial models. The result shows that the orthogonal polynomial model generally yield better power amplifier modeling accuracy as well as predistortion linearization performance then the conventional polynomial model.</p>

<p>The purpose of this master thesis was to study if the drain efficiency of power amplifiers can be maintained at power back off using a technique called load modulation.</p><p>The amplifier classes studied are E, F and D-1. The target figure was to obtain a 10 to 12 dB dynamic range of amplitude with reasonable efficiency. Studies of power amplifiers have been made to understand how power is generated. Several different load modulation networks have been evaluated. Attempts to derive design equations for the modulation networks have also been done.</p><p>The thesis work was carried out with simulations in ADS 2006. As active devices commercially available bare-die transistor models have been used. The power rating of the dies are 15 W.</p><p>A dynamic range of amplitude of over 15 dB has been achieved with drain efficiency greater than 60 percent. The peak output power is in the 40 – 45 dBm range.</p>

This dissertation presents the design and implementation of circuits and transceivers in CMOS technology to enable many new millimeter-wave applications. A simple approach is presented for accurately modeling the millimeter-wave characteristics of transistors that are not fully captured by contemporary parasitic extraction techniques. Next, the integration of a low-power 60-GHz CMOS on-off keying (OOK) receiver in 90-nm CMOS for use in multi-gigabit per second wireless communications is demonstrated. The use of non-coherent OOK demodulation by a novel demodulator enabled a data throughput of 3.5 Gbps and resulted in the lowest power budget (31pJ/bit) for integrated 60-GHz CMOS OOK receivers at the time of publication. Also presented is the design of a high-power, high-efficiency 45-GHz VCO in 45-nm SOI CMOS. The design is a class-E power amplifier placed in a positive feedback configuration. This circuit achieves the highest reported output power (8.2 dBm) and efficiency (15.64%) to date for monolithic silicon-based millimeter-wave VCOs. Results are provided for the standalone VCO as well as after packaging in a liquid crystal polymer (LCP) substrate. In addition, a high-power high-efficiency (5.2 dBm/6.1%) injection locked oscillator is presented. Finally, the design of a 2-channel 45-GHz vector modulator in 45-nm SOI CMOS for LINC transmitters is presented. A zero-power passive IQ generation network and a low-power Gilbert cell modulator are used to enable continuous 360° vector generation. The IC is packaged with a Wilkinson power combiner on LCP and driven by external DACs to demonstrate the first ever 16-QAM generated by outphasing modulation in CMOS in the Q-band.

The development of multi-standard wireless communication systems with low cost and high integration is continuously requested and accompanied by the explosive growth of the wireless communication market. Although CMOS technology can provide most building blocks in RF transceivers, the implementation of CMOS RF power amplifiers is still a challenging task. The objective of this research is to develop design techniques to implement fully-integrated multi-mode power amplifiers using CMOS technology. In this dissertation, a load modulation technique with tunable matching networks and a pre-distortion technique in a multi-stage PA are proposed to support multi-communication standards with a single PA. A fully-integrated dual-mode GSM/EDGE PA was designed and implemented in a 0.18 um CMOS technology to achieve high output power for the GSM application and high linearity for the EDGE application. With the suggested power amplifier design techniques, fully-integrated PAs have been successfully demonstrated in GSM and EDGE applications. In Addition to the proposed techniques, a body-switched cascode PA core is also proposed to utilize a single PA in multi-mode applications without hurting the performance. With the proposed techniques, a fully-integrated multi-mode PA has been implemented in a 0.18 um CMOS technology, and the power amplifier has been demonstrated successfully for GSM/EDGE/WCDMA applications. In conclusion, the research in this dissertation provides CMOS RF power amplifier solutions for multiple standards in mobile wireless communications with low cost and high integration.

Designing CMOS linear transmitter front-end, specially the power amplifiers (PAs), in multi-band wireless transceivers is a major challenge for the single-chip integration of a CMOS radio. In some of the linear PA systems, for example, polar- or predistortion-PA system, amplitude and phase control circuits are used to suppress the distortion produces by the PA core. The requirements of these controlling circuits are much different from their conventional role in a receiver or a phase array system. In this dissertation, the special design issues will be addressed, and the circuit topologies of the amplitude and phase controllers will be proposed. In attempt to control the high-power input signal of a PA system, a highly linear variable attenuator with adaptive body biasing is first introduced. The voltage swing on the signal path is intentionally coupled to the body terminal of the triple-well NMOS devices to reduce their impedance variation. The fabricated variable attenuator shows a significant improvement on linearity as compared to previous CMOS works. The results of this research are then used to build a variable gain amplifier for linear PA systems that requires gain of its amplitude tuning circuits. Different from the conventional attenuator-based VGAs, the high linearity of the suggested attenuator allows it to be put after the gain stage in the presented VGA topology. This arrangement along with the current boosting technique gives the VGA a better noise performance while having a linear-in-dB tuning curve and better worst-case linearity. The following part of the dissertation is about a compact, linear-in-degree tuned variable phase shifter as the phase controller in the PA system. This design uses a modified RC poly-phase filter to produce a set of an orthogonal phase vectors with smaller loss. A specially designed control circuit combines these vectors and generates an output signal with different phases, while having very small gain mismatches at different phase setting. The proposed amplitude and phase control circuits are then verified with a system level analysis. The results show that the proposed designs successfully reduce the non-linear effect of a wireless transmitter.

Aquesta Tesi Doctoral se centra en el disseny d'un nou linealitzador de Predistorsió Digital (Digital Predistortion - DPD) capaç de compensar la dinàmica i els efectes no lineals introduïts pels Amplificadors de Potència (Power Amplifiers - PAs). Un dels trets més rellevants d'aquest nou predistorsionador digital i adaptatiu consisteix en ser deduïble a partir d'un model de PA anomenat Nonlinear Auto-Regressive Moving Average (NARMA). A més, la seva arquitectura multi-LUT (multi-Taula) permet la implementació en un dispositiu Field Programmable Gate Array (FPGA).La funció de predistorsió es realitza en banda base, per tant, és independent de la banda freqüencial on es durà a terme l'amplificació del senyal de RF, el que pot resultar útil si tenim en compte escenaris multibanda o reconfigurables. D'altra banda, el fet que aquest DPD tingui en compte els efectes de memòria introduïts pel PA, representa una clara millora de les prestacions aconseguides per un simple DPD sense memòria. En comparació amb d'altres DPDs basats en models més computacionalment complexos, com és el cas de les xarxes neuronals amb memòria (Time-Delayed Neural Networks - TDNN), la estructura recursiva del DPD proposat permet reduir el nombre de LUTs necessàries per compensar els efectes de memòria del PA. A més, la seva estructura multi-LUT permet l'escalabilitat, és a dir, activar or desactivar les LUTs que formen el DPD en funció de la dinàmica que presenti el PA.En una primera aproximació al disseny del DPD, és necessari identificar el model NARMA del PA. Un dels majors avantatges que presenta el model NARMA és la seva capacitat per trobar un compromís entre la fidelitat en l'estimació del PA i la complexitat computacional introduïda. Per reforçar aquest compromís, l' ús d'algoritmes heurístics de cerca, com són el Simulated Annealing o els Genetic Algorithms, s'utilitzen per trobar els retards que millor caracteritzen la memòria del PA i per tant, permeten la reducció del nombre de coeficients necessaris per caracteritzar-la. Tot i així, la naturalesa recursiva del model NARMA comporta que, de cara a garantir l'estabilitat final del DPD, cal dur a terme un estudi previ sobre l'estabilitat del model.Una vegada s'ha obtingut el model NARMA del PA i s'ha verificat l'estabilitat d'aquest, es procedeix a l'obtenció de la funció de predistorsió a través del mètode d'identificació predictiu. Aquest mètode es basa en la continua identificació del model NARMA del PA i posteriorment, a partir del model obtingut, es força al PA perquè es comporti de manera lineal. Per poder implementar la funció de predistorsió en la FPGA, cal primer expressar-la en forma de combinacions en paral·lel i cascada de les anomenades Cel·les Bàsiques de Predistorsió (BPCs), que són les unitats fonamentals que composen el DPD. Una BPC està formada per un multiplicador complex, un port RAM dual que actua com a LUT (taula de registres) i un calculador d'adreces. Les LUTs s'omplen tenint en compte una distribució uniforme dels continguts i l'indexat d'aquestes es duu a terme mitjançant el mòdul de l'envoltant del senyal. Finalment, l'adaptació del DPD consisteix en monitoritzar els senyals d'entrada i sortida del PA i anar duent a terme actualitzacions periòdiques del contingut de les LUTs que formen les BPCs. El procés d'adaptació del contingut de les LUTs es pot dur a terme en la mateixa FPGA encarregada de fer la funció de predistorsió, o de manera alternativa, pot ser duta a terme per un dispositiu extern (com per exemple un DSP - Digital Signal Processor) en una escala de temps més relaxada. Per validar l'exposició teòrica i provar el bon funcionalment del DPD proposat en aquesta Tesi, es proporcionen resultats tant de simulació com experimentals que reflecteixen els objectius assolits en la linealització del PA. A més, certes qüestions derivades de la implementació pràctica, tals com el consum de potència o la eficiència del PA, són també tractades amb detall. / This Ph.D. thesis addresses the design of a new Digital Predistortion (DPD) linearizer capable to compensate the unwanted nonlinear and dynamic behavior of power amplifiers (PAs). The distinctive characteristic of this new adaptive DPD is its deduction from a Nonlinear Auto Regressive Moving Average (NARMA) PA behavioral model and its particular multi look-up table (LUT) architecture that allows its implementation in a Field Programmable Gate Array (FPGA) device.The DPD linearizer presented in this thesis operates at baseband, thus becoming independent on the final RF frequency band and making it suitable for multiband or reconfigurable scenarios. Moreover, the proposed DPD takes into account PA memory effects compensation which representsan step forward in overcoming classical limitations of memoryless predistorters. Compared to more computational complex DPDs with dynamic compensation, such Time-Delayed Neural Networks (TDNN), this new DPD takes advantage of the recursive nature of the NARMA structure to relax the number of LUTs required to compensate memory effects in PAs. Furthermore, its parallel multi-LUT architecture is scalable, that is, permits enabling or disabling the contribution of specific LUTs depending on the dynamics presented by a particular PA.In a first approach, it is necessary to identify a NARMA PA behavioral model. The extraction of PA behavioral models for DPD linearization purposes is carried out by means of input and output complex envelope signal observations. One of the major advantages of the NARMA structure regards its capacity to deal with the existing trade-off between computational complexity and accuracy in PA behavioral modeling. To reinforce this compromise, heuristic search algorithms such the Simulated Annealing or Genetic Algorithms are utilized to find the best sparse delays that permit accurately reproducing the PA nonlinear dynamic behavior. However, due to the recursive nature of the NARMA model, an stability test becomes a previous requisite before advancing towards DPD linearization.Once the PA model is identified and its stability verified, the DPD function is extracted applying a predictive predistortion method. This identification method relies just on the PA NARMA model and consists in adaptively forcing the PA to behave as a linear device. Focusing in the DPD implementation, it is possible to map the predistortion function in a FPGA, but to fulfill this objective it is first necessary to express the predistortion function as a combined set of LUTs.In order to store the DPD function into a FPGA, it has to be stated in terms of parallel and cascade Basic Predistortion Cells (BPCs), which are the fundamental building blocks of the NARMA based DPD. A BPC is formed by a complex multiplier, a dual port RAM memory block acting as LUT and an address calculator. The LUT contents are filled following an uniform spacing procedure and its indexing is performed with the amplitude (modulus) of the signal's envelope.Finally, the DPD adaptation consists in monitoring the input-output data and performing frequent updates of the LUT contents that conform the BPCs. This adaptation process can be carried out in the same FPGA in charge of performing the DPD function, or alternatively can be performed by an external device (i.e. a DSP device) in a different time-scale than real-time operation.To support all the theoretical design and to prove the linearization performance achieved by this new DPD, simulation and experimental results are provided. Moreover, some issues derived from practical experimentation, such as power consumption and efficiency, are also reported and discussed within this thesis.