The aim of the master´s thesis is to create a high-frequency amplifier with switching power amplifier classes among classes A, B, C with output power of 10 W. The amplifier operates at frequency from 3.5 MHz to 14 MHz. Master´s thesis includes also theoretical analysis, design of lowpass filter and amplifiers and their simulation, mechanical realization and measured parameters of the amplifier.

This diploma thesis is focused on design of high frequency power amplifiers in UHF band, specifically at 435 MHz. Amplifiers are designed in different classes of operation. The thesis deals with the comparison of main parameters in each class of operation, the most important parameter is effeciency. The amplifying part is unipolar transistor which is working in Single-stage mode. The results were simulated in Advanced Design Systems Software.

<div>Radio Frequency Power Amplifiers (PA) are essential components of wireless systems and nonlinear in a permanent way. So, high efficiency and linearity at a time are imperative for power amplifiers. However, it is hard to obtain because high efficiency Power Amplifiers are nonlinear and linear Power Amplifiers have poor efficiency. To meet both linearity and efficiency, the linearization techniques such as Digital Predistortion (DPD) has arrested the most attention in industrial and academic sectors due to provide a compromising data between efficiency and linearity. This thesis proposed on digital predistortion techniques to control nonlinear distortion in radio frequency transmitters. </div><div>By using predistortion technique, both linearity and efficiency can obtain. In this thesis a new generic Saleh model for use in memoryless nonlinear power amplifier (PA) behavioral modelling is used. The results are obtained by simulations through MATLAB and experiments. We explore the baseband 13.56 MHz Power Amplifier input and output relationships and reveal that they apparent differently when the Power Amplifier shows long-term, short-term or memory less effects. We derive a SIMULINK based static DPD design depend on a memory polynomial. A polynomial improves both the non-linearity and memory effects in the Power Amplifier. As PA characteristics differs from time to time and operating conditions, we developed a model to calculate the effectiveness of DPD. We extended our static DPD design model into an adaptive DPD test bench using Indirect Learning Architecture (ILA) to implement adaptive DPD which composed of DPD subsystem and DPD coefficient calculation. By this technique, the output of PA achieves linear, amplitude and phase distortions are eliminated, and spectral regrowth is prevented. </div><div>The advanced linearity performance executed through the strategies and methods evolved on this thesis can allow a higher usage of the capability overall performance of existing and emerging exceptionally performance PAs, and therefore an anticipated to have an effect in future wireless communication systems. </div>

While a lot of time and resources have been placed into transceiver design, due to the pace of a conventional engineering design process, the design of a power amplifier is often completed using scattered resources; and not always in a methodological manner, and frequently even by an iterative trial and error process. In this thesis, a research question is posed which enables for the investigation of the possibility of streamlining the design flow for power amplifiers. After thorough theoretical investigation of existing power amplifier design methods and modelling, inductors inevitably used in power amplifier design were identified as a major drawback to efficient design, even when examples of inductors are packaged in design HIT-Kits. The main contribution of this research is engineering of an inductor design process, which in-effect contributes towards enhancing conventional power amplifiers. This inductance search algorithm finds the highest quality factor configuration of a single-layer square spiral inductor within certain tolerance using formulae for inductance and inductor parasitics of traditional single-π inductor model. Further contribution of this research is a set of algorithms for the complete design of switch-mode (Class-E and Class-F) power amplifiers and their output matching networks. These algorithms make use of classic deterministic design equations so that values of parasitic components can be calculated given input parameters, including required output power, centre frequency, supply voltage, and choice of class of operation. The hypothesis was satisfied for SiGe BiCMOS S35 process from Austriamicrosystems (AMS). Several metal-3 and thick-metal inductors were designed using the abovementioned algorithm and compared with experimental results provided by AMS. Correspondence was established between designed, experimental and EM simulation results, enabling qualification of inductors other than those with experimental results available from AMS by means of EM simulations with average relative errors of 3.7% for inductors and 21% for the Q factor at its peak frequency. For a wide range of inductors, Q-factors of 10 and more were readily experienced. Furthermore, simulations were performed for number of Class-E and Class-F amplifier configurations with HBTs with ft greater than 60 GHz and total emitter area of 96 μm² as driving transistors to complete the hypothesis testing. For the complete PA system design (including inductors), simulations showed that switch-mode power amplifiers for 50 Ω load at 2.4 GHz centre frequency can be designed using the streamlined method of this research for the output power of about 6 dB less than aimed. This power loss was expected, since it can be attributed to non-ideal properties of the driving transistor and Q-factor limitations of the integrated inductors, assumptions which the computations of the routine were based on. Although these results were obtained for a single micro-process, it was further speculated that outcome of this research has a general contribution, since streamlined method can be used with a much wider range of CMOS and BiCMOS processes, when low-gigahertz operating power amplifiers are needed. This theory was confirmed by means of simulation and fabrication in 180 nm BiCMOS process from IBM, results of which were also presented. The work presented here, was combined with algorithms for SPICE netlist extraction and the spiral inductor layout extraction (CIF and GDSII formats). This secondary research outcome further contributed to the completeness of the design flow. All the above features showed that the routine developed here is substantially better than cut-and-try methods for design of power amplifiers found in the existing body of knowledge. / Thesis (PhD(Eng))--University of Pretoria, 2011. / Electrical, Electronic and Computer Engineering / unrestricted

With the wireless technology evolving quickly, so does the demand of speed and efficiency. This makes the companies look for new and better ways to improve the current systems. One way of improving the present systems would be to employ Full Duplex Technology. In recent years the standard has been Half duplex technology with either Time Division Duplexing (TDD) or Frequency Division Duplexing (FDD). The drawback of TDD is that the signals is put in different time slots, meaning if many signals is to be transmitted at the same time there will be a delay. For FDD the signals are sent at different frequencies. This takes up a lot of space in the spectral domain. Full Duplex Technology has the potential to double the spectral efficiency with it'spower to transmit and receive signals simultaneously at the same frequency. The main challenge with Full Duplex (FD) is the leaking Self-Interference (SI) from the transmitter to the receiver. Different methods can be used to suppress the SI in both the digital and the analog domain. Typically the Self-Interference Cancellation (SIC) is split into three parts. The passive Radio Frequency (RF) SIC, which suppresses the signal using for example. antenna separation, antenna polarization or a circulator. The active analog RF cancellation which could for example use a multi-tap analog least mean square adaptive and finally the Digital passband SIC, that is addressed in this thesis. The cancellation in the RF domain needs to suppress enough for the Low Noise Amplifier (LNA) and the Analog to Digital Converter (ADC) to not saturate. The Digital SIC should optimally suppress the signal to the noise floor to be able to demodulate the received signal. In this thesis modelling and reconstruction of the SI signal has been done. An attempt to model the non-linearities from the Power Amplifier (PA), the imbalance from the IQ-mixer and the effects of the circulator has been done to as correctly as possible comply to the real signal distortions. Simulations using experimental data provided by Syntronic SRD was used to evaluate the cancellation for Recursive Least Square (RLS), Ordinary Least Square (OLS) and Normalized Least Mean Square (NLMS) algorithms. The simulations shows that a cancellation of over 45dB within the bandwidth can be achieved using digital cancellation in the baseband. The result shows the importance of having a weakly nonlinear transmit signal to achieve a better performance using FD. It was showed that the linear model shows significantly worse results incomparison to the Generalized Memory Polynomial (GMP) and Memory Polynomial (MP). The MP and GMP model achieve similar results in the weakly non-linear cases but the GMP outperforms the MP model in strongly non-linear cases.

Due to continued device dimensions scaling, CMOS transistors in the nanometer regime have resulted in major reliability and variability challenges. Reliability issues such as channel hot electron injection, gate dielectric breakdown, and negative bias temperature instability (NBTI) need to be accounted for in the design of robust RF circuits. In addition, process variations in the nanoscale CMOS transistors are another major concern in today‟s circuits design. An adaptive gate-source biasing scheme to improve the RF circuit reliability is presented in this work. The adaptive method automatically adjusts the gate-source voltage to compensate the reduction in drain current subjected to various device reliability mechanisms. A class-AB RF power amplifier shows that the use of a source resistance makes the power-added efficiency robust against threshold voltage and mobility variations, while the use of a source inductance is more reliable for the input third-order intercept point. A RF power amplifier with adaptive gate biasing is proposed to improve the circuit device reliability degradation and process variation. The performances of the power amplifier with adaptive gate biasing are compared with those of the power amplifier without adaptive gate biasing technique. The adaptive gate biasing makes the power amplifier more resilient to process variations as well as the device aging such as mobility and threshold voltage degradation. Injection locked voltage-controlled oscillators (VCOs) have been examined. The VCOs are implemented using TSMC 0.18 µm mixed-signal CMOS technology. The injection locked oscillators have improved phase noise performance than free running oscillators. iv A differential Clapp-VCO has been designed and fabricated for the evaluation of hot electron reliability. The differential Clapp-VCO is formed using cross-coupled nMOS transistors, on-chip transformers/inductors, and voltage-controlled capacitors. The experimental data demonstrate that the hot carrier damage increases the oscillation frequency and degrades the phase noise of Clapp-VCO. A p-channel transistor only VCO has been designed for low phase noise. The simulation results show that the phase noise degrades after NBTI stress at elevated temperature. This is due to increased interface states after NBTI stress. The process variability has also been evaluated.

This thesis provides a description of the analysis, design, and tests of an X-band RF Transmitter communication system for small satellites. X-band transmitter systems are becoming popular in the upcoming deep space missions. Most of the deep-space ground stations have been using X-band frequencies to receive or transmit signals. The X-band (<10 GHz) can offer lower atmospheric losses and up to a couple of Mbps data rates for multiple satellite operations. Nowadays, many small satellites have been using frequency bands such as VHF, UHF, L, and S-band frequencies for communication. From deep space to the ground station, the low-frequency ranges are inadequate in providing Mbps level data rates and enough bandwidth for deep space missions. The main focus of this thesis was the development of the subsystems such as gain block amplifier, Mixer, Bandpass Filter, and RF power amplifier. The subsystems were designed separately, then they were connected together to perform an end-to-end system test. One of the thesis aims is to design a manageable, power-efficient, and especially cost-effective X-band RF transmitter system. We presented a transmitter system demonstration in this thesis that can also be used in other orbits such as LEO, MEO, or GEO. Additionally, we presented a whole transceiver architecture. However, we focused on specifically designing transmitter subsystems. Initially, the top-level transmitter system objectives were determined. Then, the link budget was calculated. In the next stage, the RF front-end components were determined. Moreover, we simulated a transmitter system to foresee the output power, EVM, LO and IF frequency requirements, harmonics and spurious signals, cascaded gain and noise figure, and phase noise. From the calculated link budget, we were able to close the link by obtaining a 3 dB link margin. At the end of this calculation, we successfully obtained 1.45 Mbps for uplink data rate and 3.05 Kbps downlink rate. We used modulated signal to evaluate EVM. From the simulated transmitter chain, the output EVM was obtained as 1.456% RMS. From the filter board, we obtained an 8.5 dB insertion loss at 8.45 GHz. From the Mixer board, we’ve got 10 dB conversion loss and greater than 20 dB isolation between LO-RF ports. From the gain block amplifier board, we obtained a +9 dB gain at 8.45 GHz. The bandpass filter, mixer, and gain block amplifier boards were designed by using FR-4 dielectric material. We also designed a 5 W RF power amplifier board. From this board, we successfully obtained +37 dBm output at bias current at 200 mA. We reached almost 30% Power-added efficiency (PAE). In the end, we connected all the subsystems together using male-to-male SMA connectors to observe output by using a spectrum analyzer. We obtained transmitter output as +10.67 dBm at 8.45 GHz with a -10.7 dBm input power level. One benefit of this thesis is that its content has inspired other students in the department to develop similar subsystems. The other benefit of this work might be to inspire the way for next-generation X-band communication systems for use in small satellites, such as for deep space missions. This thesis might also be a reference source for institutions with a limited budget to develop a cost-effective satellite communication subsystem and contribute to space exploration for their educational and research objectives.

Yes / As 5th Generation research reaches the twilight, the research community must go beyond 5G and look towards the 2030 connectivity landscape, namely 6G. In this context, this work takes a step towards the 6G vision by proposing a next generation communication platform, which aims to extend the rigid coverage area of fixed deployment networks by considering virtual mobile small cells (MSC) that are created on demand. Relying on emerging computing paradigms such as NFV (Network Function Virtualization) and SDN (Software Defined Networking), these cells can harness radio and networking capability locally reducing protocol signalling latency and overhead. These MSCs constitute an intelligent pool of networking resources that can collaborate to form a wireless network of MSCs providing a communication platform for localized, ubiquitous and reliable connectivity. The technology enablers for implementing the MSC concept are also addressed in terms of virtualization, lightweight wireless security, and energy efficient RF. The benefits of the MSC architecture towards reliable and efficient cell-offloading are demonstrated as a use-case. / This project has received funding from the European Union's H2020 research and innovation program under grant agreement H2020-MCSAITN- 2016-SECRET 722424 [2].

No description available.

The objective of this research work is to investigate, design and measurement of a digital predistortion linearizer that is able to compensate the dynamic nonlinear distortion of a High Power Amplifier (PA). The effectiveness of the proposed baseband predistorter (PD) on the performance of a WLAN OFDM transmitter utilizing a nonlinear PA with memory effect is observed and discussed. For this purpose, a 10W Class-A/B power amplifier with a gain of 22 dB, operated over the 3.5 GHz frequency band was designed and implemented. The proposed baseband PD is independent of the operating RF frequency and can be used in multiband applications. Its operation is based on the Hammerstein system, taking into account PA memory effect compensation, and demonstrates a noticeable improvement compared to memoryless predistorters. Different types of modelling procedures and linearizers were introduced and investigated, in which accurate behavioural models of Radio Frequency (RF) PAs exhibiting linear and nonlinear memory effects were presented and considered, based on the Wiener approach employing a linear parametric estimation technique. Three new linear methods of parameter estimation were investigated, with the aim of reducing the complexity of the required filtering process in linear memory compensation. Moreover, an improved wiener model is represented to include the nonlinear memory effect in the system. The validity of the PA modelling approaches and predistortion techniques for compensation of nonlinearities of a PA were verified by several tests and measurements. The approaches presented, based on the Wiener system, have the capacity to deal with the existing trade-off between accuracy and convergence speed compared to more computationally complex behavioural modelling algorithms considering memory effects, such as those based on Volterra series and Neural Networks. In addition, nonlinear and linear crosstalks introduced by the power amplifier nonlinear behaviour and antennas mutual coupling due to the compact size of a MIMO OFDM transmitter have been investigated.