abstract: Complex electronic systems include multiple power domains and drastically varying dynamic power consumption patterns, requiring the use of multiple power conversion and regulation units. High frequency switching converters have been gaining prominence in the DC-DC converter market due to smaller solution size (higher power density) and higher efficiency. As the filter components become smaller in value and size, they are unfortunately also subject to higher process variations and worse degradation profiles jeopardizing stable operation of the power supply. This dissertation presents techniques to track changes in the dynamic loop characteristics of the DC-DC converters without disturbing the normal mode of operation. A digital pseudo-noise (PN) based stimulus is used to excite the DC-DC system at various circuit nodes to calculate the corresponding closed-loop impulse response. The test signal energy is spread over a wide bandwidth and the signal analysis is achieved by correlating the PN input sequence with the disturbed output generated, thereby accumulating the desired behavior over time. A mixed-signal cross-correlation circuit is used to derive on-chip impulse responses, with smaller memory and lower computational requirement in comparison to a digital correlator approach. Model reference based parametric and non-parametric techniques are discussed to analyze the impulse response results in both time and frequency domain. The proposed techniques can extract open-loop phase margin and closed-loop unity-gain frequency within 5.2% and 4.1% error, respectively, for the load current range of 30-200mA. Converter parameters such as natural frequency (ω_n ), quality factor (Q), and center frequency (ω_c ) can be estimated within 3.6%, 4.7%, and 3.8% error respectively, over load inductance of 4.7-10.3µH, and filter capacitance of 200-400nF. A 5-MHz switching frequency, 5-8.125V input voltage range, voltage-mode controlled DC-DC buck converter is designed for the proposed built-in self-test (BIST) analysis. The converter output voltage range is 3.3-5V and the supported maximum load current is 450mA. The peak efficiency of the converter is 87.93%. The proposed converter is fabricated on a 0.6µm 6-layer-metal Silicon-On-Insulator (SOI) technology with a die area of 9mm^2 . The area impact due to the system identification blocks including related I/O structures is 3.8% and they consume 530µA quiescent current during operation. / Dissertation/Thesis / Doctoral Dissertation Electrical Engineering 2017

La compatibilité électromagnétique (CEM) est l’une des contraintes majeures de la conception des structures de l’électronique de puissance. Pour le cas des convertisseurs statiques, la commutation des semi-conducteurs et leurs interactions avec les éléments parasites liés à l’environnement sont la source principale des perturbations conduites. Cette interaction ne cesse d’augmenter notamment avec l’industrialisation des nouvelles générations de semi-conducteurs à grand gap qui deviennent de plus en plus impressionnantes grâces à leurs faibles pertes en commutation et à leur rapidité croissante. Malheureusement, l’étude de ces perturbations est souvent considérée comme le dernier obstacle à la commercialisation et elle n’est pas prise comme contrainte de conception. L’estimation a priori de ces perturbations par la simulation peut permettre un gain considérable tant sur le plan économique que sur le temps de traitement. Dans ce mémoire, nous mettons l’accent sur les modèles de composants semi-conducteurs et leurs effets sur les perturbations conduites dans les convertisseurs statiques. Cette étude mettra aussi en évidence les problèmes liés aux simulations temporelles ou fréquentielles et l’utilité de chacune. Ensuite, nous proposons des modèles pour le MOSFET et pour la diode Shottky en technologie carbure de silicium et nous analysons l’influence de leurs paramètres sur les perturbations conduites dans un circuit de hacheur. Nous exposons aussi une approche permettant d’obtenir des temps de simulation plus raisonnables en introduisant le principe de contrôle des signaux parasites et des cycles de fonctionnement. Finalement, nous introduisons une nouvelle méthode de description des commutations par des sources équivalentes. Nous montrons qu’il est possible à partir de l’étude de la loi de commande de proposer une méthode de synthèse d’une cellule de commutation permettant de reconstruire ses grandeurs électriques de sortie. / Electromagnetic compatibility (EMC) is one of the major constraints involved in the design of power electronics structures. In the case of static power converters, the switching of semiconductors and their interactions with the parasitic elements related to the environment are the main source of conducted disturbances. This interaction is increasing especially with the industrialization of new generations of wide band gap semiconductors that become increasingly impressive thanks to their low switching losses and their rapidity. Unfortunately, the study of the disturbances is often considered as the last obstacle to the marketing and it is not taken as a design constraint. An early estimation of these disturbances by simulation can provide a reduction in processing time and a considerable economic gain. In this manuscript, we focus on semiconductors models and their effects on conducted interference in static converters. This study will also reveal problems related to time or frequency simulations and usefulness of each one. Then, we propose models for silicon-carbide MOSFET and Schottky diode and we analyze the influence of their parameters on the conducted disturbances in a chopper circuit. We also expose an approach to obtain more reasonable simulation time by controlling parasitic signals and operating cycles. Finally, we introduce a new method to describe switching’s by using equivalent sources. We show that by studying the command law, it is possible to propose a synthesizing method of a switching cell able to rebuild its electrical outputs.

Les Alimentations Sans Interruption sont utilisées pour assurer la qualité et la continuité de l'énergie fournie aux charges sensibles. Basées sur deux conversions d'énergie électrique, ces alimentations supportent en permanence la puissance de la charge, rendant crucial leur rendement. Cette thèse a exploré différentes voies d'amélioration du rendement du commutateur assurant la conversion : le choix des composants semi-conducteurs, celui de la structure de conversion et du mode de fonctionnement. Le filtrage a été pris en compte sans faire l'objet d'investigations poussées. La méthode d'estimation du rendement, exploitant des données des constructeurs, a permis de quantifier l'impact et les limites de chaque voie explorée. Plusieurs structures de conversion multi-niveaux en commutation douce ont été développées, utilisant un pôle résonant. Enfin, plusieurs expérimentations ont validé les modèles utilisés, le concept du pôle résonant et la réalisation d'un prototype fonctionnel de 125 kVA. / The Uninterruptible Power Supplies (UPS) are used to supply such critical load with a high level of quality and continuity. The topology based on two consecutive converters providing permanently the whole power leading to made the efficiency a key point of the UPS. To improve the efficiency of the semi-conductors part, three ways have been studied in this thesis: The semi-conductor area, the topology of the converter and the switching mode. The filter losses have been taken into account based on the state of the art. The estimation of the efficiency, based on the datasheet from manufacturers, allow quantifying each way. Some soft-switching multi-level topologies have been developped and patented. Finally, experimentations have been made to asses the relevance of the models, the working of new topologies and the efficiency of the proposed 125 kVA UPS.

This thesis presents the simulation, design, and hardware implementation of a modified multiphase boost converter. Converter design must consider noise imposed on input and output nodes which connect to and influence the operation of other devices. Excessive noise introduces EMI which can damage sensitive circuits or impede their operation. High ripple current degrades battery lifetime and reduces operating efficiency in connected systems such as PV arrays. Converters with high ripple current also experience greater peak conduction loss and require larger components. A two-phase implementation of a modified boost converter demonstrates the input current filtering benefits of the modified topology with increased power capacity. In a 12V to 19V 95W design, the modified multiphase design exhibits a reduced input current ripple of 1.103% compared to the 9.096% of the standard multiphase design while imposing minimal detriment to overall converter efficiency. The modified topology uses two inductors and one feedback capacitance per phase. Larger value inductors generally exhibit lower current ratings as well as larger size. The split inductance of the modified multiphase topology can be designed for occupation of less total volume than the single inductance of the standard multiphase topology.

Traditional electric vehicle and stationary battery systems use series-connected battery packs that employ centralized battery management and power processing architecture. Though, these systems meet the basic safety and power requirements with a simple hard- ware structure, the approach results in a battery pack that is energy and power limited by weak cells throughout life and most importantly at end-of-life. The applications of battery systems can benefit significantly from modular, scalable battery systems capable of advanced cell balancing, efficient power processing, and cost gains via reuse beyond first-use application. The design of modular battery systems has unique requirements for the power electronics designer, including architecture, design, modeling and control of power processing converters, and battery balancing methods. This dissertation considers the requirements imposed by electric vehicle and stationary applications and presents design and control of modular battery systems to overcome challenges associated with conventional systems. The modular battery system uses cell or substring-level power converters to combine battery balancing and power processing functionality and opens the door to new opportunities for advanced cell balancing methods. This approach enables balancing control to act on cell-level information, reroute power around weaker cells in a string of cells to optimally deploy the stored energy, and achieve performance gains throughout the life of the battery pack. With this approach, the integrated balancing power converters can achieve system cost and efficiency gains by replacing or eliminating some of the conventional components inside battery systems such as passive balancing circuits and high-voltage, high-power converters. In addition, when coupled with life prognostic based cell balancing control, the modular system can extend the lifetime of a battery pack by up to 40%. The modular architecture design and control concepts developed in this dissertation can be applied to designs of large battery packs and improve battery pack performance, lifetime, size, and cost.

No description available.

Emerging large-scale modular power converters are pursuing high-performance distributed control systems. As opposed to the centralized control architecture, the distributed control architecture features shared computational burdens, pulse-width modulation (PWM) latency compensation, simplified fiber-optic cable connection, redundant data routes, and greatly enhanced local control capabilities. Modular multilevel converters (MMCs) with conventional control are subjected to large capacitor voltage ripples, especially at low-line frequencies. It is proved that with appropriate arm current shaping in the timescale of a switching period, referred as the switching-cycle control (SCC), such line-frequency dependence can be eliminated and MMCs are enabled to work even in dc-dc mode. Yet the SCC demands multiple times of arm current alternations in one switching period. To achieve the high-bandwidth current regulation, hybrid modulation approach incorporating both the carrier-based modulation and the peak-current-mode (PCM) modulation is adopted. The combined digital and analog control and the extreme time-sensitive nature together pose great challenges on the practical implementation that the existing distributed control systems cannot cope with. This dissertation aims to develop an optimized distributed control system for SCC implementation. The critical analog PCM modulation is enabled by the intelligent gate driver with integrated rogowski coil and field programmable gate array (FPGA). A novel distributed control architecture is proposed accordingly for SCC applications where the hybrid modulation function is shifted to the gate driver. The proposed distributed control solution is verified in the SCC-based converter operations. Accompanied by the growing availability of medium-voltage silicon carbide (SiC) devices, fast-switching-enabled novel control schemes raise a high synchronization requirement for the communication network. Power electronics system network (PESNet) 3.0 is a proposed next-generation communication network designed and optimized for a distributed control system. This dissertation presents the development of PESNet 3.0 with a sub-nanosecond synchronization error (SE) and a gigabits-per-second data rate dedicated for large-scale high-frequency modular power converters. The White Rabbit Network technology, originally developed for the Large Hadron Collider accelerator chain at the European Organization for Nuclear Research (CERN), has been embedded in PESNet 3.0 and tailored to be suited for distributed power conversion systems. A simplified inter-node phase-locked loop (N2N-PLL) has been developed. Subsequently, stability analysis of the N2N-PLL is carried out with closed-loop transfer function measurement using a digital perturbation injection method. The experimental validation of the PESNet 3.0 is demonstrated at the controller level and converter level, respectively. The latter is on a 10 kV SiC-MOSFET-based modular converter prototype, verifying ±0.5 ns SE at 5 Gbps data rate for a new control scheme. The communication network has an impact on the converter control and operation. The synchronicity of the controllers has an influence on the converter harmonics and safe operation. A large synchronization error can lead to the malfunction of the converter operation. The communication latency poses a challenge to the converter control frequency and bandwidth. With the increased scale of the modular converter and control frequency, the low-latency requirement of communication network becomes more stringent. / Doctor of Philosophy / Emerging silicon carbide (SiC) power devices with 10 times higher switching frequencies than conventional Si devices have enabled high-frequency high-density medium-voltage converters. In the meantime, the power electronics building block (PEBB) concept has continually benefited the manufacturing and maintenance of modular power converters. This philosophy can be further extended from power stages to control systems, and the latter become more distributed with greatly enhanced local control capabilities. In the distributed control and communication system, each PEBB is equipped with a digital controller. In this dissertation, a real-time distributed control architecture is designed to take the advantage of the powerful processing capability from all digital control units, achieving a minimized digital delay for the control system. In addition, pulse-width modulation (PWM) signals are modulated in each PEBB controller based on its own clock. Due to the uncontrollable latency among different PEBB controllers, the synchronicity becomes a critical issue. It is necessary to ensure the synchronous operation to follow the desired modulation scheme. This dissertation presents a synchronized communication network design with sub-ns synchronization error and gigabits-per-second data rate. Finally, the impact of the communication network on the converter operation is analyzed in terms of the synchronicity, the communication latency and fault redundancy.

The continuous conduction mode (CCM) boost, buck-boost and buck-boost derived pulse-width modulation dc-dc converters suffer from the large-signal control-to-output nonlinearity. Without feedback control, the large-signal control-to-output nonlinearity would lead to output overregulation and even damage the components. The control gain is defined as the ratio of output voltage to control signal. The small-signal control gain is defined as differentiating output voltage with respect to control signal. Feedback control helps to make the output trace the reference signal. A large-signal control-to-output linearity is established. Compared with open loop control, the feedback loop design is complex; and the feedback control might suffer from the instability caused by the negative small-signal control gain, which is due to the loss and parasitic in practice. Except feedback control, open loop linearization methods can also realize the large-signal control-to-output linearity. A modulated-ramp pulse-width modulation generator is introduced in [6]. A current source works as the control signal. A capacitor is charged by the current source, whose voltage works as the carrier and compared with a constant dc bias voltage to determine the duty cycle. When applying this method to boost, buck-boost and buck-boost derived PWM dc-dc converters, a large-signal control-to-output linearity is established. However, the control gain is dependent on the input voltage; it cannot maintain constant when input voltage varies. A feedforward pulse width modulator is introduced in [39] to realize a large-signal control-to-output linearity. The static conversion ratio is divided into numerator and denominator as the functions of duty cycle. An integrator with reset clock signal helps to determine the right timing. The control gain is ideally constant and independent of input voltage. However, the mismatch between the integrator time constant and the switching period would result in a nonlinear control gain, which is dependent on the input voltage. In the thesis work, a self-oscillating unified linearizing modulator is introduced. It first provides a unified procedure to establish a large-signal control-to-output linearity for different pulse-width modulation dc-dc converters. Feedforward is employed to mitigate the impact from line voltage. Self-oscillation is adopted to provide the internal clock signal and to determine the switching frequency. A constant control gain is obtained, independent on the input voltage or the mismatch between clock signals. The modulator is constructed by three simple and standard building blocks. With the considerations of parasitic components and loss, how to design the constant gain, which excludes the negative small-signal control gain within the entire control signal range, is analyzed and discussed. The performance of this self-oscillating unified linearizing modulator is verified by experiments. The impacts from propagation delay in practical components are taken into considerations, which improves the quality of generated signals. Combined with a boost converter, a good large-signal control-to-output linearization is demonstrated. In the future work, the small-signal control-to-output transfer function is first deduced based on the SOUL modulator. Bode plots show the unique characteristic based on the SOUL modulator compared with the conventional modulator. Next, the impacts from this unique characteristic to feedback loop design and dynamic performance are discussed. / Master of Science

Numerous power electronics building blocks (PEBB) based power conversion systems have been developed to explore modular design, scalable voltage and current ratings, low-cost operations, etc. This paper further extends the modular concept from the power stage to the control system. The communication network in SiC-based modular power converters is becoming significant for distributed control architecture, with the requirements of tight synchronization and low latency. The influence of the synchronization accuracy on harmonics under the phase-shifted carrier pulse width modulation (PSC-PWM) is evaluated. When the synchronization is accurate, the influence of an increase in harmonics can be ignored. Thus, a synchronous distributed control and communication protocol with well-performed synchronization of 25 ns accuracy is proposed and verified for a 120 kHz SiC-based impedance measurement unit (IMU) with cascaded H-bridge PEBBs. An improved synchronization method with additional analog circuits is further implemented and verified with sub-ns synchronization accuracy. / The power electronics building block (PEBB) concept is proposed for medium-voltage converter applications in order to realize the modular design of the power stage. Traditionally, the central control architecture is popular in converter systems. The voltage and current are sensed and then processed in one central controller. The control hardware interfaces and software have to be customized for a specified number of power cells, and the scalability of controller is lost. In stead, in the distributed control architecture, a local controller in each PEBB can communicate with the sensors, gate drivers, etc. A high-level controller collects the information from each PEBB and conducts the control algorithm. In this way, the design can be more modular, and the local controller can share the computation burden with the high-level controller, which is good for scalability. In such distributed control architecture, a synchronous communication system is required to transmit data and command between the high-level controller and local controllers. A power converter always requires a highly synchronized operation to turn on or turn off the devices. In this work, a synchronous communication protocol is proposed and experimentally validated on a SiC-based modular power converter.

The use of insulated-gate bipolar transistor (IGBT)-based power converters is increasing exponentially. This is due to high performance of these devices in terms of efficiency and switching speed. However, due to the switching action, high frequency electromagnetic interference (EMI) noises are generated. Design of a power converter with reduced EMI noise level is one of the primary objectives of this research. The first part of the work focuses on designing common-mode (CM) filters, which can be integrated with differential-mode (DM) filters for three-phase pulse-width modulation (PWM) rectifier-based motor drives. This work explores the filter design based on the CM equivalent circuit of the drive system. Guidelines are provided for selection of the filter components. Different variants of the filter topology are evaluated to establish the effectiveness of the proposed topology. Analytical results based on Bode plot of the transfer functions are presented, which suggest effective EMI reduction. Experimental results based on EMI measurement on the grid side and CM current measurement on the motor side are presented. These results validate the effectiveness of the filter. In the second part of the work, it is shown that inclusion of CM filters into DM filters results in resonance oscillations in the CM circuit. An active damping strategy is proposed to damp the oscillations in both line-to-line and line-to-ground ac voltages and currents. An approach based on pole placement by state feedback is used to actively damp both the DM and CM filter oscillations. Analytical expressions for state-feedback controller gains are derived for both continuous-and discrete-time models of the filter. Trade-off in selection of the active damping gain on the lower-order grid current harmonics is analysed using a weighted admittance function method. In the third part of the work, single-phase grid-connected power converters are considered. An integrated CM filter with DM LCL filter is proposed. The work explores the suitability of PWM methods for single-phase and parallel single-phase grid-connected power converters. It is found that bipolar PWM and unipolar PWM with 180◦interleaving angle are suitable for single-phase and parallel single-phase power converters, respectively. The proposed configuration along with the PWM methods reduces the CM voltage, CM current, and EMI noise level effectively. It is also shown that the suggested circuit is insensitive to nonidealities of the power converter such as dead-time mismatch, mismatch in converter-side inductors, unequal turn on and turn off of the switches, and propagation delays. In the fourth part of the work, the inter-phase inductor in parallel interleaved power converters is integrated with LCL filter boost inductor. Different variant designs are presented and compared with the proposed structure. It is shown that the proposed structure makes use of standard core geometries and consumes lesser core material as well as copper wire. Hence, it reduces the overall size and cost of the power converter. In the present work, a 10kVA three-phase back-to-back connected with input LCL filter and output dv/dt filter, a 5kVA single-phase grid-connected power converter with LCL filter, and a 7.5kVA parallel single-phase grid-connected power converter with LCL filter are fabricated in the laboratory to evaluate and validate the proposed methods. The experimental results validate the proposed methods that result in significant EMI performance improvement of grid-connected power converters.