In order to facilitate research and testing of kV/MVA class power electronics systems, Virginia Tech has constructed the High-Power lab facility. This lab supports testing of equipment operating at up to 1.3 MW, with maximum supply ratings of 4,160 V or 480 A, depending on how the system is configured. When operated as a recirculating power ring, the system will make minimal demands on utilities. An industrial supervisory, control, and data acquisition (SCADA) system will be used to control the facility. In this paper we will detail the lab design and give insight to the decisions behind it, with an aim toward helping the reader in their own similar effort. / Master of Science

Cellular radio communication involves wireless transmission and reception of signals at radio frequencies (RF). Base stations house equipment critical to the transmission and reception of signals. Power amplifier (PA) is a crucial element in base station assembly. PAs are expensive, take up space and dissipate heat. Of all the elements in the base station, it is difficult to design and operate a power amplifier. New designs of power amplifiers are constantly tested. One of the most important components required to perform this test successfully is a circuit simulator model of an entire communication system that generates a standard test signal. Standard test signals 524,288 data points in length require 1080 hours to complete one test of a PA model. In order to reduce the time taken to complete one test, a 'simulated test signal,' was generated. The objective of this study is to develop an algorithm to generate this 'simulated' test signal such that its characteristics match that of the 'standard' test signal.

Low-cost test and tuning methods for difficult-to-measure specifications are presented in this research from the following perspectives: 1)"Safe" test and self-tuning for power converters: To avoid the risk of device under test (DUT) damage during conventional load/line regulation measurement on power converter, a "safe" alternate test structure is developed where the power converter (boost/buck converter) is placed in a different mode of operation during alternative test (light switching load) as opposed to standard test (heavy switching load) to prevent damage to the DUT during manufacturing test. Based on the alternative test structure, self-tuning methods for both boost and buck converters are also developed in this thesis. In addition, to make these test structures suitable for on-chip built-in self-test (BIST) application, a special sensing circuit has been designed and implemented. Stability analysis filters and appropriate models are also implemented to predict the DUT’s electrical stability condition during test and to further predict the values of tuning knobs needed for the tuning process. 2) High bandwidth RF signal generation: Up-convertion has been widely used in high frequency RF signal generation but mixer nonlinearity results in signal distortion that is difficult to eliminate with such methods. To address this problem, a framework for low-cost high-fidelity wideband RF signal generation is developed in this thesis. Depending on the band-limited target waveform, the input data for two interleaved DACs (digital-to-analog converters) system is optimized by a matrix-model-based algorithm in such a way that it minimizes the distortion between one of its image replicas in the frequency domain and the target RF waveform within a specified signal bandwidth. The approach is used to demonstrate how interferers with specified frequency characteristics can be synthesized at low cost for interference testing of RF communications systems. The frameworks presented in this thesis have a significant impact in enabling low-cost test and tuning of difficult-to-measure device specifications for power converter and high-speed devices.

\par The thesis deals with the statistical evaluation of data gained by the sensory analysis of the foodstuff. It brings a selection of the suitable statistical tests, a detailed analysis of these tests and their comparision based on the particular power functions for given parameters. As an important part of the thesis, there is a creating of custom software for the evaluating of sensorial data.

Statisticians are interested in testing the structure of covariance matrices, especially under the high-dimensional scenario in which the dimensionality of data matrices exceeds the sample size. Many test statistics have been introduced to test whether the covariance matrix is equal to identity structure (<img src="http://www.diva-portal.org/cgi-bin/mimetex.cgi?H_%7B01%7D:%20%5CSigma%20=%20I_p" />), sphericity structure (<img src="http://www.diva-portal.org/cgi-bin/mimetex.cgi?H_%7B02%7D:%20%5CSigma%20=%20%5Csigma%5E2I_p" />) or diagonal structure (<img src="http://www.diva-portal.org/cgi-bin/mimetex.cgi?H_%7B03%7D:%20%5CSigma%20=%20diag(d_1,%20d_2,%5Cdots,d_p)" />). These test statistics work under the assumption that data follows the multivariate normal distribution. In our thesis work, we want to compare the performance of test statistics for each structure test under given assumptions and when the distributional assumption is violated, and compare the test sensitivity to outliers. We apply simulation studies with the help of significance level, power of test, and goodness of fit tests to evaluate the performance of structure test statistics. In conclusion, we identify the recommended test statistics that perform well under different scenarios. Moreover, we find out that the test statistics for the identity structure test are more sensitive to the changes of distribution assumptions and outliers compared with others. The test statistics for the diagonal structure test have a better tolerant to the change of the data matrices.

This paper deals with a method to additionally heat with switching losses in a classical power cycling test, as it is often used for power semiconductors.The fundamentals of testing, switching behavior, thermal and electrical characteristics of semiconductors are covered.The core of the work is the construction, start-up and solution of technical problems during the testing of the test stand. Another aspects are the measurement and software challenges in generating the pulse pattern and in evaluating the results. The last part of the work deals with the testing of different types of semiconductors, such as IGBTs and MOSFETs, which were also made of different materials, such as silicon and silicon carbide, and had different voltage classes.:Contents i Symbols and Abbreviations iii Introduction 1 1. Power Cycling Lifetime 2 1.1. Power Cycling-induced Ageing Mechanisms and Test Methods 2 1.1.1. Overview of Packaging Technologies and their Wear-out Failures 2 1.1.2. Failure Mechanisms in Power Modules and Discrete Devices 6 1.1.3. Basic Structure of a Test Bench for DC Power Cycling Tests 8 1.1.4. Modifications for SiC MOSFET Operation 12 1.1.5. Measurement Accuracy, Limits and Consequences for Test Evaluation 16 1.1.6. Thermal Resistance and Thermal Impedance Spectroscopy 18 1.2. Empirical Power Cycling Lifetime Models 21 2. Specific Limitations in Conditions for some Devices 27 3. Approaches of an Application-close Power Cycling Test 30 4. New Test Bench Concept with an adjustable part of switching losses 35 4.1. Basics for Switching 35 4.1.1. Active Clamping 38 4.1.2. Boosted Active Clamping 40 4.2. Repetitive Unclamped Inductive Switching 42 4.3. Test Bench Concept for Power Cycling Test with Turn-off Losses 44 4.4. Dimensioning of the Stray Inductance 47 4.4.1. Current Ripple and Attainable Switching Losses 51 4.5. Special Setup for Si and SiC MOSFETs 57 4.6. Measurement Algorithm and necessary Hardware 58 4.6.1. Measurement Hardware 58 4.6.2. Measurement Algorithm 60 4.6.3. Challenges during the Measurement 62 4.6.4. Current Source for Fast Regulation 66 5. Test Results with IGBTs 69 5.1. Modules with Baseplate 69 5.2. Modules without Baseplate 80 5.3. IGBTs in Discrete Housings 90 6. Test Results with MOSFETs 97 6.1. Low Voltage Si MOSFETs 97 6.2. SiC MOSFETs 106 7. Analysis of Si Low-voltage MOSFETs Results with FEM 107 8. Conclusion and Outlook 113 9. Acknowledgement 118 References 119 Appendix 136

This work deals with the power cycling reliably of power modules and discrete devices. A small part was tested with standard test equipment, but the majority of devices were tested with an advanced test approach with additional switching losses. A large variety of packages under different conditions were tested: Discrete low-voltage silicon MOSFETs (<100 V), discrete SiC MOSFETs, baseplate-free SiC modules, medium power silicon modules and high power silicon modules. The core of the work is the investigation of low temperature swings in the transition between elastic and plastic deformation. During high operation temperatures, no significant increase in lifetime was observed, but at reduced junction temperatures, the impact was significant. All experimental results were transferred into a 3D simulation environment, for further investigation of the temperature and current distribution as well as the mechanical fatigue parameters, to allow a better understanding of the physical processes.

Power electronics, which fully covers the generation, conversion, transmission and usage of electrical energy, is a key technology for human welfare. With the development of technologies, the requirements on the reliability of power electronic systems are keep increasing. Long term operation under harsh environments is often accompanied by higher switching frequency and higher power density. To allow a reliable and sustainable performance of the power electronic systems, precise lifetime estimation of the power semiconductor devices is of significant importance. This work covers some aspects in the lifetime prediction of power semiconductor devices, especially IGBT and diode, in power module and transfer-molded discrete package. Difference in device temperature determination was illustrated using analytical calculation, simulation and measurement. In addition, temperature calculation in the frequency domain was demonstrated which gives benefits in the application with several hundred devices. Furthermore, different control strategies in the power cycling test were compared. The linear cumulative damage theory was validated by using the power cycling test. For the high power IGBT module used in the MMC HVDC application, power cycling lifetime with 50 Hz heating processes was investigated. For the transfer-molded discrete package, the first lifetime model with comparable scope like the lifetime model of power modules was proposed. / Leistungselektronik, welche direkt relevant für die Erzeugung, Umwandlung, Übertragung und Nutzung elektrischer Energie ist, ist eine Schlüsseltechnologie für das Wohl der Menschen. Mit der Entwicklung von Technologien steigen die Anforderungen an die Zuverlässigkeit leistungselektronischer Systeme. Der Langzeitbetrieb unter rauen Umgebungsbedingungen geht häufig mit einer höheren Schaltfrequenz und einer höheren Leistungsdichte einher. Um eine zuverlässige und nachhaltige Operation der leistungselektronischen Systeme zu ermöglichen, ist die genaue Lebensdauerabschätzung der Halbleiter-Leistungsbauelemente von großer Bedeutung. Diese Arbeit befasst sich mit einigen Aspekten der Lebensdauerabschätzung von den Halbleiter-Leistungsbauelementen. Unterschied in der Temperaturabstimmung der Halbleiter-Leistungsbauelemente wird anhand von Berechnung, Simulation und Messung veranschaulicht. Darüber hinaus bietet die Temperaturberechnung im Frequenzbereich Vorteile bei der Anwendung mit mehreren hundert Bauelementen. Darüber hinaus wurden verschiedene Regelstrategien im Lastwechseltest verglichen. Die lineare kumulative Alterungstheorie wurde unter Verwendung des Lastwechseltests validiert. Für das in der MMC-HGÜ-Anwendung verwendete Hochleistungs-IGBT-Modul wurden Alterungsprozesse bei 50 Hz Erwärmung untersucht. Für das Diskrete-Gehäuse wird das erste Lebensdauermodell vorgestellt, welches ein vergleichbares Anwendungsbereich wie das Lebensdauermodell von Leistungsmodulen hat.

Miniaturizing circuit size and increasing power density are the latest trends in modern power electronics development. In order to meet the requirements of higher frequency and higher power density in power electronics applications, planar interconnections are utilized to achieve a higher integration level. Power switching devices, passive power components, and EMI (Electromagnetic Interference) filters can all be integrated into planar power modules by using planar metallization, which is a technology involving electrical, mechanical, material, and thermal issues. By processing high dielectric materials, magnetic materials, or silicon chips using compatible manufacturing procedures, and by carefully designing structures and interconnections, we can realize the conventional discrete inductors, capacitors, and switch circuits with planar modules. Compared with conventional discrete components, the integrated planar modules have several advantages including lower profiles, better form factors, and less labor-intensive processing steps. In addition, planar interconnections reduce the wire bond inductive and resistive parasitic parameters, especially for high frequency applications. However, planar integration technology is a packaging approach with a large contact area between different materials. This may result in unknown failure mechanisms in power applications. Extensive research has already been done to study the performance, processing, and reliability of the planar interconnects in thin film structures. The thickness of the thin films used in integrated circuits (IC) or microelectronics applications ranges from the magnitude of nanometers to that of micrometers. In this work, we are interested in adopting planar interconnections to Integrated Power Electronics Modules (IPEM). In Integrated Power Electronics Modules (IPEMs), copper traces, especially bus traces, need to conduct current ranging from a few amps to tens of amps. One of the major differences between IC and IPEM is that the metal layer in IPEMs (normally >75µm) is much thicker than that of the thin films in IC (normally <1µm). The other major difference, which is also a feature of IPEM, is that the planar metallization is deposited on different brittle substrates. In active IPEM, switching devices are in a bare die form with no encapsulation. The copper deposition is on top of the silicon chips and the insulation polyimide layer. One of the key elements for passive IPEM and the EMI IPEM is the integrated inductor-capacitor (LC) module, which realizes equivalent inductors and capacitors in one single module. The deposition processes for silicon substrates and ceramic substrates are compatible and both the silicon and ceramic materials are brittle. Under high current and high temperature conditions, these copper depositions on brittle materials will cause detrimental failure spots. Over the last few years, the design, manufacture, optimization, and testing of the IPEMs has been developed and well documented. Up to this time , the research on failure mechanisms of conventional integrated power modules has led to the understanding of failures centered on wire bond or solder layer. However, investigation on the reliability and failure modes of IPEM is lacking, particularly that which uses metallization on brittle substrates for high current operations. In this study, we conduct experiments to measure and calculate the residual stresses induced during the process. We also, theoretically model and simulate the thermo-mechanical stresses caused by the mismatch of thermal expansion coefficients between different materials in the integrated power modules. In order to verify the simulation results, the integrated power modules are manufactured and subjected to the lifetime tests, in which both power cycling and temperature cycling tests are carried out. The failure mode analysis indicates that there are different failure modes for copper films under tensile or compressive stresses. The failure detection process verifies that delamination and silicon cracks happen to copper films due to compressive and tensile stresses respectively. This study confirms that the high stresses between the metallization and the silicon are the failure drivers in integrated power electronics modules.. We also discuss the driving forces behind several different failure modes. Further understanding of thesefailure mechanisms enables the failure modes to be engineered for safer electrical operation of IPEM modules and helps to enhance the reliability of system-level operation. It is also the basis to improve the design and to optimize the process parameters so that IPEM modules can have a high resistance to recognized failures. / Ph. D.

Pension schemes are facing more difficulties on matching their underlying liabilities with assets, mainly due to faster mortality improvements for their underlying populations, better environments and medical treatments and historically low interest rates. Given most of the pension schemes are relatively much smaller than the national population, modelling and forecasting the small populations' longevity risk become urgent tasks for both the industrial practitioners and academic researchers. This thesis starts with a systematic analysis on the influence of population size on the uncertainties of mortality estimates and forecasts with a stochastic mortality model, based on a parametric bootstrap methodology with England and Wales males as our benchmark population. The population size has significant effect on the uncertainty of mortality estimates and forecasts. The volatilities of small populations are over-estimated by the maximum likelihood estimators. A Bayesian model is developed to improve the estimation of the volatilities and the predictions of mortality rates for the small populations by employing the information of larger population with informative prior distributions. The new model is validated with the simulated small death scenarios. The Bayesian methodologies generate smoothed estimations for the mortality rates. Moreover, a methodology is introduced to use the information of large population for obtaining unbiased volatilities estimations given the underlying prior settings. At last, an empirical study is carried out based on the Scotland mortality dataset.