Gallium Oxide (Ga2O3) is an ultra-wide bandgap semiconductor with a bandgap of 4.5–4.9 eV, which is larger than that of Silicon (Si), Silicon Carbide (SiC), and Gallium Nitride (GaN). A benefit of this ultra-wide bandgap is the high-temperature stability due to the low intrinsic carrier concentration. Another benefit is the high critical electric field (Ec), which is estimated to be from 6 MV/cm to 8 MV/cm in Ga2O3. This allows for a superior Baliga's figure of merit (BFOM) of unipolar Ga2O3 power devices, i.e., they potentially can achieve a smaller specific on-resistance (RON,SP) as compared to the Si, SiC, and GaN devices with the same breakdown voltage (BV). The above prospects make Ga2O3 devices the promising candidates for next-generation power electronics. This dissertation explores the design, fabrication, characterization, and packaging of vertical β-Ga2O3 Schottky barrier diodes (SBDs) and P-N diodes. The power SBDs allow for a small forward voltage and a fast switching speed; thus, it is ubiquitously utilized in power electronics systems. Meanwhile, the Ga2O3 power P-N diodes have the benefit of smaller leakage current, and the diode structure could be a building block for many advanced diodes and transistors. Hence, the study of Ga2O3 Schottky and P-N diodes is expected to provide the foundation for developing a series of Ga2O3 power devices. Firstly, vertical Ga2O3 Schottky and P-N diodes with a novel edge termination (ET), the multi-layer Nickel Oxide (NiO) junction termination extension (JTE), are fabricated on Ga2O3 substrates. This multi-JTE NiO structure decreases the peak electric field (Epeak) at the triple point of device edge when the Ga2O3 diodes are reversely biased. For SBDs, BV reach 2.5 kV, the 1-D junction field reaches 3.08 MV/cm, and the BFOM exceeds 1 GW/cm2. For P-N diodes, BV reaches 3.3 kV, the junction field reaches 4.2 MV/cm, and the BFOM reaches 2.6 GW/cm2. These results are among the highest in Ga2O3 power devices and are comparable to the state-of-the-art vertical GaN Schottky and P-N diodes. Notably, all these diodes are small-area devices. Secondly, large-area (3 mm×3 mm anode size) Ga2O3 Schottky and P-N diodes with high current capability are fabricated to explore the packaging, thermal management, and switching characteristics of Ga2O3 diodes. The same ET is applied for the large-area P-N diode. The fabricated large-area P-N diodes have a turn-on voltage of 2 V, a differential on-resistance (Ron) of 0.2 Ω, and they can reach at least 15 A when measured in the pulse mode. The BV of large-area Ga2O3 P-N diodes varies due to the fabrication non-uniformity, but the best device achieves a BV of 1.6 kV, standing among the highest values reported for large-area Ga2O3 diodes. Also, the large-area Ga2O3 SBDs with similar current rating but with a FP ET are fabricated mainly for the packaging and thermal management studies. Thirdly, medium-area Ga2O3 P-N diodes with a current over 1 A and a higher yield of BV are fabricated to evaluate the JTE's capacitance and switching characteristics. The JTE accounts for only ~11% of the junction capacitance of this 1 A diode, and the percentage is expected to be even smaller for higher-current diodes. The turn-on/off speed and reverse recovery time of the diode are comparable to commercial SiC Schottky barrier diodes under the on-wafer switching test. These results show the viability of NiO JTE for enabling a fast switching speed in high-voltage Ga2O3 power devices. Fourthly, the fabricated large-area Ga2O3 diodes are packaged using silver sintering as the die attach. The sintered silver joint has higher thermal conductivity (kT) and better reliability as compared to the solder joint. Due to the low kT of Ga2O3 material, junction-side-cooled (JSC) packaging configuration is necessary for Ga2O3 devices. For the packaged device, its junction-to-case thermal resistance (RθJC) is measured in the bottom-side-cooled (BSC) and junction-side-cooled (JSC) configuration by the transient dual interface method according to the JEDEC 51-14 standard. The RθJC of the junction- and bottom-cooled Ga2O3 SBD is measured to be 0.5 K/W and 1.43 K/W, respectively. The former RθJC is lower than that of similarly-rated commercial SiC SBDs. This manifests the significance of JSC packaging for the thermal management of Ga2O3 devices. Fifthly, to evaluate the electrothermal robustness of the packaged Ga2O3 devices, the surge current capability of JSC packaged Ga2O3 SBDs are measured. The Ga2O3 SBDs with proper packaging show high surge current capabilities. The double-side-cooled (DSC) large-area Ga2O3 SBDs can sustain a peak surge current over 60 A, with a ratio between the peak surge current and the rated current superior to that of similarly-rated commercial SiC SBDs. These results show the excellent ruggedness of Ga2O3 power devices. Finally, a Ga2O3 integrated diode module consisting of four single-diode sub-modules is designed and fabricated. For many power electronics applications, high current is desired; however, for emerging semiconductors, the current upscaling is difficult by directly increasing the device area because of the limitation of heat extraction capability and the limited material/processing yield. Here we explore the paralleling of multiple Ga2O3 P-N diodes to increase the current level. For each sub-module, the JSC packaging structure is used for heat extraction, and a metal post is sintered to the anode for electric field (E-field) management. RθJC is measured to be 1 W/K for each sub-module. On-board double-pulsed test is performed for both the sub-module and the full module. The sub-module and full module demonstrate 400 V, 10 A and 150 V, 70 A switching capabilities, respectively. This is the first demonstration of Ga2O3 power module and shows a promising approach to upscale of the power level of Ga2O3 power electronics. In addition to Ga2O3 device study, a research is conducted to explore the chip size (Achip) minimization for wide-bandgap (WBG) and ultra-wide bandgap (UWBG) power devices. Achip optimization is particularly critical for WBG and UWBG power devices and modules due to the high material cost. This work presents a new, holistic, electrothermal approach to optimize Achip for a given set of target specifications including BV, conduction current (I0), and switching frequency (f). The conduction and switching losses of the device are considered, as well as the heat dissipation in the chip and its package. For a given BV and I0, the optimal Achip, Wdr, and Ndr show strong dependence on f and thermal management. Our approach offers more accurate cost analysis and design guidelines for power modules. In summary, this dissertation covers the design, fabrication, characterization, and packaging of Ga2O3 Schottky and P-N diodes, with the aim to advance Ga2O3 devices to power electronics applications. This dissertation addresses many knowledge gaps on Ga2O3 devices, including the voltage upscaling (ET), current upscaling (large-area device fabrication, packaging, and thermal management), and their concurrence (module demonstration), as well as the circuit-level switching characterizations. / Doctor of Philosophy / Power electronics is the processing of electric energy using solid-state electronics. It is ubiquitously used in consumer electronics, data centers, electric vehicles, electricity grids, and renewable energy systems. Advanced power device technologies are paramount to improving the performance of power electronic systems. Power device design centers on the concurrent realization of low on-resistance (RON), high breakdown voltage (BV), and small turn-on/turn-off power losses. A key driver for advancement of power devices is the semiconductor material. Over the last decade, power devices based on wide-bandgap semiconductors like SiC and GaN have enabled tremendous performance advancements in power electronic systems. On the horizon, Ga2O3 is an emerging semiconductor with an ultra-wide bandgap (UWBG) of 4.5–4.9 eV, which is higher than that of Si, SiC, and GaN. Benefitted from this larger bandgap, the theoretical performance of Ga2O3 power devices is superior to the Si, SiC, and GaN counterparts. Hence, Ga2O3 devices are regarded as the promising candidates for next-generation power electronics. The power diode is an important component in power circuits, and the diode structure is usually a building block for power transistors. Small-area (0.1 A current level) Ga2O3 Schottky barrier diodes (SBDs) and P-N diodes are first designed and fabricated with a novel ET, the NiO JTE, reaching a high BV from 2.5 to 3.5 kV and junction E-field up to 4.2 MV/cm. Subsequently, large-area (>15 A current level) Ga2O3 diodes are fabricated with the same ET, achieving a BV of 1.6 kV, which is among the highest BV demonstrated in large-area Ga2O3 devices. In addition, on-wafer switching tests are performed on the medium-area (1 A current level) Ga2O3 P-N diodes, and their turn-on/off speed and reverse recovery time are comparable to commercial SiC Schottky barrier diodes. In addition to voltage upscaling, current upscaling is also a key challenge for Ga2O3 power devices. To overcome the low thermal conductivity (kT) of Ga2O3, junction side cooling (JSC) packaging is used to increase the heat extraction capability of Ga2O3 diode, enabling the demonstration of a junction-to-case thermal resistance comparable to that of similarly-rated, commercial SiC diode. Benefitted from this enhanced heat extraction, the packaged Ga2O3 diodes show an excellent surge current robustness. Finally, a Ga2O3 integrated diode module consisting of four single-diode sub-modules is designed, fabricated, and tested in the on-board switching circuits up to 70 A and 400 V. This is the first demonstration of a Ga2O3 power module. In summary, this dissertation covers the design, fabrication, characterization, and packaging of Ga2O3 power diodes with the aim to advance Ga2O3 devices to power electronics applications. This dissertation addresses many knowledge gaps on the voltage upscaling, current upscaling, and the circuit-level switching characteristics of Ga2O3 power devices and modules and thus pave the road for their power electronics applications.

Significant progress in reducing the growth temperature of the SiC epitaxial growth became possible in the previous work by using new chloro-carbon epitaxial growth method. However, it was established that even in the new process, homogenous nucleation of Si in the gas phase limited the growth rate. In the present work, new chlorinated silicon precursor SiCl4 was investigated as a replacement for the traditional silicon precursor SiH4 during the low-temperature chlorocarbon epitaxial growth. The new process completely eliminated the homogenous nucleation in the gas phase. Growth rate of 5-6 μm/h was achieved at 1300°C compared to less than 3 μm/h in the SiH4-based growth. The growth dependence on the C/Si ratio revealed that the transition from the C-supply-limited to the Si-supply-limited growth mode takes place at the value of the C/Si ratio much higher than unity, suggesting that certain carbon-containing species are favorably excluded from the surface reactions in the new process. Morphology degradation mechanisms, which are unique for the lowtemperature growth, were observed outside the established process window. Prior to this work, it remained unclear if CH3Cl simply served as a source of Cl to suppress homogeneous nucleation in the gas phase, or if it brought some other unknown improvements. In this work true benefits of CH3Cl in providing unique improvement mechanisms have been revealed. It was established that CH3Cl provided a much wider process window compared to C3H8. In contrast, even a very significant supply of extra Cl from a chlorinated silicon precursor or from HCl during the C3H8-based growth could not provide a similar benefit. The combination of the chloro-carbon and the chloro-silane precursors was also investigated at conventional growth temperature. High-quality thick epitaxial layers, with the growth rate up to 100μm/h were obtained, and the factors influencing the growth rate and morphology were investigated. Extensive optical and electrical characterization of the low-temperature and the regular-temperature epitaxial layers was conducted. The device-quality of the lowtemperature chloro-carbon epilayers was validated for the first time since the development of the chloro-carbon epitaxial process in the year 2005 by fabricating simple Schottky diodes and investigating their electrical characteristics.

The MOS-gated thyristors (MGT) refer to the class of power devices that combine the ease of a MOS gate control with the superior current carrying capability of a thyristor structure for high-power applications. The MOS-controlled thyristor (MCT) is a typical MGT device. A comprehensive investigation of the reverse-biased safe operating area (RBSOA) characteristics of the MCT has been undertaken. The electrical failure mechanisms of the MCT are discussed, and the relationship between the dynamic avalanche limited RBSOA boundary of the MCT and the lower open-base transistor is identified. An analytical model based on the dynamic current gain concept is proposed to characterize the open-base transistor. For the first time, a RBSOA characteristic equation is developed for the MCT and a unified view of the RBSOA characteristics of the MCT is presented. The fundamental characteristics of the MCT are compared to those of the insulated gate bipolar transistor (IGBT) at two levels: unit-cell and multi-cell. The investigation of the unit-cell level focuses on the tradeoff between the on-state voltage drop, the turn-off loss, and the RBSOA characteristic. The investigation of the multi-cell level reveals the fundamental difference between the MCT and the IGBT in handling the non-uniform turn-off caused by the internal propagation gate delay of a large-area device. Lack of current saturation capability is identified as the main reason for the severe degradation of the turn-off capability of a large-area multi-cell MCT. The current saturation and controlled turn-on capabilities can be realized in the MGT devices with dual operation modes. For the first time, a dual operation mode MCT developed with superior current saturation capability is used to demonstrate how the dual operation device can be beneficial in the switching circuit application. The maximum controllable current density (Jmcc) is the most important characteristic of the dual operation mode MGT devices. A first-order analytic model is developed to characterize the Jmcc of the dual operation mode MGT structures compatible with the IGBT fabrication process. A new device structure with improved Jmcc characteristics is proposed and verified by both simulation and experimental results. The dissertation also carries out a comprehensive investigation of the development of power diodes. A new power diode, called the Trench Bipolar Junction Diode (TBJD), which has superior dynamic characteristics over the conventional P-i-N diode, is proposed. The TBJD controls the anode injection efficiency of the diode by the action of a reverse active transistor structure integrated into its anode junction. The reverse active transistor helps tailor an optimized on-state carrier profile to improve the diode switching characteristics. A novel self-aligned process is developed to fabricate the TBJD. Experimental characterization of the fabricated TBJD devices shows that the TBJD achieves superior dynamic characteristics without sacrificing the on-state voltage drop and the leakage current characteristics. / Ph. D.

The next generation of power converters not only must meet the characteristics demanded by the load, but also has to meet some specific requirements like limited space and high ambient temperature etc. This needs the power converter to achieve high power density and high temperature operation. It is usually required that the active power devices operate at higher switching frequencies to shrink the passive components volume. The power semiconductor devices for high frequency high density power converter applications have been investigated. Firstly, the methodology is developed to evaluate the power semiconductor devices for high power density applications. The power density figure of merit (PDFOM) for power MOSFET and IGBT are derived from the junction temperature rise, power loss and package points of view. The device matrices are generated for device comparison and selection to show how to use the PDFOM. A calculation example is given to validate the PDFOM. Several semiconductor material figures of merit are also proposed. The wide bandgap materials based power devices benefits for power density are explored compared to the silicon material power devices. Secondly, the high temperature operation characteristics of power semiconductor devices have been presented that benefit the power density. The electrical characteristics and thermal stabilities are tested and analyzed, which include the avalanche breakdown voltage, leakage current variation with junction temperature rise. To study the thermal stability of power device, the closed loop thermal system and stability criteria are developed and analyzed. From the developed thermal stability criterion, the maximum switching frequency can be derived for the converter system design. The developed thermal system analysis approach can be extended to other Si devices or wide bandgap devices. To fully and safely utilize the power devices the junction temperature prediction approach is developed and implemented in the system test, which considers the parasitic components inside the power MOSFET module when the power MOSFET module switches at hundreds of kHz. Also the thermal stability for pulse power application characteristics is studied further to predict how the high junction temperature operation affects the power density improvement. Thirdly, to develop high frequency high power devices for high power high density converter design, the basic approaches are paralleling low current rating power MOSFETs or series low voltage rating IGBTs to achieve high frequency high power output, because power MOSFETs and low voltage IGBTs can operate at high switching frequency and have better thermal handling capability. However the current sharing issues caused by transconductance, threshold voltage and miller capacitance mismatch during conduction and switching transient states may generate higher power losses, which need to be analyzed further. A current sharing control approach from the gate side is developed. The experimental results indicate that the power MOSFETs can be paralleled with proper gate driver design and accordingly the switching losses are reduced to some extent, which is very useful for the switching loss dominated high power density converter design. The gate driving design is also important for the power MOSFET module with parallel dice inside thus increased input capacitance. This results in the higher gate driver power loss when the traditional resistive gate driver is implemented. Therefore the advanced self-power resonant gate driver is investigated and implemented. The low gate driver loss results in the development of the self-power unit that takes the power from the power bus. The overall volume of the gate driver can be minimized thus the power density is improved. Next, power semiconductor device series-connection operation is often used in the high power density converter to meet the high voltage output such as high power density boost converter. The static and dynamic voltage balancing between series-connected IGBTs is achieved using a hybrid approach of an active clamp circuit and an active gate control. A Scalable Power Semiconductor Switch (SPSS) based on series-IGBTs is developed with built-in power supply and a single optical control terminal. An integrated package with a common baseplate is used to achieve a better thermal characteristic. These design features allow the SPSS unit to function as a single optically controlled three-terminal switching device for users. Experimental evaluation of the prototype SPSS shows it fully achieved the design objectives. The SPSS is a useful power switch concept for building high power density, high switching frequency and high voltage functions that are beyond the capability of individual power devices. As conclusions, in this dissertation, the above-mentioned issues and approaches to develop high density power converter from power semiconductor devices standpoint are explored, particularly with regards to high frequency high temperature operation. To realize such power switches the related current sharing, voltage balance and gate driving techniques are developed. The power density potential improvements are investigated based on the real high density power converter design. The power semiconductor devices effects on power density are investigated from the power device figure of merit, high frequency high temperature operation and device parallel operation points of view. / Ph. D.

This dissertation presents the analysis and development of an innovative semiconductor device and topology for the high power current source converter (CSC). The CSC is very attractive in high power applications due to its lower output dv/dt, easy regeneration capability and implicit short-circuit protection. Traditionally, either a symmetrical gate turn-off (GTO) thyritor or an asymmetrical GTO in series with a diode is used as the power switch in the CSC. Since the GTO has a lower switching speed and requires a complicated gate driver, the symmetrical GTO based CSC usually has low dynamic response speed and low efficiency. To achieve high power rating, fast dynamic response speed and low harmonics, an advanced semiconductor device and topology are needed for the CSC. Based on symmetrical GTO and power MOSFET technologies, a symmetrical emitter turn-off (ETO) thyristor is developed that shows superior switching performance, high power rating and reverse voltage blocking capability. The on-state characteristics, forced turn-on characteristics, forced turn-off characteristics and the load-commutated characteristics are studied. Test results show that although the load-commutation loss is high, the developed symmetrical ETO is suitable for use in high power CSC due to its low conduction loss, fast switching speed and reverse voltage blocking capability. The snubberless turn-on capability is preferred for a semiconductor device in a power conversion system, and can be achieved for devices with forward biased safe operation area (FBSOA). The FBSOA of the ETO is investigated and experimentally demonstrated. The ETO device has excellent FBSOA due to the negative feedback provided by the emitter switch. However, the FBSOA for a large area ETO is poor. A new ETO concept is therefore proposed for future development in order to demonstrate the FBSOA over a large area device. To improve the turn-on performance of the large area ETO, a novel concept, named the transistor-mode turn-on, is proposed and studied. During the transistor-mode turn-on process, the ETO behaves like a transistor instead of a thyristor. Without a snubber, the transistor-mode turn-on for the ETO is hard to achieve. Through the selection of a proper gate drive and di/dt snubber, the transistor-mode turn-on can be implemented, and the turn-on performance for the ETO can be dramatically improved. To increase the power rating of the CSC without degrading the utilization of power semiconductor devices, a novel multilevel CSC, named the parallel-cell multilevel CSC, is proposed. Based on a six-switch CSC cell, the parallel-cell multilevel CSC has the advantages of high power rating, low harmonics, fast dynamic response and modularity. Therefore, it is very suitable for high power applications. The power stage design, modeling, control and switching modulation scheme for a parallel-cell multilevel CSC based static var compensator (STATCOM) are analyzed and verified through simulation. / Ph. D.

This thesis provides insight into state-of-the-art 1.2 kV silicon carbide (SiC) power semiconductor transistors, including the MOSFET, BJT, SJT, and normally-on and normally-off JFETs. Both commercial and sample devices from the semiconductor industry's well-known manufacturers were evaluated in this study. These manufacturers include: Cree Inc., ROHM Semiconductor, General Electric, Fairchild Semiconductor, GeneSiC Semiconductor, Infineon Technologies, and SemiSouth Laboratories. To carry out this work, static characterization of each device was performed from 25 ºC to 200 ºC. Dynamic characterization was also conducted through double-pulse tests. Accordingly, this thesis describes the experimental setup used and the different measurements conducted, which comprise: threshold voltage, transconductance, current gain, specific on-resistance, parasitic capacitances, internal gate resistance, and the turn on and turn off switching times and energies. For the latter, the driving method used for each device is described in detail. Furthermore, for the devices that require on-state dc currents, driving losses are taken into consideration. While all of the SiC transistors characterized in this thesis demonstrated low specific on-resistances, the SiC BJT showed the lowest, with Fairchild's FSICBH057A120 SiC BJT having 3.6 mΩ•cm2 (using die area) at 25 ºC. However, the on-resistance of GE's SiC MOSFET proved to have the smallest temperature dependency, increasing by only 59 % from 25 ºC to 200 ºC. From the dynamic characterization, it was shown that Cree's C2M0080120D second generation SiC MOSFET achieved dv/dt rates of 57 V/ns. The SiC MOSFETs also featured low turn off switching energy losses, which were typically less than 70 µJ at 600 V bus voltage and 20 A load current. / Master of Science

Gallium Oxide (Ga2O3) is an ultra-wide bandgap semiconductor with a bandgap of 4.5–4.9 eV, which is higher than the bandgap of Silicon (Si), Silicon Carbide (SiC), and Gallium Nitride (GaN). A benefit of this wide-bandgap is the high critical electric field of Ga2O3, which is estimated to be from 5 MV/cm to 9 MV/cm. This allows a higher Baliga’s figure of merit (BFOM), i.e., unipolar Ga2O3 devices potentially possess a smaller specific on-resistance (Ron,sp) as compared to the Si, SiC, and GaN devices with the same breakdown voltage (BV). This prospect makes Ga2O3 devices promising candidates for next-generation power electronics. This thesis explores the design, fabrication, and packaging of vertical Ga2O3 Schottky barrier diodes (SBDs). The power SBD allows for a small forward voltage and a fast switching speed; thus, it is ubiquitously utilized in power electronics systems. It is also a building block for many advanced power transistors. Hence, the study of Ga2O3 SBDs is expected to pave the way for developing a series of Ga2O3 power devices. In this work, a vertical β-Ga2O3 SBD with a novel edge termination, which is the small-angle beveled field plate (SABFP), is fabricated on thinned Ga2O3 substrates. This SABFP structure decreases the peak electric field (Epeak) at the triple point when the Ga2O3 SBD is reverse biased, resulting in a BV of 1.1 kV and an Epeak of 3.5 MV/cm. This device demonstrates a BFOM of 0.6 GW/cm2, which is among the highest in β-Ga2O3 power devices and is comparable to the state-of-the-art vertical GaN SBDs. The high-temperature characteristics of Ga2O3 SBDs with a 45o beveled angle sidewall edge termination are studied at temperatures up to 600 K. As compared to the state-of-the-art SiC and GaN SBDs with a similar blocking voltage, the vertical Ga2O3 SBDs are capable of operating at higher temperatures and show a smaller leakage current increase with temperature. The leakage current mechanisms were also revealed at various temperatures and reverse biases. A new fabrication method of a dielectric field plate and Ga2O3 mesa of a medium angle (10o~30o) is achieved by controlling the adhesion between the photoresist (PR) and the dielectric surface. As compared to the small-angle termination, this medium-angle edge termination can allow a superior yield and uniformity in device fabrication, at the same time maintaining the major functionalities of beveled edge termination. Good surface morphology of the field plates and Ga2O3 mesa of the medium angle 10o~30o sidewall angle is verified by atomic force microscopy. Finally, large-area Ga2O3 SBDs are fabricated and packaged using silver sintering as the die attach. The sintered silver joint has higher thermal conductivity and better reliability as compared to the solder joint. The metal finish on the anode and cathode has been optimized for silver sintering. Large-area, packaged Ga2O3 SBDs with an anode size of 3×3 mm2 are prototyped. They show a forward current of over 5 A, a current on/off ratio of ~109, and a BV of 190 V. To the best of the author’s knowledge, this is the first experimental demonstration of a large-area, packaged Ga2O3 power device. / M.S. / Power electronics is the processing of electric energy using solid-state electronics. It is ubiquitously used in consumer electronics, data centers, electric vehicles, electricity grids, and renewable energy systems. Advanced power device technologies are paramount to improving the performance of power electronic systems. Power device design centers on the concurrent realization of low on-resistance (RON), high breakdown voltage (BV), and small turn-on/turn-off power losses. The performance of power devices hinges on semiconductor material properties. Over the last several years, power devices based on wide-bandgap semiconductors like Silicon Carbide (SiC) and Gallium Nitride (GaN) have enabled tremendous performance advancements in power electronic systems. Gallium Oxide (Ga2O3) is an ultra-wide bandgap semiconductor with a bandgap of 4.5–4.9 eV, which is higher than the bandgap of Silicon (Si), SiC, and GaN. As a benefit of this wide bandgap, the theoretical performance of Ga2O3 devices is superior to the Si, SiC, and GaN counterparts. Hence, Ga2O3 devices are regarded as promising candidates for next-generation power electronics. This thesis explores the design, fabrication, and packaging of vertical Ga2O3 Schottky barrier diodes (SBDs). The power SBD allows a small forward voltage and a fast switching speed; thus, it is extensively utilized in power electronics systems. It is also a building block for many advanced power transistors. First, a vertical β-Ga2O3 SBD with a novel edge termination is fabricated. This edge termination structure reduces the peak electric field (Epeak) in the device and enhances the BV. The fabricated device shows one of the highest figure of merits in β-Ga2O3 power devices. Next, the high-temperature characteristics of the fabricated Ga2O3 SBDs are studied at temperatures up to 600 K. The leakage current mechanisms were also revealed at various temperatures and reverse biases. Finally, large-area Ga2O3 SBDs are fabricated and packaged using silver sintering as the die attach. The sintered silver joint has higher thermal conductivity and better reliability as compared to the conventional solder joint. The packaged Ga2O3 SBDs show a forward current of over 5 A and a BV of 190 V. To the best of the author’s knowledge, this is the first experimental demonstration of a large-area, packaged Ga2O3 power device.

Wide-bandgap gallium nitride (GaN) high electron mobility transistors (HEMTs) are gaining increased adoption in applications like mobile electronics and data centers. Benefitting from the high channel mobility and the high breakdown field of GaN, GaN power HEMTs enable low specific on-resistance and small capacitance and thus become attractive for high-frequency applications. In addition, most commercial GaN power HEMTs are fabricated on Si substrates up to 8 inches, allowing for a remarkable cost advantage. However, a by-product of the low-cost GaN-on-Si wafer (and conductive Si substrate) is the high voltage drop and high electric field (E-field) in the GaN buffer layers and transition layers sandwiched between the GaN channel and Si substrate. To boost the vertical blocking capability and minimize the leakage current, the GaN buffer layer is usually doped with carbon or iron, which can introduce complex carrier traps. This can further lead to the dynamic shifts of various parameters in GaN-on-Si HEMTs, which can cause their stability and robustness issues in practical circuit operations. This dissertation work studies the robustness and stability of GaN power HEMTs in dynamic power switching. The structures of most GaN power devices are fundamentally different from Si or Silicon Carbide (SiC) power devices, leading to numerous open questions on GaN power device robustness and stability. Simple equipment-level static characterization may not reflect the real device characteristics in circuit-level operation. Based on the relevance between the stress condition and the device's safe operating area (SOA), this dissertation is divided into two parts. In each part, two representative GaN power devices, the standalone GaN HEMT, and the GaN-Si cascode HEMT, are studied. The dissertation's first half discusses the GaN HEMT behavior outside of SOA, with a focus on the robustness of GaN HEMTs in overvoltage power switching. This focus is motivated by the lack of avalanche capability of GaN HEMTs, which is a unique device physics distinct from SiC/Si power transistors. Instead of withstanding the surge energy through avalanching, GaN HEMTs rely on their high breakdown voltage margin to withstand the surge energy, which can trigger new degradation and failure mechanisms. Therefore, investigating the GaN HEMTs' robustness in overvoltage switching is of great interest. The robustness study begins with a standalone depletion-mode (D-mode) MIS (Metal-Insulator-Semiconductor) HEMT in an overvoltage hard-switching. The device is found to show a decreased threshold voltage and increased saturation current after stress. These parametric shifts increase as switching cycles increase but reach a saturation point before one million cycles. The root cause is believed to be the impact-ionization-generated holes trapped underneath the insulated gate. This is verified by the physics-based TCAD (Technology Computer-Aided Design) simulation. After the stress, MIS-HEMT cannot fully recover naturally. Applying at positive gate-to-source bias (VGS) is found to be able to accelerate the threshold voltage recovery but not the saturation current recovery, while a 50-V substrate bias is shown to fully recover both parameters. These findings provide new insight into the hole trapping/de-trapping dynamics and the benefits of substrate voltage control in GaN MIS-HEMTs. Then, a cascode GaN HEMT, which contains a D-mode GaN MIS-HEMT and an enhancement-mode (E-mode) Si MOSFET, is studied similarly in overvoltage stress produced by an inductive switching circuit. Parametric shifts are found in cascode GaN HEMTs, including the unstable breakdown voltage and increased on-resistance. The crosstalk between Si MOSFET and GaN HEMT is believed to account for these parametric shifts. A decapsulated device is developed based on the commercial part to monitor the Si MOSFET behavior. Si MOSFET is found to avalanche during the overvoltage switching. The parametric shifts are believed to be due to the avalanche-generated electrons, which are injected into the GaN HEMTs and trapped in the GaN buffer layer. These electron traps alter the E-field distribution of the GaN HEMT and induce parametric shifts. The second half of the dissertation focuses on the GaN HEMT's stability inside the SOA, with a focus on the non-ideal power loss generated in high-frequency switching. The output capacitance (COSS) loss has recently been found to be the dominant loss in soft switching, which is the loss associated with GaN HEMT's COSS when it is charged and discharged. This process should be lossless for an ideal capacitor, but GaN HEMT experiences a hysteresis COSS loss during each charging-discharging cycle due to the COSS instability in dynamic power switching. The COSS loss study starts with an accurate and easy-to-implement test platform, which is proven to have good robustness and repeatability. The measured COSS loss of different types of GaN HEMTs is modeled, followed by the investigation of the COSS loss origin. TCAD simulation reveals the fundamental role of trappings in the cause of COSS loss in standalone GaN HEMTs. For the cascode GaN HEMT, two additional loss mechanisms are involved as compared to the standalone GaN HEMTs: Si avalanche energy loss and GaN early turn-on loss. This makes cascode GaN HEMT experiences much higher COSS loss than standalone GaN HEMTs. The COSS loss of cascode GaN HEMT is quantitively analyzed, and a mitigation strategy is proposed for suppressing the COSS loss of cascode GaN HEMTs. Then, a circuit-level method is proposed to reduce the COSS loss of standalone GaN HEMT by dynamically tuning the substrate bias, which is verified with a standalone D-mode GaN HEMT. The Si substrate bias can follow the drain voltage in a certain ratio by tuning the capacitance ratio between the drain, substrate, and source. It is found that with a substrate bias of 1/4 to 1/2 of the drain voltage, the COSS loss can be reduced by 86%. This result removes a critical roadblock for deploying GaN HEMTs in high-frequency, soft-switching applications. Finally, the COSS loss of similarly rated Si and SiC power transistors is characterized using the developed test platform. The capability of the setup is further broadened to testing power diodes. Some similarities and distinctions are found in the COSS loss behavior between GaN HEMTs and Si/SiC devices. Also, an EDISS validation process is provided for the UIS-based method in an operating class-E converter, verifying the effectiveness and accuracy of the proposed method. This provides important references for selecting the optimal power devices for high-frequency applications. / Doctor of Philosophy / Gallium Nitride (GaN) high electron mobility transistors (HEMTs) are reshaping the power electronics field. They have become increasingly popular in many applications like smartphones, electric vehicles, and data centers. They offer smaller on-resistance and can handle higher voltages compared to traditional silicon-based devices. GaN transistors are built on large-diameter silicon substrates, making them cost-effective but can lead to unique stability and robustness issues. This dissertation investigates the stability and robustness of GaN power HEMTs in high-voltage and high-frequency power switching. Based on the relevance of the studied stress to the device safe-operating-area, the discussion is divided into two parts: The first part looks at how GaN transistors handle situations where they are pushed beyond their safe operating limits, such as during power surges and overvoltage events. These transistors are found to experience changes in their electrical properties after being stressed, which might affect their performance across their lifetime. In addition to unveiling the physics and evolution of such parametric shifts, this work also discovers ways to recover the device parameters and maintain the device functionality. The second part of the research focuses on the stability and non-ideal power loss of GaN transistors within their safe operating area. The high-frequency soft-switching application is being investigated, as it has become a common trend for future power electronics. The study reveals that GaN transistors can produce additional power loss due to the intrinsic electrical instabilities. In addition to unveiling the key impact factors and physics of this loss, this work also develops device designs to suppress this non-ideal power loss significantly, improving the device efficiency in high-frequency applications. Overall, this work provides valuable insights into improving the robustness and efficiency of GaN transistors, which provide guidelines and insights for GaN designers and users to achieve optimal device and system performance.

The thesis deals with study of high-temperature alloying process of power semiconductor devices. Mechanical durability and loss heat extraction is achieved via contacting silicon devices on molybdenum electrode in vacuum alloying furnace. Properties of alloy contact determine electrical, geometrical and mechanical parameters of device and are related with durability of device under heavy load during operation in various industrial machines or transport vehicles. Process parameters are evaluated in terms of input materials and their preparation along with temperature ramp profile and conditions in vacuum furnace. Test samples are analyzed to assess their electrical and geometrical parameters and selected samples underwent element analysis of alloy contact. Optimal process parameters are estimated according to analysis of experiments.

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