The third quadrant (3rd-quad) conduction (or reverse conduction) of power transistors is critical for synchronous power converters. For power metal-oxide-semiconductor field-effect-transistors (MOSFETs), there are two current paths in the 3rd-quad conduction, namely the MOS channel path and the body diode path. It is well known that, for 1.2 kV silicon carbide (SiC) planar MOSFETs, the conduction loss in the 3rd-quad is reduced by turning on the MOS channel with a positive gate bias (VGS) and keeping the dead time as small as possible. Under this scenario, the current is conducted through both paths, allowing the device to take advantage of the zero 3rd-quad forward voltage drop (VF3rd) of the MOS channel path and the small differential resistance of the body diode path. However, in this thesis work, this popular belief is found to be invalid for power MOSFETs with higher voltage ratings (e.g., 3.3 kV and 10 kV), particularly at high temperatures and current levels. The aforementioned MOS channel and body diode paths compete in the device’s 3rd-quad conduction, and their competition is affected by VGS and device structure. This thesis work presents a comparative study on the 3rd-quad behavior of 1.2 kV to 10 kV SiC planar MOSFET through a combination of device characterization, TCAD simulation and analytical modeling. It is revealed that, once the MOS channel turns on, it changes the potential distribution within the device, which further makes the body diode turn on at a source-to-drain voltage (VSD) much higher than the built-in potential of the pn junction. In 10 kV SiC MOSFETs, with the MOS channel on, the body diode does not turn on over the entire practical VSD range. As a result, the positive VGS leads to a completely unipolar conduction via the MOS channel, which could induce a higher VF3rd than the bipolar body diode at high temperatures. Circuit test is performed, which validates that a negative VGS control provides the smallest 3rd-quad voltage drop and conduction loss at high temperatures in 10 kV SiC planar MOSFET. The study is also extended to the trench MOSFET, another major structure of commercial SiC MOSFETs. Based on the revealed physics for planar MOSFETs, the optimal VGS control for the 3rd-quad conduction in different types of commercial trench MOSFETs is discussed, which provides insights for the design of high-voltage trench MOSFETs. These results provide key guidelines for the circuit applications of medium-voltage SiC power MOSFETs. / M.S. / Recent years, the prosperity of power electronics applications such as electric vehicle and smart grid has led to a rapid increase in the adoption of wide bandgap (WBG) power devices. Silicon Carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) is one of the most attractive candidates in WBG devices, owing to its good tradeoff between breakdown voltage and on resistance, capability of operation at high temperatures, and superior device robustness over other WBG power devices. In most power converters, power device is required to conduct current in its third quadrant (3rd-quad) (i.e., conduct reverse current) either for handling current during the dead time or acting as a commutation switch. In a SiC MOSFET, there are two current paths in the 3rd-quad conduction, namely the MOS channel path and the body diode path. It is widely accepted that by turning on the MOS channel with a positive gate-to-source bias (VGS), both paths are turned on in parallel such that the 3rd-quad conduction loss can be reduced. In this thesis work, it is shown that this long-held opinion does not hold for SiC MOSFETs with high voltage ratings (e.g., 3.3 kV and 10 kV). Through a combination of device characterization, TCAD simulation, and analytical modeling, this thesis work unveils the competing current sharing between the MOS channel and the body diode. Once the MOS channel turns on, it delays the turn-on of the body diode and suppresses the diode current. This effect is more pronounced in MOSFETs with higher voltage ratings. In 10 kV SiC MOSFETs, with the MOS channel on, the body diode does not turn on in the practical operation conditions. At high temperatures, as the bipolar diode path possesses the conductivity modulation, which can significantly lower the voltage drop and is absent in the MOS channel, it would be optimal to turn off the MOS channel. Circuit test is also performed to validate these device findings and evaluate their impact on device applications. Finally, the study is also extended to the commercial SiC trench MOSFET, the other mainstream type of SiC power MOSFETs. These results provide key guidelines for the circuit applications of medium-voltage SiC power MOSFETs.

Power device robustness refers to the device capability of withstanding abnormal events in power electronics applications, which is one of the key device capabilities that are desired in numerous applications. While the current robustness test methods and qualification standards are developed across the 70 years of Silicon (Si) device history, their applicability to the recent wide bandgap (WBG) power devices is questionable. While the market of WBG power devices has exceeded $1 billion and is fast growing, there are many knowledge gaps regarding their robustness, including the failure or degradation physics, testing methods, and lifetime extraction. This dissertation work studies the robustness of Gallium Nitride (GaN) power device. The structures of many GaN power devices are fundamentally different from Si or Silicon Carbide (SiC) power devices, leading to numerous open questions on GaN power device robustness. Based on the device structure, this dissertation is divided into two parts: The first half discusses the robustness of lateral GaN high electron mobility transistor (HEMT), which recently sees rapid adoption among wide range of applications such as the power adapter and chargers, data center, and photovoltaic panels. The absence of p-n junction between the source and drain of GaN HEMT results in the lack of avalanche mechanism. This raises a concern on the device capability of withstanding surge-energy or overvoltage stress, which hinders the penetration of GaN HEMTs in broader applications. To address this concern, the study begins with conducting the single-event unclamped inductive switching (UIS) test on two mainstream commercial p-gate GaN HEMTs with the Ohmic- and Schottky-type gate contacts, where the GaN HEMT is found to withstand surge energy through a resonant energy transfer between the device capacitance and the loop inductance. The failure mechanism is identified to be a pure electrical breakdown determined by device transient breakdown voltage (BV). The BV of GaN HEMT is further found to be "dynamic" from the switching tests with various pulse widths and frequencies, which is further explained by the time-dependent buffer trapping. This dynamic BV (BVDYN) phenomenon indicates that the static or single-pulse test may not reveal the true BV of GaN HEMT in high frequency switching applications. To address this gap, a novel testbed based on a zero-voltage-switching converter with an active clamping circuit is developed to enable the stable switching with kilovolt overvoltage and megahertz frequency. The overvoltage failure boundaries and failure mechanisms of four commercial p-gate GaN HEMTs from multiple vendors are explored. In addition to the frequency-dependent BVDYN, two new failure mechanisms are observed in some devices, which are attributable to the serious carrier trapping in GaN HEMTs under the high-frequency overvoltage switching. At last, based on the findings in the high frequency overvoltage test (HFOT), a physics-based lifetime model for commercial GaN HEMTs utilizing the device on resistance (RON) shift is established and validated by experimental results. Overall, the switching-based test methodology and experimental results provide critical references for the overvoltage protection and qualification of GaN power HEMTs. The second half of the dissertation discusses the robustness of the vertical GaN fin-channel junction field effect transistor (Fin-JFET), a promising pre-commercialized GaN power device with the p-n junction embedded between the gate and drain which enables the avalanche breakdown. The robustness study on GaN JFET follows similar test approaches as Si metal-oxide-semiconductor field-effect transistor (MOSFET) with two key interests: the avalanche and short circuit capabilities. The avalanche breakdown is first explored via the single-event and repetitive UIS tests and under various gate drivers, from which an interesting "avalanche-through-fin-channel" mechanism is discovered. By leveraging this avalanche path, the electro-thermal stress migrates from the main blocking p-n junction to the n-GaN fin channel, resulting in a very favorable failure-to-open-circuit signature. The single-pulse critical avalanche energy density (EAVA) of vertical GaN Fin-JFET is measured to be as high as 10 J/cm2, which is much higher than the Si MOSFET and comparable to the SiC MOSFET. The short circuit capability is explored utilizing the hard-switching fault on the 650-V rated GaN Fin-JFET, with a gate driving circuit identical to the switching application to best mimic device operation in converters. The short circuit withstanding time is measured to be 30.5 µs at an input voltage of 400 V, 17.0 µs at 600 V, and 11.6 µs at 800 V, all among the longest reported for 600-700 V normally-off transistors. In addition, the failure-to-open-circuit signature is also shown in the single-event and repetitive short circuit tests; all devices retain the avalanche breakdown after failure, which is highly desirable for system applications. These results suggest that, while GaN HEMT is already available in market, vertical GaN Fin-JFET shows superior avalanche and short-circuit robustness and thereby can unlock great potential of GaN devices for applications like automotive powertrains, motor drives, and grids. / Doctor of Philosophy / In recent years, many power electronics applications such as data centers and electric vehicles have witnessed a rapid increase in the adoption of wide bandgap (WBG) power devices. The Gallium Nitride (GaN) device is one of the most attractive candidates in WBG devices, owing to its good tradeoff between breakdown voltage and on resistance, as well as the small gate charge that enables high frequency switching. For power devices, their robustness against overvoltage and overcurrent stresses is as important as their performance under normal operations. However, the new material, new device structure, and new device physics in GaN power devices brought up many open knowledge gaps in their robustness study, particularly under the dynamic operation in switching circuits. This dissertation presents the work in exploring the robustness of GaN power devices. Based on the device structure, the discussion is divided in two parts: The first half of the dissertation focuses on the overvoltage robustness of the lateral GaN High Electron Mobility Transistor (HEMT), the commercially available device covering 30 to 900 V voltage classes. A key feature of this device is the lack of p-n junction between source and drain, leading to an absence of avalanche capability. The study is conducted on mainstream, commercial p-gate GaN HEMTs, with a combination of circuit testing, microscale failure analysis, and physics-based device simulation. The main contribution is on three aspects: identifying the single-event and high-frequency repetitive overvoltage boundaries of GaN HEMT, unveiling the failure and degradation mechanisms under transient overvoltage conditions, and providing guidelines to GaN HEMT device users with proper robustness test methodology for device qualification and screening. The second half of the dissertation focuses on the robustness of vertical GaN fin-channel junction field effect transistor (Fin-JFET), a promising pre-commercial GaN power device with the p-n junction implemented between the source and drain. The robustness tests follow the classic approaches deployed for Silicon power devices, where both the avalanche and short circuit capabilities are investigated. From the single-event and repetitive test results, the GaN JFET shows excellent avalanche robustness with a desirable failure-to-open-circuit behavior, as well as a critical avalanche energy (EAVA) of 10 J/cm2 that is higher than the Silicon metal-oxide-semiconductor field-effect transistor (MOSFET) and comparable to the Silicon Carbide MOSFET. For a 650-V rated GaN Fin-JFET, a record high 30.5 μs short circuit time is demonstrated under the hard-switching fault condition at 400 V input voltage. Overall, the results show great potential of GaN power devices for the power electronics applications that involve more stressful operation conditions for devices.

Power electronics plays an important role in many energy conversion applications in modern society including consumer electronics, data centers, electric vehicles, and power grids, etc. The key components of power electronic circuits are power semiconductor devices including diodes and transistors, which determine the performance of power electronics circuits. Traditional power devices are based on the semiconductor silicon (Si), which have already reached the silicon's material limit. Gallium nitride (GaN) is a wide bandgap semiconductor with high electron mobility and high critical electric field. GaN-based power devices promise superior device performance over the Si-based counterpart. The primary design target of a unipolar power device is to achieve low on-resistance and high breakdown voltage. Although GaN high electron mobility transistor (HEMT) is commercially available in a voltage class from 15 V to 900 V, the performance of GaN devices is still far below the GaN material limit, due to several reasons: 1) To achieve the normally-off operation in a GaN HEMT, the density of two-dimensional electron gas (2DEG) channel cannot be too high; this limits the on-resistance reduction in the access region. 2) The gate capacitance of GaN HEMT is usually low so that the carrier concentration in the channel underneath the gate is relatively low, limiting the on-resistance reduction in the gated channel region. 3) The electric-field distribution in the drift region is not uniform, resulting in a limited breakdown voltage. We proposed to use the junction-based structure in GaN power devices to address the above problems and fully exploit GaN's material properties. The first part of this dissertation characterizes nickel oxide (NiO) as a p-type material to construct the junction-based GaN power devices. Although the homogenous p-GaN/n-GaN junction is preferred in many devices, the selective-area, p-GaN regrowth can lead to excessive leakage current; in comparison, the p-NiO/n-GaN junction is stable without leakage. This section describes the optimization of NiO deposition as well as the NiO characterization. Although acceptor in NiO is not generated by impurity doping, the acceptor concentration modulation is realized by tuning the O2 partial pressure during the sputtering process. Practical breakdown electric field is also characterized and confirmed to be higher than GaN. These results provide the design guidelines for NiO-GaN junction-based power devices. The second part of this dissertation demonstrates the 3D NiO-GaN junction gate to improve the GaN HEMT's on-resistance. The 3D junction gate structure enables a high carrier concentration under the gate region in the device on-state. Meanwhile, the strong depletion effect of the junction-based gate allows for a robust normally-off operation; as a result, the GaN wafer with a higher 2DEG concentration can be used to achieve both normally-off and low on-state resistance in HEMT devices. Simulation is also performed to project the performance space of trigate GaN junction HEMTs using the p-GaN instead of NiO. The third part of this dissertation presents the application of the p-GaN/n-GaN junction in the drift region of the multi-channel lateral devices to achieve the high breakdown voltage. Here p-GaN is grown in-situ with the multi-channel AlGaN/GaN structure, and there is no leakage problem. The structure is designed to achieve charge balance between the acceptor in p-GaN and the net donor in the multichannel AlGaN/GaN. This design enables a uniform electric field distribution and breakdown voltage over 10 kV. The fourth part of this dissertation presents the application of the p-NiO/n-GaN junction in vertical superjunction (SJ) devices. We show the design and simulation of this heterojunction structure in a SJ and confirm the uniform electric field and high breakdown voltage under the charge balance. Then the device fabrication is presented in detail, which mainly comprises the deep GaN trench etch, NiO self-aligned lift off, and photoresist trench planarization. The optimized device shows a trade-off between its drift region specific on-resistance versus breakdown that exceeds the 1D GaN's limit. The last part of this dissertation is exploring the design and fabrication of p-GaN/n-GaN based SJ devices. First, the challenges in p-GaN regrowth especially the introduction of interface impurities are discussed, followed by device simulation and modeling to optimize the SJ performance considering these interface impurities. The activation of regrown p-GaN in deep trenches is more difficult than planar p-GaN, and we present the characterization and physical model for the activation of the deep buried p-GaN. Last, the results of p-GaN filling regrowth and the acceptor concentration calibration in the lightly doped p-GaN are presented and discussed. In summary, our work combines experimental device fabrication and characterization, TCAD simulation, and device modeling to demonstrate the benefit of multi-dimensional, junction-based GaN power devices as compared to the traditional GaN power devices. The junction-based structure at gate region can provides stable normally-off operation and low on-resistance. When being applied to the drift region, the multidimensional junction structure can push the device specific on-resistance versus breakdown voltage trade-off near or even exceeding the material limit. These results will advance the performance and application spaces of GaN power devices. / Doctor of Philosophy / Power electronics plays an important role in many energy conversion applications in modern society including consumer electronics, data centers, electric vehicles, and power grids, etc. The key components of power electronic circuits are power semiconductor devices including diodes and transistors, which determine the performance of power electronics circuits. Traditional power devices are based on the semiconductor silicon (Si), which have already reached the silicon's material limit. Gallium nitride (GaN) is a wide bandgap semiconductor with high electron mobility and high critical electric field. GaN-based power devices promise superior device performance over the Si-based counterpart. Currently, GaN power devices performance is still far below its material limit due to several reasons: 1) To achieve normally-off operation, the carriers at gate region need to be fully depleted at zero bias. Due to a relatively limited depletion capability of the planar gate, the normally-off operation poses an upper limit on the channel carrier density, which increases the device on-resistance. 2) The electric field distribution is not uniform when the device is blocking off-state voltage, and the crowded electric field will cause the device premature breakdown. This work proposed to use multi-dimensional, p-n junction-based device structure to overcome the above challenges. The devices with diverse structures are fabricated, characterized, and compared with the commercially available devices. The multi-dimensional, junction-based gate structure provides strong electrostatic control to realize normally-off operation and allow for higher carrier concentration and lower on-resistance. The devices with multi-dimensional, junction-based drift region enables the uniform electric field distribution at the device off-state, allowing devices to block high voltage without compromising the on-state resistance. Examples of such devices investigated in this dissertation include the tri-gate junction transistors, reduced-surface-field (RESURF) diodes, and superjunction diodes. In summary, this work demonstrates the multi-dimensional, junction-based device structure to overcome the performance limitations of planar devices and fully exploit GaN's material benefits for power devices. The multi-dimensional, junction-based devices are experimentally fabricated and characterized, manifesting the superior performance over traditional GaN devices. This work will significantly boost the performance and application space of GaN power devices.

The work deals with the capacitance measurement of high-voltage PN junctions. The work is divided into theoretical and practical parts. The theoretical part presents insight into the fundamental properties of PN junctions and methods for measuring of the capacitance of PN junctions, primarily by C-V measurement. In the practical part, several kinds of measuring circuits are introduced and a suitable method of measurement is found. The calculations of basic parameters - the width of the base and resistivity are presented and discussed. The results were compared with the values obtained by calculation from the technological parameters of the junction.

Power electronics, which fully covers the generation, conversion, transmission and usage of electrical energy, is a key technology for human welfare. With the development of technologies, the requirements on the reliability of power electronic systems are keep increasing. Long term operation under harsh environments is often accompanied by higher switching frequency and higher power density. To allow a reliable and sustainable performance of the power electronic systems, precise lifetime estimation of the power semiconductor devices is of significant importance. This work covers some aspects in the lifetime prediction of power semiconductor devices, especially IGBT and diode, in power module and transfer-molded discrete package. Difference in device temperature determination was illustrated using analytical calculation, simulation and measurement. In addition, temperature calculation in the frequency domain was demonstrated which gives benefits in the application with several hundred devices. Furthermore, different control strategies in the power cycling test were compared. The linear cumulative damage theory was validated by using the power cycling test. For the high power IGBT module used in the MMC HVDC application, power cycling lifetime with 50 Hz heating processes was investigated. For the transfer-molded discrete package, the first lifetime model with comparable scope like the lifetime model of power modules was proposed. / Leistungselektronik, welche direkt relevant für die Erzeugung, Umwandlung, Übertragung und Nutzung elektrischer Energie ist, ist eine Schlüsseltechnologie für das Wohl der Menschen. Mit der Entwicklung von Technologien steigen die Anforderungen an die Zuverlässigkeit leistungselektronischer Systeme. Der Langzeitbetrieb unter rauen Umgebungsbedingungen geht häufig mit einer höheren Schaltfrequenz und einer höheren Leistungsdichte einher. Um eine zuverlässige und nachhaltige Operation der leistungselektronischen Systeme zu ermöglichen, ist die genaue Lebensdauerabschätzung der Halbleiter-Leistungsbauelemente von großer Bedeutung. Diese Arbeit befasst sich mit einigen Aspekten der Lebensdauerabschätzung von den Halbleiter-Leistungsbauelementen. Unterschied in der Temperaturabstimmung der Halbleiter-Leistungsbauelemente wird anhand von Berechnung, Simulation und Messung veranschaulicht. Darüber hinaus bietet die Temperaturberechnung im Frequenzbereich Vorteile bei der Anwendung mit mehreren hundert Bauelementen. Darüber hinaus wurden verschiedene Regelstrategien im Lastwechseltest verglichen. Die lineare kumulative Alterungstheorie wurde unter Verwendung des Lastwechseltests validiert. Für das in der MMC-HGÜ-Anwendung verwendete Hochleistungs-IGBT-Modul wurden Alterungsprozesse bei 50 Hz Erwärmung untersucht. Für das Diskrete-Gehäuse wird das erste Lebensdauermodell vorgestellt, welches ein vergleichbares Anwendungsbereich wie das Lebensdauermodell von Leistungsmodulen hat.

Cette thèse présente l'étude et la réalisation d'un disjoncteur statique tout silicium et intelligent pouvant fonctionner à haute température (200°C) pour des applications de type DC basse et moyenne tensions. Plusieurs applications dans l’aéronautique, l’automobile et les transports ferroviaires poussent les composants à semi-conducteur de puissance à être utilisés à haute température. Cependant, les Si-IGBT et Si-CoolMOSTM actuellement commercialisés ont une température de jonction spécifiée et estimée à 150°C et quelque fois à 175°C. L’une des faiblesses des convertisseurs provient de la réduction du rendement avec l’augmentation de la température de jonction des composants à semiconducteur de puissance qui peut amener à leur destruction. La solution serait d’utiliser des composants grand-gap (SiC, GaN), qui autorisent un fonctionnement à une température de jonction plus élevée ;mais ces technologies en plein essor ont un coût relativement élevé. Une solution alternative serait de faire fonctionner des composants en silicium à une température de jonction voisine de 200°C afin de conserver l’un des principaux intérêts du silicium en termes de coût. Avant de commencer, le premier chapitre portera sur un état de l’art des différentes techniques de protection aussi bien mécanique que statique afin d’identifier les éléments essentiels pour la réalisation du circuit de protection. Les disjoncteurs hybrides seront aussi abordés afin de voir comment ceux-ci arrivent à combler les lacunes des disjoncteurs mécaniques et purement électroniques (statiques). A partir du chapitre précédent, un disjoncteur statique intelligent de faible puissance sera réalisé afin de mieux cerner les différentes difficultés qui sont liées à ce type de disjoncteur. Le disjoncteur statique sera réalisé à partir de fonction analogique de telle façon à ce qui soit autonome et bas cout. Il en ressort que les inductances parasites ainsi que la température des composants à base de semi-conducteurs ont un impact significatif lors de la coupure.Le chapitre III portera sur une analyse non exhaustive, vis-à-vis de la température, de différents types d’interrupteurs contrôlés à base de semi-conducteur de puissance en s’appuyant sur plusieurs caractérisations électriques (test de conduction, tension de seuil, etc) afin de sélectionner le type d’interrupteur de puissance qui sera utilisé pour le chapitre IV. Comme il sera démontré, les composants silicium à super jonction peuvent se rapprocher du comportement des composants à base de carbure de silicium pour les basses puissances. Un disjoncteur statique 400V/63A (courant de court-circuit prédictible de 5kA) sera étudié et 4développé afin de mettre en pratique ce qui a été précédemment acquis et pour montrer la compétitivité du silicium pour cette gamme de puissance. / This thesis presents a study about a smart solid state circuit breaker which can work at 200°C forlow and medium voltage continuous applications. Some applications in aeronautics, automotive,railways, petroleum extraction push power semiconductor devices to operate at high junctiontemperature. However, current commercially available Si-IGBT and Si-CoolMOS have basically amaximum junction temperature specified and rated at 150°C and even 175°C. Indeed, the main problemin conventional DC-DC converters is the switching losses of power semiconductor devices (linked to thetemperature influence on carrier lifetime, on-state voltage, on-resistance and leakage current) whichdrastically increase with the temperature rise and may drive to the device failure. Then, the use of wideband gap semiconductor like SiC or GaN devices allows higher junction temperature operation (intheory about 500°C) and higher integration (smaller heatsink, higher switching frequency, smallconverter), but are still under development and are expensive technologies. In order to keep theadvantage of low cost silicon devices, a solution is to investigate the feasibility to operate such devicesat junction temperature up to 200°C.Before starting the first starting chapter is a stat of the art of protectives circuit technics as well asmechanics as statics in order to identify essentials elements to develop the protective circuit. Hybridprotective circuits are approached too.From the precedent chapter, a smart and low power solid state circuit breaker is realized to identifyproblems which are linked with this type of circuit breaker. Solid state circuit breaker is developed withanalog components in a way that is autonomous and low cost. It’s follow that stray inductance andtemperature have an important impact when a default occurs.Chapter III give an analyze on different silicon power semiconductor dice towards temperature5relying on statics and dynamics characteristics in order to find the best silicon power switch which beused in the chapter IV. It has been shown that super junction MOSFET has the same behavior at lowpower than silicon carbide MOSFET.Solid state circuit breaker (400V/63A) has been studied and developed, in order to use all theknowledge previously acquired and to show the competitively of the silicon for this power range.

<div>Power semiconductor devices play an important role in many areas, including household</div><div>appliances, electric vehicles, high speed trains, electric power stations, and renewable energy</div><div>conversion. In the modern era, silicon based devices have dominated the semiconductor</div><div>market, including power electronics, because of their low cost and high performance. The</div><div>applications of devices rated 600 V - 6.5 kV are still dominated by silicon devices, but they</div><div>are nearly reaching fundamental material limits. New wide band gap materials such as silicon</div><div>carbide (SiC) offer significant performance improvements due to superior material properties</div><div>for such applications in and beyond this voltage range. 4H-SiC is a strong candidate</div><div>among other wide band gap materials because of its high critical electric field, high thermal</div><div>conductivity, compatibility with silicon processing techniques, and the availability of high</div><div>quality conductive substrates.</div><div>Vertical DMOSFETs and insulated gate bipolar transistors (IGBT) are key devices for</div><div>high voltage applications. High blocking voltages require thick drift regions with very light</div><div>doping, leading to specific on-resistance (R_ON,SP ) that increases with the square of blocking</div><div>voltage (V_BR). In theory, superjunction drift regions could provide a solution because of a</div><div>linear dependence of R_ON,SP on V_BR when charge balance between the pillars is achieved</div><div>through extremely tight process control. In this thesis, we have concluded that superjunction</div><div>devices inevitably have at least some level of charge imbalance which leads to a quadratic</div><div>relationship between V_BR and R_ON,SP . We then proposed an optimization methodology to</div><div>achieve improved performance in the presence of this inevitable imbalance.</div><div>On the other hand, an IGBT combines the benefits of a conductivity modulated drift</div><div>region for significantly reduced specific on-resistance with the voltage controlled input of a</div><div>MOSFET. Silicon carbide n-channel IGBTs would have lower conduction losses than equivalent</div><div>DMOSFETs beyond 6.5 kV, but traditionally have not been feasible below 15 kV. This</div><div>is due to the fact that the n+ substrate must be removed to access the p+ collector of the</div><div>IGBT, and devices below 15 kV have drift layers too thin to be mechanically self-supporting.</div><div>In this thesis, we have demonstrated the world’s first functional 10 kV class n-IGBT with</div><div>a waffle substrate through simulation, process development, fabrication and characterization.</div><div><div>The waffle substrate would provide the required mechanical support for this class of devices.</div><div>The fabricated IGBT has exhibited a differential R_ON,SP of 160 mohm</div><div>.cm², less than half of</div><div>what would be expected without conductivity modulation. An extensive fabrication process</div><div>development for integrating a waffle substrate into an active IGBT structure is described</div><div>in this thesis. This process enables an entirely new class of moderate voltage SiC IGBTs,</div><div>opening up new applications for SiC power devices.</div></div>

Advances in wide-bandgap semiconductor devices have increased the allowable operating temperature of power electronic systems. High-temperature devices can benefit applications such as renewable energy, electric vehicles, and space-based power electronics that currently require bulky cooling systems for silicon power devices. Cooling systems can typically be reduced in size or removed by adopting wide-bandgap semiconductor devices, such as silicon carbide. However, to do this, semiconductor device packaging with high reliability at high temperatures is necessary. Transient liquid phase (TLP) die-attach has shown in literature to be a promising bonding technique for this packaging need. In this work TLP has been comprehensively investigated and characterized to assess its viability for high-temperature power electronics applications. The reliability and durability of TLP die-attach was extensively investigated utilizing electrical resistivity measurement as an indicator of material diffusion in gold-indium TLP samples. Criteria of ensuring diffusive stability were also developed. Samples were fabricated by material deposition on glass substrates with variant Au–In compositions but identical barrier layers. They were stressed with thermal cycling to simulate their operating conditions then characterized and compared. Excess indium content in the die-attach was shown to have poor reliability due to material diffusion through barrier layers while samples containing suitable indium content proved reliable throughout the thermal cycling process. This was confirmed by electrical resistivity measurement, EDS, FIB, and SEM characterization. Thermal and mechanical characterization of TLP die-attached samples was also performed to gain a newfound understanding of the relationship between TLP design parameters and die-attach properties. Samples with a SiC diode chip TLP bonded to a copper metalized silicon nitride iv substrate were made using several different values of fabrication parameters such as gold and indium thickness, Au–In ratio, and bonding pressure. The TLP bonds were then characterized for die-attach voiding, shear strength, and thermal impedance. It was found that TLP die-attach offers high average shear force strength of 22.0 kgf and a low average thermal impedance of 0.35 K/W from the device junction to the substrate. The influence of various fabrication parameters on the bond characteristics were also compared, providing information necessary for implementing TLP die-attach into power electronic modules for high-temperature applications. The outcome of the investigation on TLP bonding techniques was incorporated into a new power module design utilizing TLP bonding. A full half-bridge inverter power module for low-power space applications has been designed and analyzed with extensive finite element thermomechanical modeling. In summary, TLP die-attach has investigated to confirm its reliability and to understand how to design effective TLP bonds, this information has been used to design a new high-temperature power electronic module.

NASA missions require innovative power electronics system and component solutions with long life capability, high radiation tolerance, low mass and volume, and high reliability in space environments. Presently vertical double-diffused MOSFETs (VDMOS) are the most widely used power switching device for space power systems. It is proposed that a new lateral double-diffused MOSFET (LDMOS) designed at UCF can offer improvements in total dose and single event radiation hardness, switching performance, development and manufacturing costs, and total mass of power electronics systems. Availability of a hardened fast-switching power MOSFET will allow space-borne power electronics to approach the current level of terrestrial technology, thereby facilitating the use of more modern digital electronic systems in space. It is believed that the use of a p+/p-epi starting material for the LDMOS will offer better hardness against single-event burnout (SEB) and single-event gate rupture (SEGR) when compared to vertical devices fabricated on an n+/n-epi material. By placing a source contact on the bottom-side of the p+ substrate, much of the hole current generated by a heavy ion strike will flow away from the dielectric gate, thereby reducing electrical stress on the gate and decreasing the likelihood of SEGR. Similarly, the device is hardened against SEB by the redirection of hole current away from the base of the device's parasitic bipolar transistor. Total dose hardness is achieved by the use of a standard complementary metal-oxide semiconductor (CMOS) process that has shown proven hardness against total dose radiation effects.

Wide bandgap (WBG) semiconductor devices are becoming increasing popular in power electronics applications. However, WBG semiconductor devices generate a substantial amount of conducted electromagnetic interference (EMI) compared to silicon (Si) devices due to their ability to operate at higher switching frequencies, higher operating voltages and faster slew rates. This thesis explores and analyzes EMI mitigation techniques that can be applied to a power module architecture at the packaging level. In this thesis, the EMI footprint of four different module architectures is measured experimentally. A time domain LTspice simulation model of the experimental test setup is then built. The common mode (CM) EMI emissions that escape the baseplate of the module into the converter is then examined through the simulation. The simulation is used to explore the CM noise footprint of eight additional module architectures that were found in literature. The EMI trends and the underlying mitigation principle for the twelve modules is explained by highlighting key differences in the architectures using common mode equivalent modelling and substitution and superposition theorem. The work aims to help future module designers by not only comparing the EMI performance of the majority of module architectures available in literature but by also providing an analysis methodology that can be used to understand the EMI behavior of any new module architecture that has not been discussed. Although silicon carbide (SiC) modules are used for this study, the results are applicable for any WBG device. / M.S. / As society moves towards the electric grid of the future, there have been increasing calls for high efficiency, high power density, and low electromagnetic interference (EMI) power electronic converters. EMI is a big problem when using wide-bandgap (WBG) devices as these devices can switch very quickly and handle higher voltages when compared to silicon devices. In this study, ways to reduce EMI in a WBG power module through twelve different types of packaging are explored. Four WBG power modules are designed and fabricated in the lab, whereas a simulation model was created to study the EMI behavior of the remaining eight power module. The EMI behavior of these modules is explained using common mode (CM) equivalent modeling and substitution and superposition theorem. This study is important because WBG devices are becoming more and more popular in power electronic applications. The author hopes the findings and analysis presented in this paper can help future module designers reduce the EMI footprint of modules they design.