Low drop out (LDO) voltage regulators are widely used for post regulating the switching ripples generated by the switched mode power supplies (SMPS). Due to demand for portable applications, industry is pushing for complete system on chip power management solutions. Hence, the switching frequencies of the SMPS are increasing to allow higher level of integration. Therefore, the subsequent post-regulator LDO must have good power supply rejection (PSR) up to switching frequencies of SMPS. Unfortunately, the conventional LDOs have poor PSR at high frequencies. The objective of this research is to develop novel LDO regulators that can achieve good high frequency PSR performance. In this thesis, two PSR improvement methods are presented. The first method proposes a novel power supply noise-cancelling scheme to improve the PSR of an external-capacitor LDO. The proposed power supply noise-cancelling scheme is designed using adaptive power consumption, thereby not degrading the power efficiency of the LDO. The second method proposes a feed forward ripple cancellation technique to improve the PSR of capacitor-less LDO; also a dynamically powered transient improvement scheme has been proposed. The feed forward ripple cancellation is designed by reusing the load transient improvement block, thus achieving the improvement in PSR with no additional power consumption. Both the projects have been designed in TSMC 0.18 μm technology. The first method achieves a PSR of 66 dB up to 1 MHz where as the second method achieves a 55 dB PSR up to 1 MHz.

Low Dropout Regulators (LDOs) are extensively used in portable applications like mobile phones, PDAs and notebooks. These portable applications demand high power efficiency and low output voltage ripple. In addition to these, the radio circuits in these applications demand high power supply rejection (PSR). The output voltage of a conventional DC/DC converter (generally switched mode) has considerable ripple which feeds as input to these LDOs. And the challenge is to suppress these ripples for wide range of frequencies (for radio units) to provide clean supply. Enhanced buffer based compensation is proposed for the fully on-chip CMOS LDO which stabilizes the loop for different load conditions as well as improve the power supply rejection (PSR) until frequencies closer to open loop‟s unity-gain frequency. The stability and PSR are totally valid even for load capacitor varying from 0 to 100 pF. The proposed capacitor-less LDO is fabricated in On-Semi 0.5 μm fully CMOS process. Experimental results confirm a PSR of -30 dB till 420 KHz for the maximum load current of 50mA. The load transients of the chip shows transient glitches less than 90 mV independent of output capacitance.

Test power is an important issue in deep submicron semiconductor testing. Too much power supply noise and too much power dissipation can result in excessive temperature rise, both leading to overkill during delay test. Scan-based test has been widely adopted as one of the most commonly used VLSI testing method. The test power during scan testing comprises shift power and capture power. The power consumed in the shift cycle dominates the total power dissipation. It is crucial for IC manufacturing companies to achieve near constant power consumption for a given timing window in order to keep the chip under test (CUT) at a near constant temperature, to make it easy to characterize the circuit behavior and prevent delay test over kill. To achieve constant test power, first, we built a fast and accurate power model, which can estimate the shift power without logic simulation of the circuit. We also proposed an efficient and low power X-bit Filling process, which could potentially reduce both the shift power and capture power. Then, we introduced an efficient test pattern reordering algorithm, which achieves near constant power between groups of patterns. The number of patterns in a group is determined by the thermal constant of the chip. Experimental results show that our proposed power model has very good correlation. Our proposed X-Fill process achieved both minimum shift power and capture power. The algorithm supports multiple scan chains and can achieve constant power within different regions of the chip. The greedy test pattern reordering algorithm can reduce the power variation from 29-126 percent to 8-10 percent or even lower if we reduce the power variance threshold. Excessive noise can significantly affect the timing performance of Deep Sub-Micron (DSM) designs and cause non-trivial additional delay. In delay test generation, test compaction and test fill techniques can produce excessive power supply noise. This can result in delay test overkill. Prior approaches to power supply noise aware delay test compaction are too costly due to many logic simulations, and are limited to static compaction. We proposed a realistic low cost delay test compaction flow that guardbands the delay using a sequence of estimation metrics to keep the circuit under test supply noise more like functional mode. This flow has been implemented in both static compaction and dynamic compaction. We analyzed the relationship between delay and voltage drop, and the relationship between effective weighted switching activity (WSA) and voltage drop. Based on these correlations, we introduce the low cost delay test pattern compaction framework considering power supply noise. Experimental results on ISCAS89 circuits show that our low cost framework is up to ten times faster than the prior high cost framework. Simulation results also verify that the low cost model can correctly guardband every path‟s extra noise-induced delay. We discussed the rules to set different constraints in the levelized framework. The veto process used in the compaction can be also applied to other constraints, such as power and temperature.

The first topic of this thesis is a novel NTSC video sync separator (NSS) with a high-PSR (power supply rejection) bias generation circuitry (BGC) comprising a temperature compensation circuitry. The proposed BGC is composed of step-down regulators and a bandgap-based bias with cascode current control. The clamping voltages required for sync separation from an NTSC signal are generated. The second topic is a temperature-compensated 6th order transconductance-C (Gm-C) anti-aliasing filter (AAF) with digitally tunable bandwidth which can be applied in the analog front-end circuit of DVB-T receivers. The proposed AAF is controlled by digital signals to provide three different baseband bandwidth (6, 7, 8 MHz) selection. A regulator with a bandgap circuitry supplies a stable voltage to suppress the variations of power and temperature. Moreover, a temperature -compensated circuitry is used to neutralize bandwidth drifting caused by the temperature variation. The bandwidth accuracy of the proposed design verified by HSPICE post-layout simulations is better than 3.28% at every PVT (process, supply voltage, temperature) corner. It is adequate for the DVB-T receivers¡¦ baseband processing.

This paper design a Digital-Singal-Processor based which cooperating with the technique of switching power supply to implement the Brushless DC motor driver for electric vehicle ,and use the asymmetry pulse-width modulation theorem in sinusoidal PWM switch to increase motion efficiency of motor and decrease the power depletion ,thus can improve the current- spike from analog controller effectively ,and prove the feasibility of the system.

Abstract This study is to investigate the status quo and relationship between R&D-Marketing integration in the product innovation process and organizational performance. Based on the company registered in 2003, a target population composed of 259 Switching Power Supply(SPS¡^companies is formed. Questionnaires were completed by managers responsible for marketing or R&D-Marketing departments. E-mail survey were employed to collect the data and use correlation analysis, one-way ANOVA and hierarchical regression analysis to analysis the data. It is found that the organizational factors variations exist in the integration of department and have positive influence on various activities when perpetual department was established and the manager is responsible for both marketing and R&D-Marketing department. Moreover, the result of research shows organizational factors have positive influence on department integration, and the mutual participation of members is most important. Besides, organizational factors will affect financial performance and program accomplish by integration of R&D-Marketing respectively of organizational category and chief factor. Based on the research findings, the perpetual department for developing new product and co-operated managers are suggested. In addition, mutual participation of members and establishing information network and database to reduce the gap of information between two departments deserve more attention so that the new product¡¦s performance could be improved. Keywords : switching power supply , new product development, department integration, organizational performance

Die Entflechtung der Netze von den liberalisierten Bereichen der Energieversorgungsunternehmen (EVU) spiegelt sich in der Staatsaufsicht wider: Die liberalisierten Tätigkeitsbereiche werden dem freien Spiel der Kräfte ausgesetzt und unterliegen im Falle von Marktmacht der kartellrechtlichen Missbrauchsaufsicht. Demgegenüber wird der Netzbetrieb vollumfänglich und ausschließlich durch die Regulierungsbehörden überwacht. Trotz wesentlicher Unterschiede haben beide Formen der Staatsaufsicht die Funktion, unternehmerisches Handeln derart zu lenken, dass ein effektiver Wettbewerb im Energiemarkt möglich ist. Mit dem Ziel der Wettbewerbsförderung wird das Energierecht ständig Reformplänen unterzogen, ohne dass der Verordnungsgeber bereits bestehenden Konkretisierungsaufträgen umfassend nachkommen konnte. Unter Berücksichtigung der ausstehenden Rechtsverordnungen müssen Reformen ein angemessenes Verhältnis von staatlicher Steuerung und unternehmerischer Freiheit beachten. / Government supervision reflects the ongoing segregation of the distribution networks from the liberalised sectors of the power supply industry: The latter are exposed to full competition and are subject to the control of abusive practices by competition authorities. The networks, however, are controlled fully and exclusively by regulatory authorities. Despite their substantial differences, both forms of supervision are aimed at directing business activities to ensure effective competition on the energy markets. To promote competition, energy law is undergoing constant reform, but the required ordinances are yet to be enacted. New reform ideas should consider the outstanding ordinances and maintain an appropriate balance between government supervision and corporate freedom.

As process technologies continue their rapid advancement, transistor features are shrinking to almost unimaginable sizes. Some dimensions can be measured at the atomic level. One consequence of these smaller devices is that they have become more susceptible to deviations from nominal than previous process nodes. To illustrate, as few as one hundred atoms determine how much voltage is needed to turn a transistor on and off. With over two billion transistors on a single chip, it is easy to imagine how even the tiniest of variations can affect many transistors throughout the entire chip. To compensate for these deviations, chip designers add margin to their designs. Even more margin is then added for increased safety. All of this margin leads to chips that are slower than a nominal design would be. At the other end of the spectrum, these same deviations might result in chips that are faster than needed. However, faster is not always better, as these faster chips usually require more power. Even worse, these deviations sometimes produce chips that are both slower and use more power than a nominal design. TuneChip is designed to mitigate the effects of these process variations by speeding up areas of a chip that need to run faster while at the same time reducing power in parts of a chip that are operating faster than needed. TuneChip attacks the variation problem by changing the voltage on small areas of the chip in response to the type of variation for that particular area. Since voltage has a strong relationship to the speed of a chip, TuneChip can increase the speed of areas that need to go faster. At the same time, TuneChip can decrease the speed of other areas on the chip that are too fast. Even more important than speed for current designs, though, is power. Changing the voltage has a quadratic relationship with the amount of power consumed by that device. Specifically, a 10% reduction in supply voltage yields a 20% reduction in energy. Moreover, it is not only battery powered devices that benefit from reduced energy consumption; some high performance designs are limited by how much they can cool the chip. Cost-effective cooling technology is not scaling at anywhere near the same rate as transistor geometries. Reducing a chip’s power consumption also reduces excess heat. In order to selectively change the voltage of specific areas of the design, TuneChip starts by partitioning the chip into smaller blocks. A dual voltage design style with two voltage grids spans the entire chip. In order to best react to variations particular to an individual chip, each block is assigned a supply voltage only after manufacturing. First, the chip is tested at high voltage and high power in order to verify the correct functionality of that chip. If the chip passes its functionality testing, each individual block is tested to determine how fast it is operating. Blocks that need to run faster are configured to connect to the high supply voltage grid, and blocks that are able to run slower are configured to connect to the low supply voltage grid. The configurable block supply voltage connection is accomplished with pmos pass transistors that act like switches. By having only one pmos pass transistor switch turned on at a time, each block has a choice of two supply voltages. / text

published_or_final_version / Electrical and Electronic Engineering / Doctoral / Doctor of Philosophy

Η παρούσα διπλωματική εργασία πραγματεύεται τη θεωρητική ανάλυση και προσομοίωση διάταξης φόρτισης ηλεκτροχημικών συσσωρευτών για ηλεκτροκίνητο όχημα καθώς και την κατασκευή της για την πειραματική απόδειξη της ορθής λειτουργίας της. / This thesis deals with the theoritical analysis and simulation of power supply for electric vehicle and the construction for experimental evidence for the proper functioning of the power supply.