On-chip supply voltage fluctuations are known to adversely affect performance parameters of VLSI circuits. These power supply fluctuations reduce drive capability, causes reliability issues, decrease noise margin and also adversely affect timing. Technology scaling further aggravates the problem as IR and Ldi/dt noise sources increase with each device generation. Current method used to reduce power supply variations uses an on-chip decoupling capacitors (decaps). These MOS capacitors utilize significant die area with about 15%-20% common for high-end microprocessors [4]. They also consume a considerable amount of power due to leakage and are prone to oxide breakdown during an ESD event because of reduced oxide thickness, making MOS capacitors unsuitable for technologies 90 nm and below. To improve the effectiveness of decap and reduce decap’s area, a new active decap design is proposed for 90 nm technology.

Master of Science

The design of an active-unity power factor correction circuit with variable-hysteresis control for off-line dc-to-dc switching power supplies is described. Design equations relating the boost inductor current ripple to the circuit components selection and circuit performance arc discussed. A computer-aided design program (CADO) is developed to give the optimal circuit components selection. A 500 watt, 300 volt experimental circuit is built to verify the simulation and analysis results. The control-to-output response of the power factor circuit is verified with the experimental results. Design guidelines for the low-frequency feedback network are presented. Small-signal closed-loop responses are measured with an experimental power factor circuit. / Master of Science

This study presents a methodology and the necessary analytical tools to evaluate the alternatives to provide Internet access with embedded power generation in remote areas. The objective is to provide a screening tool for policy makers to analyze possible telecom and power alternatives. Results from the study demonstrate the technical alternatives to providing sustainable Internet and power access. The dissertation investigates innovative telecom technologies currently available on the market, and develops a model that generates a Telecom-and-Internet access map of a region or a small country. The map illustrates the combination of technologies and their locations that can provide wide-area Internet access to cover a majority of the population at the least cost. The model then looks at the design of a small-scale power system for a remote location where grid power is unavailable or unreliable. The methodology takes into account locally available energy resources, technical and economic parameters of each power generating technology, and the trade-off among investment costs, environmental costs and system robustness. Lastly, a computer simulation is conducted to verify that the power system design has the ability to meet the demand at the level of required reliability. A remote area of a developing country (Chittagong and Chittagong Hill Tracts - Bangladesh) is selected as a case study. Several scenarios are simulated in order to explore the possibility of extending the reach of the Internet and electric power to the remote area, and to conceptualize pilot projects as building blocks to build a countrywide infrastructure. Since the selected area is one of the least developed and most difficult to access in Bangladesh, demonstrating that the Internet and local power access can be provided to this area can serve as a model for similar places around the world. / Ph. D.

A new method for small-signal analysis of switching power converters is developed and implemented in a computer program. The method is derived for systems where the nonlinearities can be described by elements that can take on one of two values, based upon a controlling variable. Another requirement is that the system be periodic. The method is shown by examples to be very accurate, even at high frequencies. It predicts the subharmonic oscillation that can occur in converters with constant-frequency current-mode control. It is implemented using the COSMIR program to solve for the state equations and for steady-state, making a general power supply simulation program. / Ph. D.

The growing demand for high voltage, compact pulsed power supplies has gained great attention. It requires power supplies with high power density, low profile and high efficiency. In this thesis, topologies and techniques are investigated to meet and exceed these challenges. Non-isolation type topologies have been used for this application. Due to the high voltage stress of the output, non-isolation topologies will suffer severe loss problems. Extremely low switching frequency will lead to massive magnetic volume. For non-isolation topologies, PWM converters can achieve soft switching to increase switching frequency. However, for this application, due to the large voltage regulation range and high voltage transformer nonidealities, it is difficult to optimize PWM converters. Secondary diode reverse recovery is another significant issue for PWM techniques. Resonant converters can achieve ZCS or ZVS and result in very low switching loss, thus enabling power supplies to operate at high switching frequency. Furthermore, the PRC and LCC resonant converter can fully absorb the leakage inductance and parasitic capacitance. With a capacitive output filter, the secondary diode will achieve natural turn-off and overcome reverse recovery problems. With a three-level structure, low voltage MOSFETs can be applied for this application. Switching frequency is increased to 200 kHz. In this paper, the power factor concept for resonant converters is proposed and analyzed. Based on this concept, a new methodology to measure the performance of resonant converters is presented. The optimal design guideline is provided. A novel constant power factor control is proposed and studied. Based on this control scheme, the performance of the resonant converter will be improved significantly. Design trade-offs are analyzed and studied. The optimal design aiming to increase the power density is investigated. The parallel resonant converter is proven to be the optimum topology for this application. The power density of 31 W/inch3 can be achieved by using the PRC topology with the constant power factor control. / Master of Science

Power supply noise has become a critical issue for low power and high performance circuit design in recent years. The rapid scaling of the CMOS process has pushed the limit further and further in building low-cost and increasingly complex digital VLSI systems. Continued technology scaling has contributed to significant improvements in performance, increases in transistor density, and reductions in power consumption. However, smaller feature sizes, higher operation frequencies, and supply voltage reduction make current and future VLSI systems more vulnerable to power supply noise. Therefore, there is a strong demand for strategies to prevent problems caused by power supply noise. Design challenges exist in different design phases to reduce power supply noise. In terms of physical design, careful power distribution design is required, since it directly determines the quality of power stability and the timing integrity. In addition, power management, such as switching mode of the power gating technique, is another major challenge during the circuit design phase. A bad power gating switching strategy may draw an excessive rush current and slow down other active circuitry. After the circuit is implemented, another critical design challenge is to estimate power supply noise. Designers need to be aware of the voltage drop in order to enhance the power distribution network without wasting unnecessary design resources. However, estimating power supply noise is usually difficult, especially finding the circuit activity which induces the maximum supply noise. Blind search may be very time consuming and not effective. At post-silicon test, detecting power supply noise within a chip is also challenging. The visibility of supply noise is low since there is no trivial method to measure it. However, the supply noise measurement result on silicon is critical to debug and to characterize the chip. This dissertation focuses on novel circuit designs and design methodologies to prevent problems resulted from power supply noise in different design phases. First, a supply noise estimation methodology is developed. This methodology systematically searches the circuit activity inducing the maximum voltage drop. Meanwhile, once the circuit activity is found, it is validated through instruction execution. Therefore, the estimated voltage drop is a realistic estimation close to the real phenomenon. Simulation results show that this technique is able to find the circuit activity more efficiently and effectively compared to random simulation. Second, two on-chip power supply noise detectors are designed to improve the visibility of voltage drop during test phase. The first detector facilitates insertion of numerous detectors when there is a need for additional test points, such as a fine-grained power gating design or a circuit with multiple power domains. It focuses on minimizing the area consumption of the existing detector. This detector significantly reduces the area consumption compared to the conventional approach without losing accuracy due to the area minimization. The major goal of designing the second on-chip detector is to achieve self-calibration under process and temperature variations. Simulation and silicon measurement results demonstrate the capability of self-calibration regardless these variations. Lastly, a robust power gating reactivation technique is designed. This reactivation scheme utilizes the on-chip detector presented in this dissertation to monitor power supply noise in real time. It takes a dynamic approach to control the wakeup sequence according to the ambient voltage level. Simulation results demonstrate the ability to prevent the excessive voltage drop while the ambient active circuitry induces a high voltage drop during the wakeup phase. As a result, the fixed design resource, which is used to prevent the voltage emergency, can potentially be reduced by utilizing the dynamic reactivation scheme. / text

Functional electrical stimulation (FES) devices have direct applications in the realm of rehabilitation engineering, physiotherapy, occupational therapy and medicine for research, diagnostic and therapeutic purposes. This thesis presents a novel electrical stimulator for use in a FES system. The stimulator produces regulated current pulses using two switched mode power supplies (SMPS) in series. The first power stage - a flyback converter - steps up the supply voltage using primary side digital control. The second power stage is a buck converter with output current hysteretic control. An output switched capacitor circuit shapes the current pulses. All pulse variables are programmable and various pulses can be formed for virtually any FES application. Compared to previous FES devices, the pulses generated here are sharper, have faster rise time and the amplitude and temporal characteristics are more tightly regulated. A single channel prototype system is implemented and experimental results are shown.

Functional electrical stimulation (FES) devices have direct applications in the realm of rehabilitation engineering, physiotherapy, occupational therapy and medicine for research, diagnostic and therapeutic purposes. This thesis presents a novel electrical stimulator for use in a FES system. The stimulator produces regulated current pulses using two switched mode power supplies (SMPS) in series. The first power stage - a flyback converter - steps up the supply voltage using primary side digital control. The second power stage is a buck converter with output current hysteretic control. An output switched capacitor circuit shapes the current pulses. All pulse variables are programmable and various pulses can be formed for virtually any FES application. Compared to previous FES devices, the pulses generated here are sharper, have faster rise time and the amplitude and temporal characteristics are more tightly regulated. A single channel prototype system is implemented and experimental results are shown.

Power management components can be found in a host of different applications ranging from portable hand held gadgets to modern avionics to advanced medical instrumentations, among many other applications. Low-dropout (LDO) linear regulators are particularly popular owing to their: ease of use, low cost, high accuracy, low noise, and high bandwidth. With all its glory, however, it tends to underperform switched-mode power supplies (SMPS) when with comes to power conversion efficiency, although the later generates a lot of ripple at its output. With the growing need to improve system efficiency (hence longer battery life) without degrading system performance, many high end (noise sensitive) applications such as data converters, RF transceivers, precision signal conditioning, among others, use high efficiency SMPS with LDO regulators as post-regulators for rejecting the ripple generated by SMPS. This attribute of LDO regulators is known as power supply rejection (PSR). With the trend towards increasing switching frequency for SMPS, to minimize PC board real estate, it is becoming ever more difficult for LDO regulators to suppress the associate high frequency ripple since at such high frequencies, different parasitic components of the LDO regulator start to deteriorate its PSR performance. There have been a handful of different techniques suggested in the literature that can be used to achieve good PSR performance at higher frequencies. However, each of these techniques suffers from a number of drawbacks ranging from reduced efficiency to increased cost to increased solution size, and with the growing demand for higher efficiency and smaller power supplies, these techniques have their clear limitations. The objective of this research project is to develop a novel current-mode LDO regulator that can achieve good high frequency PSR performance without suffering from the afore mentioned drawbacks. The proposed architecture was fabricated using a proprietary 1.5 um Bipolar process technology, and the measurement results show a PSR improvement of 20dB (at high frequencies) over conventional regulators. Moreover, the proposed LDO regulator requires a small 15nF output capacitor for stability, which is far smaller than some of the currently used techniques.