In this thesis, two different processor designs, LEON3 microcontroller and ADSP-218x digital signal processor, are integrated in an AMBA-based SoC platform. The SoC platform is based on the LEON3 AHB that includes a LEON3 microcontroller and other interfaces and debugging units. We add the ADSP-218x processor into the platform. The design of ADSP processor includes both the processor core design and the AMBA bus interface design. In addition, we extend the bit accuracy of the original 16-bit DSP to 32-bit and add the feature of single-instruction-multiple-data (SIMD) into the DSP core to improve the performance in digital signal processing applications. We also test several application examples executed on the two different processors and analyze their performance differences.

This thesis is concerned with the design and implementation of a Synthetic Aperture Radar (SAR) data processor. The implementation of the processing is based on a standard sequential approach to the problem and employs commonly used algorithms. The processing was done using the C language running on an IBM Compatible Personal Computer. The raw data processed was that obtained from the Shuttle Imaging Radar B (SIRB) and was supplied by the Jet Propulsion Laboratories (JPL) in California. The basic functions performed by the software include range and azimuth processing, which involve the match filtering of reference functions with the raw data. Compensation for the effects of being a spaceborne SAR were also implemented, which involved compensation for the effect of planet rotation and radar height. Images processed by JPL of the same area were also available, which allowed for direct comparisons between the outputs of the two SAR processors. The images produced were passed through a number of filters, to improve the image quality, and resulted in favourable comparisons to the JPL generated images. The actual images are included in the later sections of the thesis.

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International Telemetering Conference Proceedings / October 30-November 02, 1989 / Town & Country Hotel & Convention Center, San Diego, California / In order to suit the development of computer telemetry systems, we have developed the intelligent code-modulator and demodulation-decoder. In hardware, they consist of a monolithic processor and some high-integrated devices. Different code or decode ways and several subcarrier modulation or demodulation systems can be varied by carrying out corresponding software programs. In this paper, the equipments' hardware constructions and software cnarts and their main principles are presented.

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The effective performance of computer systems is to a large measure determined by the synergy between the processor architecture, the instruction set and the compiler. In the past, the sequencing of information within processor architectures has normally been synchronous: controlled centrally by a clock. However, this global signal could possibly limit the future gains in performance that can potentially be achieved through improvements in implementation technology. This thesis investigates the effects of relaxing this strict synchrony by distributing control within processor architectures through the use of a novel asynchronous design model known as a micronet. The impact of asynchronous control on the performance of a RISC-style processor is explored at different levels. Firstly, improvements in the performance of individual instructions by exploiting actual run-time behaviours are demonstrated. Secondly, it is shown that micronets are able to exploit further (both spatial and temporal) instructionlevel parallelism (ILP) efficiently through the distribution of control to datapath resources. Finally, exposing fine-grain concurrency within a datapath can only be of benefit to a computer system if it can easily be exploited by the compiler. Although compilers for micronet-based asynchronous processors may be considered to be more complex than their synchronous counterparts, it is shown that the variable execution time of an instruction does not adversely affect the compiler's ability to schedule code efficiently. In conclusion, the modelling of a processor's datapath as a micronet permits the exploitation of both finegrain ILP and actual run-time delays, thus leading to the efficient utilisation of functional units and in turn resulting in an improvement in overall system performance.

There are more and more Internet services such as video on demand, voice over IP,Blog, and so on. The network quality is important for providing good services. P2P technology can decentralize the usage of bandwidth, so a server can provide services with lower bandwidth. The bandwidth is filled by P2P traffic if we don¡¦t limit the usage of P2P applications, so we need a service controller that can limit the P2P traffic to provide better quality for other applications. The traditional network systems use software solutions or hardware solutions. The software solutions offer flexibility but have low performance; The hardware solutions offer highest speed but are inflexible and expensive to modify or upgrade. there is another solution known as network processors. A network processor can be programmed and has been optimizede for packet procecssing. We need a good service classifier to classify P2P traffic, then we can limit it. The performance of a signature based service classifier is dominated by the speed of its pattern matching algorithm. In this paper, we proposed a fast ulti-pattern matching algorithm by improving WM algorithm. Serveral algorithms are implemented on IXP2400 network processor for performance evaluation, and our proposed algorithm outperforms other algorithms if its parameters are properly set.

In recent years, many researchers had proposed a new class of computer architecture, called processor-in-memory (PIM), to reduce the performance gap between the CPU and memory. In order to exploit the benefits of PIM, we designed a parallelizing system ¡V SAGE (Statement Analysis Grouping Evaluation) in our previous research. In this paper, we design a program decomposition mechanism for SAGE system. The mechanism partitions the statements in a program into several parts according to control flow relation. Then it analyzes data dependence relation by using Polaris system, and generates weighted partition dependence graphs which are scheduled by task scheduling mechanisms of SAGE system.

This dissertation describes the development of voltage regulators for the purpose of power reduction and further scaling in highly integrated system-on-chip products. Emphasis is placed on the architecture and implementation of integrated voltage regulation using commercially available components, standard CMOS technology, and a practical controller. The research spans the fundamental elements, architectural aspects, and detailed analog integrated circuit design. / text