In recent years, due to advances in semiconductor technology and mature integrated circuit design, complex signal processing equipment is beginning to be replaced by the integrated circuit. This paper presents an integrated circuit programmable frequency generator for open-loop resonator application and its evaluation. It can eventually replace the conventional discrete component system and be used to find the resonance frequency shift for the readout of micro-balances or similar devices. The oscillator provides an analog tuning input to set the coarse center frequency and bit resolution, and uses a digital input to control the frequency sweep. Calculating the resonance frequency difference between the active balance and a passive reference can mitigate some environmental effects on the resonator (e.g. temperature). The generator circuit is designed using Synopsys¡¦ HSPICE and Cadence's Spectre to perform circuit simulation. The circuit is implemented by Taiwan Semiconductor Manufacturing Company in 0.35 £gm 2-poly 4-metal CMOS process technology. The potential detection precision of a micro-balance using the forward generator is assessed by connecting test chips to an evaluation PCB with commercial piezo crystals providing a known resonance frequency for testing. National Instruments¡¦ LABVIEW is used to record the data output, and MATLAB to analyze the results. A minimum detection accuracy of 1 kHz is demonstrated with this setup.

The functionality provided by mobile devices such as cellular phones and tablets continues to increase over the years, with integration of an ever larger number of wireless standards within a given device. In several of these designs, each standard supported by a device requires its own IC receiver to be mounted on the device’s PCB. In multistandard and multimode radios, it is desirable to integrate all receivers onto the same IC as the digital processors for the standards, in order to reduce device cost and size. Ideally all the receivers should also share a single signal chain. Since each standard has its own requirements for linearity and noise figure, and each standard operates at a different RF carrier frequency, implementing such a receiver is very challenging. Such a receiver could be theoretically implemented using a broadband mixing receiver or by direct sampling by a high-speed analog-to-digital converter (ADC). Broadband mixing requires the use of a harmonic rejection mixer (HRM) or tunable band pass filter to remove harmonic mixing effects, which in the past have suffered from a large primary clock tuning range and high power consumption. However, direct sampling of the RF input requires a high-speed ADC with large dynamic range which is typically limited by clock timing skew, clock jitter, or harmonic folding. In this dissertation, techniques for programmable broadband radio receivers are proposed. A local oscillator (LO) synthesis method within HRMs is proposed which reduces the required primary clock tuning range in broadband receivers. The LO synthesis method is implemented in 130-nm CMOS. A clocking technique is introduced within the two-stage HRM, which helps in achieving state-of-the-art harmonic rejection performance without calibration or harmonic filtering. An analog frequency synthesis based broadband channelizer is proposed using the LO synthesis method which is capable of channelizing a broadband input using a single mixing stage and primary clock frequency. A frequency-folded ADC architecture is proposed which enables high-speed sampling with high dynamic range. A receiver based on the frequency-folded ADC architecture is implemented in 65-nm CMOS and achieves a sample rate of 2-GS/s, a mean 49-dB SNDR, and 8.5-dB NF. / text