With an increasing number of transistors integrated on a single die, the need for global on-chip interconnectivity is growing. Long interconnects, in turn, have very large capacitances which consume a large share of a chip’s total power budget. Power consumption can be lowered in several ways, mainly by reduction of switching activity, reduction of total capacitance and by using low voltage swing. In this project, the issue is addressed by proposing a new encoding based on Pulse Width Modulation (PWM). The implementation of this encoding will both lower the switching activity and decrease the capacitance between nearby wires. Hence, the total effective capacitance will be reduced considerably. Schematic level implementation of a robust transmitter and receiver circuit was carried out in CMOS090, designed for speeds up to 100 MHz. On a 10 mm wire, this implementation would give a 40% decrease in power dissipation compared to a parallel bus having the same metal footprint. The proposed encoding can be efficiently applied for global interconnects in sub-micron systems-on-chip (SoC).

This thesis proposes a dimming approach with Double Pulse Width Modulation for equalizing the light output of the back light with light emitted diodes (LEDs) for large scale outdoor liquid crystal displays (LCDs). The approach compensates the difference among the LED light bars by adjusting the power outputs of converters according to the feedback of light strength from light sensors. With the proposed Double Pulse Width Modulation method, local brightness adjustment on the light bars can be made to provide a uniform light output and the dimming function for LCD can be retained. Experiments results made on a 46¡¨ LCD with four LED light bars demonstrate that the double pulse-width- modulation can provide uniformly in the light bar output. The experimental results show the proposed Double Pulse Width Modulation (DPWM) method can alleviate the problem from divergence of the light bars and thus can generate more uniform light output on LCDs.

To provide more information mobility, many wireless communication systems such as WCDMA and EDGE in phone systems, bluetooth and WIMAX in communication networks have been recently developed. Recent efforts have been made to build the allin- one next generation device which integrates a large number of wireless services into a single receiving path in order to raise the competitiveness of the device. Among all the receiver architectures, the high-IF receiver presents several unique properties for the next generation receiver by digitalizing the signal at the intermediate frequency around a few hundred MHz. In this architecture, the modulation/demodulation schemes, protocols, equalization, etc., are all determined in a software platform that runs in the digital signal processor (DSP) or FPGA. The specifications for most of front-end building blocks are relaxed, except the analog-to-digital converter (ADC). The requirements of large bandwidth, high operational frequency and high resolution make the design of the ADC very challenging. Solving the bottleneck associated with the high-IF receiver architecture is a major focus of many ongoing research efforts. In this work, a 6th-order bandpass continuous time sigma-delta ADC with measured 68.4dB SNDR at 10MHz bandwidth to accommodate video applications is proposed. Tuned at 200 MHz, the fs/4 architecture employs an 800 MHz clock frequency. By making use of a unique software-based calibration scheme together with the tuning properties of the bandpass filters developed under the umbrella of this project, the ADC performance is optimized automatically to fulfill all requirements for the high-IF architecture. In a separate project, other critical design issues for continuous-time sigma-delta ADCs are addressed, especially the issues related to unit current source mismatches in multi-level DACs as well as excess loop delays that may cause loop instability. The reported solutions are revisited to find more efficient architectures. The aforementioned techniques are used for the design of a 25MHz bandwidth lowpass continuous-time sigma-delta modulator with time-domain two-step 3-bit quantizer and DAC for WiMAX applications. The prototype is designed by employing a level-to-pulse-width modulation (PWM) converter followed by a single-level DAC in the feedback path to translate the typical digital codes into PWM signals with the proposed pulse arrangement. Therefore, the non-linearity issue from current source mismatch in multi-level DACs is prevented. The jitter behavior and timing mismatch issue of the proposed time-based methods are fully analyzed. The measurement results of a chip prototype achieving 67.7dB peak SNDR and 78dB SFDR in 25MHz bandwidth properly demonstrate the design concepts and effectiveness of time-based quantization and feedback. Both continuous-time sigma-delta ADCs were fabricated in mainstream CMOS 0.18um technologies, which are the most popular in today?s consumer electronics industry.

A single-stage high-power-factor electronic ballast is designed for fluorescent lamps with dimming capability. The circuit configuration is originated from the integration of the half-bridge resonant inverter and the buck-boost converter. The buck-boost converter is designed to operate in discontinuous conduction mode (DCM) to provide nearly unit power factor at a fixed switching frequency. With asymmetrical pulse-width-modulation (APWM), the lamp power can be effectively regulated. The power switches of the inverter exhibit either zero-voltage-switching (ZVS) or zero-current-switching (ZCS) over the whole dimming range. Design equations are derived and computer analyses are performed based on a power-dependent lamp model and fundamental approximation. Design guidelines for determining circuit parameters are provided. A prototype circuit for a T8-36W fluorescent lamp is built and tested to verify the analytical predictions.

To minimize the size of the electronic ballast, a half-bridge load- resonant inverter with a cascading Rosen-type piezoelectric transformer (PT) is designed for cold cathode fluorescent lamps (CCFLs). The electrical characteristics of the PT are investigated to obtain a higher voltage gain by adapting the load impedance to the interposed network. The circuit parameters are selected under the considerations of (1) the minimum inductor size, (2) the higher circuit efficiency, (3) the rated current of the PT, and (4) the stable lamp operation. The electronic ballasts are designed for operating the lamp at the rated lamp power and with dimming control by asymmetrical pulse-width-modulation (APWM),respectively. Laboratory circuits are assembled and, experimental tests are carried out to validate the theoretical analyse

The design and implementation of the digital signal processing (DSP) based on a brushless DC (BLDC) motor sensorless driver with Sine PWM. Because of dispensable power consumption problems generated by closed-loop speed control methods with speed estimation signal feedback are adopted for improvement. In addition, current feedback is added to the driver for the sake of increasing efficiency. Then, sine wave closes 30¢X, 15¢X, and 8¢X to comparing the improvements for efficiency. Experimental results from a laboratory prototype are shown to verify the feasibility of the proposed scheme. The laboratory results show that current feedback and sine wave closed 8¢X have high efficiency.

This report is a study of the effects of a commercial 0.13[mu] process and automotive temperature corners on a synchronous DC-DC buck converter design. The basics of switching converters will be explored with an emphasis on voltage-mode controlled feedback. A Type-III compensation network is designed using transfer function analysis to compensate for the inherent double pole introduced by an LC network. The output of the compensation network will drive a pulse width modulation comparator to vary the duty cycle of the high-side PMOS and low-side NMOS transistor switches. After the synchronous buck converter design was complete, the effect of process and temperature on efficiency, output voltage ripple, inductor peak to peak current, and output voltage load response was examined. / text

The objective of this research is to explore circuit techniques and architectures suitable for implementation in digital technologies, that can be used to enhance the efficiency of power stages. Specifically, the use of switching power stages with pulse-width modulation techniques is considered. Switching power stages, such as Class D amplifiers, are inherently well-suited for implementation in deep-submicron CMOS. Pulse-width modulation (PWM) employs discrete amplitude levels and encodes signal information in local time-based averages, and as such can also benefit from such technologies. Additionally PWM does not suffer from quantization noise, and is well-suited for low noise applications. PWM designs, that can be applied for a range of signal bandwidth requirements, spanning several tens to hundreds of kHz are proposed. Applications for these architectures include audio systems, powerline communications and wireless communications. Design challenges and requirements that can arise in different application contexts are considered in the specification of the architectures. A common goal in the definition of the architectures is to minimize complexity of the designs. In the first part of the dissertation, a third-order self-oscillating PWM class-D amplifier for audio applications, that utilizes a hysteretic comparator is described. The design is analyzed and its THD is theoretically determined by employing an equivalent model, that relates the approach to natural sampling pulse-width modulation. The architecture eliminates the requirement for a high-quality carrier generator. A low-cost hysteresis compensation technique is utilized to enhance distortion performance at high output power levels. An implementation is presented in a 0.7um CMOS process. The design achieves a dynamic range (DR) of 116.5 dB, and a THD+N of 0.0012%, while delivering a power of 125 mW into an 8[Omega] load at 1 kHz. The THD+N is under 0.006% up to 90% of the maximum output power. The amplifier can deliver 1.45 W into the load with a THD of 5% with a 5 V power supply. The efficiency is greater than 84% for output power larger than 1 W. The area of the amplifier is 6 mm². The achieved performance indicates that the design is well-suited for high-performance audio applications. A class D line driver that utilizes a phase-locked loop (PLL) based PWM generation technique is presented next. The principle of operation, and implementation details relating to loop stability, linearity and noise performance are analyzed. An implementation is presented in a 130nm CMOS process. The amplifier can deliver 1.2 W into an 6.8[Omega] load with a 4.8 V power supply. The architecture eliminates the requirement for a high-quality carrier generator and a fast, continuous voltage comparator that are often required in PWM implementations. The design can achieve a THD of -65 dB, with a switching frequency that can be as high as 20 MHz. The peak efficiency is 83% for output power larger than 1 W, for a switching frequency of 10 MHz. The area of the amplifier is 2.25 mm². This architecture is potentially suitable for powerline applications. Finally, a phase-locked loop based PWM Cartesian transmitter with the capability to drive switched power amplifiers, such as a Class D power amplifier, is proposed. A phase-locked loop based technique is employed to generate a high-frequency PWM pulse stream centered at 1.28 GHz. The prototype is simulated in a 130 nm CMOS process, and achieves 35% peak efficiency for 17 dBm output power with a carrier frequency of 900 MHz. Operation of the architecture with non-constant envelope modulation, such as that employed in the WCDMA standard, is verified in simulation. / text

Η ψηφιακή τεχνολογία έχει διεισδύσει πλήρως στην περιοχή της Ακουστικής και της Τεχνολογίας Ήχου, όπως επίσης και σε όλους σχεδόν τους κλάδους της σύγχρονης επιστήμης και της τεχνολογίας. Στον τομέα των ηλεκτρονικών για ηχητικές εφαρμογές, ιδιαίτερα καθοριστικό ρόλο κατέχουν οι ενι- σχυτές. Σκοπός της εργασίας αυτής, είναι να παρουσιάσει το λειτουργικό μοντέλο ενός ψηφιακού ενι- σχυτή Class-D για ηχητικά σήματα, το οποίο προσομοιώθηκε και λειτούργησε σε περιβάλλον Matlab & Simulink. Στο τέλος παρουσιάζονται τα αποτελέσματα χρήσιμων μετρήσεων για σημαντικούς δεί- κτες της ηλεκτροακουστικής όπως η Απόκριση Συχνότητας, Total Harmonic Distortion(THD), Total Harmonic Distortion plus Noise (THD+N) ως προς τη συχνότητα και ως προς την ισχύ, από όπου βγαίνουν συμπεράσματα σχετικά με την ποιότητα και την απόδοση της συγκεκριμένης τεχνολογίας υλοποίησης. / DigitalTechnology has been fully into Acousctics and Audio Technology,as in virtually all branches of modern science and technology.In audio electronics applications, amplifiers have a significant role. The purpose of this thesis is to present the functional model of a digital Class-D amplifier for audio signals, which has been simulated and run in Matlab & Simulink environment. Finally the results of measurements relating to some important electroacoustics indexes like Frequency Response, Total Harmonic Distortion (THD), Total Harmonic Distortion plus Noise (THD+N), relative to the audio signal’s frequency and power, are presented and lead to some conclusions concerning the quality and efficiency of this implementation technology.

Στην παρούσα διπλωματική εργασία μοντελοποιήθηκε και αναλύθηκε η λειτουργία και η συμπεριφορά ενός τριφασικού ασύγχρονου κινητήρα τροφοδοτούμενου μέσω ηλεκτρονικού μετατροπέα τόσο στην περίπτωση της «υγιούς» μηχανής, όσο και στην περίπτωση μηχανής η οποία παρουσίαζε σφάλματα στον κλωβό. Πιο συγκεκριμένα, με την βοήθεια προγράμματος πεπερασμένων στοιχείων και ειδικότερα πραγματοποιώντας ανάλυση στις δύο διαστάσεις, προσομοιώσαμε την τάση εξόδου ενός αντιστροφέα πηγής τάσης με λειτουργία διαμόρφωσης εύρους παλμών μέσω κώδικα που σχεδιάσαμε, και στην συνέχεια τροφοδοτήσαμε με τους παλμούς που παρήχθησαν τα τυλίγματα του στάτη της ασύγχρονης υπό μελέτη μηχανής. Ακολούθως με την χρήση του προαναφερθέντος προγράμματος έγινε ηλεκτρομαγνητική ανάλυση, της μηχανής. Παρήχθησαν οι κυματομορφές των βασικότερων μεγεθών της μηχανής και πραγματοποιήσαμε με την βοήθεια του προγράμματος MATLAB/SIMULINK(R2008A) , αναλύσεις fourier στα φασικά ρεύματα και στις φασικές τάσεις του στάτη, τόσο για το μοντέλο της ασύγχρονης μηχανής χωρίς σφάλματα του δρομέα όσο και για το μοντέλο με σφάλματα. Για την διάγνωση του σφάλματος χρησιμοποιήθηκε η μέθοδος MCSA(motor current signature analysis) καθώς και η ανάλυση των αρμονικών στο φάσμα της ροπής. Αναλυτικότερα, στο πρώτο κεφάλαιο γίνεται μια εισαγωγή στα κατασκευαστικά χαρακτηριστικά καθώς και στις βασικές μεθόδους λειτουργίας της ασύγχρονής μηχανής, ενώ γίνεται ιδιαίτερη αναφορά στον έλεγχο κινητήρων γενικότερα όπως επίσης και στην λειτουργία αυτών σε περίπτωση σφαλμάτων. Στο δεύτερο κεφάλαιο περιγράφονται οι ηλεκτρονικοί μετατροπείς ισχύος για συστήματα οδήγησης ασύγχρονων κινητήρων. Ειδικότερα, παρουσιάζεται συνοπτικά η λειτουργία του τριφασικού ανορθωτή, ενώ ιδιαίτερη αναφορά γίνεται στον τριφασικό αντιστροφέα. Πιο συγκεκριμένα, παρουσιάζονται τα κατασκευαστικά και τα λειτουργικά χαρακτηριστικά του αντιστροφέα πηγής τάσης, γίνεται εκτενής αναφορά στην λειτουργία του με διαμόρφωση εύρους παλμών (PWM mode of operation) ενώ κυρίως αναλύεται η συμπεριφορά του στην γραμμική περιοχή λειτουργίας του(0<modulation index<0.907), όπου και μας ενδιαφέρει. Στο τρίτο κεφάλαιο παρουσιάζονται τα αποτελέσματα της εξομοίωσης του ασύγχρονου τριφασικού κινητήρα, με και χωρίς σφάλμα στον δρομέα όπως αυτά προέκυψαν από την ανάλυση που πραγματοποιήθηκε με χρήση του προγράμματος πεπερασμένων στοιχείων. Παράλληλα δίνεται ανάλυση του κώδικα που σχεδιάστηκε για την προσομοίωση της τάσης εξόδου ενός τριφασικού αντιστροφέα με λειτουργία PWM για την τροφοδοσία των τυλιγμάτων της μηχανής μας, γεγονός το οποίο και αποτελεί κυρίαρχο περιεχόμενο της παρούσας διπλωματικής εργασίας. Στο τέταρτο κεφάλαιο γίνεται αναφορά στο πειραματικό σκέλος της διπλωματικής εργασίας. Περιγράφεται δηλαδή η πειραματική διάταξη που υλοποιήθηκε στο εργαστήριο χρησιμοποιώντας δύο όμοιους τριφασικούς ασύγχρονους κινητήρες κλωβού, ένα με σφάλμα στο δακτύλιο βραχυκύκλωσης και ένα χωρίς σφάλμα, ενώ ταυτόχρονα παρατίθενται οι κυματομορφές του ρεύματος στάτη στις οποίες έγινε ανάλυση FFΤ έτσι ώστε να εντοπιστούν οι συχνότητες στις οποίες εισάγονται αρμονικές λόγω του σφάλματος στο δακτύλιο βραχυκύκλωσης και να γίνει έτσι η διάγνωση του σφάλματος. Στο πέμπτο κεφάλαιο πραγματοποιούμε επεξεργασία των πειραματικών αποτελεσμάτων καθώς και των αποτελεσμάτων τα οποία προκύπτουν από την εξομοίωση των δύο κινητήρων από το πρόγραμμα πεπερασμένων στοιχείων OPERA- 2D. Συγκεκριμένα πραγματοποιούμε ανάλυση FFT μέσω του προγράμματος MATLAB/SIMULINK(R2008A) στις κυματομορφές του ρεύματος στάτη και των τάσεων αυτού καθώς και της ροπής για τους δύο κινητήρες τόσο στην περίπτωση ημιτονοειδούς τροφοδοσίας τους, όσο και στην περίπτωση που τροφοδοτούνται με την τάση εξόδου ενός inverter με pwm διαμόρφωση. Από τα αποτελέσματα που προκύπτουν εξάγουμε σημαντικά συμπεράσματα όσο αφορά τη λειτουργία των δύο κινητήρων ενώ ταυτόχρονα επιτυγχάνεται και μια σύγκριση των πειραματικών αποτελεσμάτων με τα αποτελέσματα της εξομοίωσης. Τέλος, στο έκτο κεφάλαιο, το οποίο αποτελεί και το παράρτημα της παρούσας διπλωματικής εργασίας, δίνεται η μοντελοποίηση μέσω του SIMULINK του αντιστροφέα πηγής τάσης με λειτουργία PWM, ενώ παράλληλα γίνεται αναφορά στις διακοπτικές απώλειες των ασύγχρονων κινητήρων όταν αυτοί τροφοδοτούνται με την τάση εξόδου ενός inverter με pwm διαμόρφωση, αλλά και των αντιστροφέων πηγής τάσης, οι οποίοι αποτέλεσαν και κυρίαρχο αντικείμενο μελέτης . / This diploma thesis forms a study on modeling an analyzing an induction motor by using a faulty detection. These motors are often used in industrial applications thanks to their usability and their robustness. However, nowadays optimisation of production becomes so critical that the conceptual reliability of the motor is not suffcient anymore. In this thesis different implementations of control algorithm were examined along with the most important PWM modulation techniques. The cage induction motor is modeled with the space and time discretized finite element analysis using the program OPERA and developing an appropriate model for the motor in 2 dimensions. The fft analysis was performed by developing an appropriate algorithm for the system at the Matlab Tests have been conducted on an experimental construction in order to confirm the theoretically expected operational characteristics of the system.