Over the years, number of design methodologies were developed. One of the state-of-the-art modeling approaches is Model Driven Architecture. This thesis is an attempt to utilize the MDA in a specific and complex domain – real-time systems development. In MDA framework there are three levels of abstraction: computation independent, platform independent and platform specific. The target environment of the method presented in the thesis is Ada 2005 programming language which extended the old version of the language with several new object-oriented features making it suitable for using with the MDA. Application of the MDA in real-time systems domain targeted towards Ada 2005 implementation constitutes a new design method which benefits from the MDA, UML and Ada 2005 advantages. The thesis starts with presentation of the complexity of the real-time systems domain. A few real-time domain aspects are chosen as a main area for elaborating the design method. The utilizes UML Profile for Schedulability, Performance and Time for defining platform independent model. Additionally it provides its extension – the Ada UML profile – which constitutes the platform specific model. This is followed by specification of transformations between platform independent and specific model. The specification is used as a base for implementation of the transformations. Guidelines for code generation form the Ada UML profile are also provided. Finally, the thesis describes how the transformations can be implemented in Telelogic TAU tool. / gruszka.robert@gmail.com

In today’s world, embedded systems which have very large and highly configurable software systems, consisting of hundreds of tasks with huge lines of code and mostly with real-time constraints, has replaced the traditional systems. Generally in real-time systems, the WCET of a program is a crucial component, which is the longest execution time of a specified task. WCET is determined by WCET analysis techniques and the values produced should be tight and safe to ensure the proper timing behavior of a real-time system. Static WCET is one of the techniques to compute the upper bounds of the execution time of programs, without actually executing the programs but relying on mathematical models of the software and the hardware involved. Mathematical models can be used to generate timing estimations on source code level when the hardware is not yet fully accessible or the code is not yet ready to compile. In this thesis, the methods used to build timing models developed by WCET group in MDH have been assessed by evaluating the accuracy of the resulting timing models for a number of combinations of hardware architecture. Furthermore, the timing model identification is extended for various hardware platforms, like advanced architecture with cache and pipeline and also included floating-point instructions by selecting benchmarks that uses floating-points as well.

Safety-critical applications have to function correctly even in presence of faults. This thesis deals with techniques for tolerating effects of transient and intermittent faults. Reexecution, software replication, and rollback recovery with checkpointing are used to provide the required level of fault tolerance. These techniques are considered in the context of distributed real-time systems with non-preemptive static cyclic scheduling. Safety-critical applications have strict time and cost constrains, which means that not only faults have to be tolerated but also the constraints should be satisfied. Hence, efficient system design approaches with consideration of fault tolerance are required. The thesis proposes several design optimization strategies and scheduling techniques that take fault tolerance into account. The design optimization tasks addressed include, among others, process mapping, fault tolerance policy assignment, and checkpoint distribution. Dedicated scheduling techniques and mapping optimization strategies are also proposed to handle customized transparency requirements associated with processes and messages. By providing fault containment, transparency can, potentially, improve testability and debugability of fault-tolerant applications. The efficiency of the proposed scheduling techniques and design optimization strategies is evaluated with extensive experiments conducted on a number of synthetic applications and a real-life example. The experimental results show that considering fault tolerance during system-level design optimization is essential when designing cost-effective fault-tolerant embedded systems.

A real-time kernel offers many advantages when developing safety-critical real-time applications. It allows for a modular software architecture and provides many services to help meet any timing constraints imposed on the application. However, these benefits come at a price. The use of a real-time kernel can introduce both latency and non-determinism into the system, forcing the application designer to account for worst case execution times which might be overly pessimistic in the average case. This thesis presents a hardware accelerated implementation of the widely popular real-time kernel FreeRTOS, using only off-the-shelf hardware components. A set of benchmark tests were also developed to compare FreeRTOS and the suggested hardware accelerated implementation with respect to performance and determinism. By migrating critical parts of FreeRTOS into hardware, we were able to greatly reduce the delays associated with the kernel. Furthermore, constant execution times for all supported kernel API calls were achieved, facilitating accurate timing analysis of any application running on top of the real-time kernel. / Användandet av en realtidskärna vid utveckling av säkerhetskritiska realtidsapplikationer har flera fördelar. Det underlättar konstruktionen av en modulär mjukvaruarkitektur och erbjuder flera mekanismer för att klara de tidsrelaterade krav som ställs på en applikation. En realtidskärna kan emellertid introducera långa och icke-deterministiska responstider, vilket tvingar applikationsdesignern att alltid ta höjd för det teoretiska värstafallet även om detta är överdrivet pessimistisk jämfört med medelfallet. I denna uppsats presenteras en hårdvaruaccelererad implementation av realtidskärnan FreeRTOS, konstruerad med hjälp av kommersiellt tillgängliga hårdvarukomponenter. Utöver detta presenteras även en uppsättning tester för att jämföra FreeRTOS samt dess hårdvaruaccelererade motsvarighet med avseende på prestanda och determinism. Genom att migrera kritiska delar av FreeRTOS till hårdvara kunde de långa responstiderna kraftigt reduceras. Utöver detta blev exekveringstiden helt deterministiskt i den hårdvaruaccelererade implementationen, något som möjliggör en mer exakt tidsanalys.

Computers are widely present in our daily life and are used in critical applic-ations like cars, planes, pacemakers. Those real-time systems are nowadaysbased on processors which have an increasing complexity and have specifichardware services designed to reduce task preemption and migration over-heads. However using those services can add unpredictable overheads whenthe system has to switch from one task to another in some cases.This document screens existing solutions used in commonly availableprocessors to ease preemption and migration to highlight their strengths andweaknesses. A new hardware service is proposed to speed up task switchingat the L1 cache level, to reduce context switch overheads and to improvesystem predictability.The solution presented is based on stacking several identical cachememories at the L1 level. Each layer is able to save and restore its completestate independently to/from the main memory. One layer can be used forthe active task running on the processor while another layers can be restoredor saved concurrently. The active task can remain in execution until thepreempting task is ready in another layer after restoration from the mainmemory. The context switch between tasks can then be performed in avery short time by switching to the other layer which is now ready to runthe preempting task. Furthermore, the task will be resumed with the exactL1 cache memory state as saved earlier after the previous preemption. Theprevious task state can be sent back to the main memory for future use.Using this mechanism can lead to minimise the time required for migrationsand preemptions and consequently lower overheads and limit cache missesdue to preemptions and usually considered in the cache migration andpreemption delays. Isolation between tasks is also provided as they areexecuted from a dedicated layer.Both uniprocessor and multiprocessor designs are presented along withimplications on the real-time theory induced by the use of this hardware ser-vice. An implementation of the system is characterized and results show im-provements to the maximum and average execution time of a set of varioustasks: When the same size is used for the baseline cache and HwCS layers,94% of the tasks have a better execution time (up to 67%) and 80% have a bet-ter Worst Case Execution Time (WCET). 80% of the tasks are more predictableand the remaining 20% still have a better execution time. When we split thebaseline cache size among layers of the HwCS, measurements show that 75%of the tasks have a better execution time (up to 67%) leading to 50% of thetasks having a better WCET. Only 6% of the tasks suffer from worse executiontime and worse predictability while 75% of the tasks remain more predictablewhen using the HwCS compared to the baseline cache. / Les ordinateurs ont envahi notre quotidien et sont de plus en plus souventutilisés pour remplir des missions critiques. Ces systèmes temps réel sontbasés sur des processeurs dont la complexité augmente sans cesse. Des ser-vices matériels spécifiques permettent de réduire les coûts de préemption etmigration. Malheureusement, ces services ajoutent des temps morts lorsquele système doit passer d’une tâche à une autre.Ce document expose les solutions actuelles utilisées dans les processeurscourants pour mettre en lumière leurs qualités et défauts. Un nouveau ser-vice matériel (HwCS) est proposé afin d’accélérer le changement de tâches aupremier niveau de mémoire (L1) et de réduire ainsi les temps morts dus auxchangements de contextes tout en améliorant la prédictibilité du système.Bien que cette thèse se concentre sur le cache L1, le concept développépeut également s’appliquer aux autres niveaux de mémoire ainsi qu’àtout bloc dépendant du contexte. La solution présentée se base sur unempilement de caches identiques au premier niveau. Chaque couche del’empilement est capable de sauvegarder ou recharger son état vers/depuisla mémoire principale du système en toute autonomie. Une couche peutêtre utilisée par la tâche active pendant qu’une autre peut sauvegarder ourestaurer l’état d’une autre tâche. La tâche active peut ainsi poursuivre sonexécution en attendant que la tâche suivante soit rechargée. Le changementde contexte entre la tâche active et la tâche suivante peut alors avoir lieu enun temps très court. De plus, la tâche reprendra son exécution sur un cacheL1 dont l’état sera identique à celui au moment où elle a été interrompueprécédemment. L’état du cache de la tâche désormais inactive peut êtresauvegardé dans la mémoire principale en vue d’une utilisation ultérieure.Ce mécanisme permet de réduire au strict minimum le temps de calculperdu à cause des préemptions et migrations, les temps de sauvegarde et derechargement de la L1 n’ayant plus d’influence sur l’exécution des tâches. Deplus, chaque niveau étant dédié à une tâche, les interférences entre tâchessont réduites.Les propriétés ainsi que les implications sur les aspects temps réelsthéoriques sont présentées pour des systèmes mono et multiprocesseurs.Une implémentation d’un système uniprocesseur incluant ce servicematériel et sa caractérisation par rapport à l’exécution d’un set de tâchessont également présentées ainsi que les bénéfices apportés par le HwCS:Lorsque les couches du HwCS ont la même taille que le cache de base, 94%des tâches ont un meilleur temps d’exécution (jusqu’à 67%) et 80% ont unmeilleur pire temps d’exécution (WCET). 80% des tâches deviennent plusprédictibles et les 20% restants bénéficient néanmoins d’un meilleur WCET.Toutefois, si la taille du cache est partagée entre les couches du HwCS, lesmesures montrent que 75% des tâches ont un meilleur temps d’exécution,impliquant un meilleur WCET pour la moitié des tâches du système. Seule-ment 6% des tâches voient leur WCET augmenter et leur prédictibilitédiminuer tandis que 75% des tâches améliorent leur prédictibilité grâce auHwCS. / Doctorat en Sciences de l'ingénieur et technologie / info:eu-repo/semantics/nonPublished

In 1994, Alur and Dill introduced timed automata as a simple mathematical model for modelling the behaviour of real-time systems. In this thesis, we extend timed automata with weights. More detailed, we equip both the states and transitions of a timed automaton with weights taken from an appropriate mathematical structure. The weight of a transition determines the weight for taking this transition, and the weight of a state determines the weight for letting time elapse in this state. Since the weight for staying in a state depends on time, this model, called weighted timed automata, has many interesting applications, for instance, in operations research and scheduling. We give characterizations for the behaviours of weighted timed automata in terms of rational expressions and logical formulas. These formalisms are useful for the specification of real-time systems with continuous resource consumption. We further investigate the relation between the behaviours of weighted timed automata and timed automata. Finally, we present important decidability results for weighted timed automata.

Present research into critical embedded control systems tends to focus on the computational elements and largely ignore the link between the computational and physical elements. This link is very important since the computational capability of the computer can greatly affect the performance and dynamics of the system it controls. The control computer is in the feedback loop of control systems and contributes to feedback delay in addition to already existing mechanical delays. While mechanical delays are compensated in control design, variable computational delays cause system to underperform in its intended physical behavior and impose a cost in terms of fuel or time. For this reason, the scheduler in a real-time operating systems should not focus only on the task deadlines, but also on efficient scheduling which minimizes the effect of computational delay on the controlled plant. The proposed work provides a systematic framework to manage and evaluate the implications of computational delay in vehicles. The work also includes cost sensitive real-time control task scheduling heuristics and Dynamic Voltage Scaling (DVS) for better energy/thermal control. We show through simulations that our heuristic achieves a significant improvement in cost over the traditional real-time scheduling algorithm Earliest Deadline First (EDF) and show that it can adjust according to energy constraints imposed on the system.

The criticality of the applications modeled by the real-time software places stringent requirements on software quality before deploying into real use. Though automated test tools can be used to run a large number of tests efficiently, the functionality of any test tool is not complege without providing a means for analyzing the test results to determine potential problem sub-domains and sub-domains that need to be covered, and estimating the reliability of the modeled system. This thesis outlines a solution strategy and implementation of that strategy for deriving quantitative metrics from domain testing of real-time control software tested via simulation. The key portion of this thesis addresses the combinatorial problems involved with effective evaluation of test coverage and provides the developer with reliability metrics from testing of the software to gain confidence in the test phase of development. The two approaches for reliability analysis- time domain and input domain approaches are studied and a hybrid approach that combines the strengths of both these approaches is proposed. A Reliability analysis Test Tool (RATT) has been developed to implement the proposed strategies. The results show that the metrics are practically feasible to compute and can be applied to most real-time software.

<p dir="ltr">Dynamic analysis of embedded firmware is a necessary capability for many security tasks, e.g., vulnerability detection. Rehosting is a technique that enables dynamic analysis by facilitating the execution of firmware in a host environment decoupled from the actual hardware. Current rehosting techniques focus on high-fidelity execution of the entire firmware. Consequently, these techniques try to execute firmware in an emulated environment, with precise models of hardware (i.e., peripheral) interactions. However, these techniques are hard to scale and have various drawbacks. </p><p dir="ltr">Therefore, a novel take on rehosting is proposed by focusing on the application components and their interactions with the firmware without the need to model hardware dependencies. This is achieved by rehosting the embedded application as a Linux application. In addition to avoiding precise peripheral modeling, such a rehosting technique enables the use of existing dynamic analysis techniques on these embedded applications. The feasibility of this approach is demonstrated first by manually performing the rehosting on real-world embedded applications. The challenges in each of the phases – retargeting to x86-64, peripheral handling, and fuzzing the rehosted applications are elaborated. Furthermore, automated steps for retargeting to the x86-64 and peripheral handling are developed. The peripheral handling achieves 89% accuracy if reserved regions are also considered. The testing of these rehosted applications found 2 previously unknown defects in driver components.</p>

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