The employment of real time NDT systems has been spread widely last years. It is very important to control in real-time layer thicknesses of multi-layered materials during manufacturing process. In this work multi-layer thickness measurement digital signal processing methods are evaluated. Presented real-time nondestructive testing system and signal propagation model is a background for measurement algorithm analysis and development. In this work multi-layer thickness measurement problem is addressed with a different approach, by applying correlation functions on parts of the ultrasonic signal, thus reducing the overall computational complexity.

Embedded systems are becoming ubiquitous in our daily life. Due to close interaction with physical world, embedded systems are typically subject to timing constraints. At design time, it must be ensured that the run-time behaviors of such systems satisfy the pre-specified timing constraints under any circumstance. In this thesis, we develop techniques to address the timing analysis problems brought by the increasing complexity of underlying hardware and software on different levels of abstraction in embedded systems design. On the program level, we develop quantitative analysis techniques to predict the cache hit/miss behaviors for tight WCET estimation, and study two commonly used replacement policies, MRU and FIFO, which cannot be analyzed adequately using the state-of-the-art qualitative cache analysis method. Our quantitative approach greatly improves the precision of WCET estimation and discloses interesting predictability properties of these replacement policies, which are concealed in the qualitative analysis framework. On the component level, we address the challenges raised by multi-core computing. Several fundamental problems in multiprocessor scheduling are investigated. In global scheduling, we propose an analysis method to rule out a great part of impossible system behaviors for better analysis precision, and establish conditions to guarantee the bounded responsiveness of computing tasks. In partitioned scheduling, we close a long standing open problem to generalize the famous Liu and Layland's utilization bound in uniprocessor real-time scheduling to multiprocessor systems. We also propose to use cache partitioning for multi-core systems to avoid contentions on shared caches, and solve the underlying schedulability analysis problem. On the system level, we present techniques to improve the Real-Time Calculus (RTC) analysis framework in both efficiency and precision. First, we have developed Finitary Real-Time Calculus to solve the scalability problem of the original RTC due to period explosion. The key idea is to only maintain and operate on a limited prefix of each curve that is relevant to the final results during the whole analysis procedure. We further improve the analysis precision of EDF components in RTC, by precisely bounding the response time of each computation request.

La recherche d'une borne supérieure au temps d'exécution d'un programme est une partie essentielle du processus de vérification de systèmes temps-réel critiques. Les programmes de tels systèmes ont généralement des temps d'exécution variables et il est difficile, voire impossible, de prédire l'ensemble de ces temps possibles. Au lieu de cela, il est préférable de rechercher une approximation du temps d'exécution pire-cas ou Worst-Case Execution Time (WCET). Une propriété cruciale de cette approximation est qu'elle doit être sûre, c'est-à-dire qu'elle doit être garantie de majorer le WCET. Parce que nous cherchons à prouver que le système en question se termine en un temps raisonnable, une surapproximation est le seul type d'approximation acceptable. La garantie de cette propriété de sûreté ne saurait raisonnablement se faire sans analyse statique, un résultat se basant sur une série de tests ne pouvant être sûr sans un traitement exhaustif des cas d'exécution. De plus, en l'absence de certification du processus de compilation (et de transfert des propriétés vers le binaire), l'extraction de propriétés doit se faire directement sur le code binaire pour garantir leur fiabilité. Toutefois, cette approximation a un coût : un pessimisme - écart entre le WCET estimé et le WCET réel - important entraîne des surcoûts superflus de matériel pour que le système respecte les contraintes temporelles qui lui sont imposées. Il s'agit donc ensuite, tout en maintenant la garantie de sécurité de l'estimation du WCET, d'améliorer sa précision en réduisant cet écart de telle sorte qu'il soit suffisamment faible pour ne pas entraîner des coûts supplémentaires démesurés. Un des principaux facteurs de surestimation est la prise en compte de chemins d'exécution sémantiquement impossibles, dits infaisables, dans le calcul du WCET. Ceci est dû à l'analyse par énumération implicite des chemins ou Implicit Path Enumeration Technique (IPET) qui raisonne sur un surensemble des chemins d'exécution. Lorsque le chemin d'exécution pire-cas ou Worst-Case Execution Path (WCEP), correspondant au WCET estimé, porte sur un chemin infaisable, la précision de cette estimation est négativement affectée. Afin de parer à cette perte de précision, cette thèse propose une technique de détection de chemins infaisables, permettant l'amélioration de la précision des analyses statiques (dont celles pour le WCET) en les informant de l'infaisabilité de certains chemins du programme. Cette information est passée sous la forme de propriétés de flot de données formatées dans un langage d'annotation portable, FFX, permettant la communication des résultats de notre analyse de chemins infaisables vers d'autres analyses. Les méthodes présentées dans cette thèse sont inclues dans le framework OTAWA, développé au sein de l'équipe TRACES à l'IRIT. Elles usent elles-mêmes d'approximations pour représenter les états possibles de la machine en différents points du programme. / The search for an upper bound of the execution time of a program is an essential part of the verification of real-time critical systems. The execution times of the programs of such systems generally vary a lot, and it is difficult, or impossible, to predict the range of the possible times. Instead, it is better to look for an approximation of the Worst-Case Execution Time (WCET). A crucial requirement of this estimate is that it must be safe, that is, it must be guaranteed above the real WCET. Because we are looking to prove that the system in question terminates reasonably quickly, an overapproximation is the only acceptable form of approximation. The guarantee of such a safety property could not sensibly be done without static analysis, as a result based on a battery of tests could not be safe without an exhaustive handling of test cases. Furthermore, in the absence of a certified compiler (and tech- nique for the safe transfer of properties to the binaries), the extraction of properties must be done directly on binary code to warrant their soundness. However, this approximation comes with a cost : an important pessimism, the gap between the estimated WCET and the real WCET, would lead to superfluous extra costs in hardware in order for the system to respect the imposed timing requirements. It is therefore important to improve the precision of the WCET by reducing this gap, while maintaining the safety property, as such that it is low enough to not lead to immoderate costs. A major cause of overestimation is the inclusion of semantically impossible paths, said infeasible paths, in the WCET computation. This is due to the use of the Implicit Path Enumeration Technique (IPET), which works on an superset of the possible execution paths. When the Worst-Case Execution Path (WCEP), corresponding to the estimated WCET, is infeasible, the precision of that estimation is negatively affected. In order to deal with this loss of precision, this thesis proposes an infeasible paths detection technique, enabling the improvement of the precision of static analyses (namely for WCET estimation) by notifying them of the infeasibility of some paths of the program. This information is then passed as data flow properties, formatted in the FFX portable annotation language, and allowing the communication of the results of our infeasible path analysis to other analyses.

Dans le domaine des systèmes critiques, l'analyse des temps d'exécution des programmes est nécessaire pour planifier et ordonnancer au mieux différentes tâches et par extension pour dimensionner les systèmes. La durée d'exécution d'un programme dépend de divers facteurs comme ses entrées ou le matériel utilisé. Or cette variation temporelle pose problème dans les systèmes temps-réel dans lesquels il est nécessaire de dimensionner précisément les temps processeur alloués à chaque tâche, et pour cela, connaître leur temps d'exécution au pire cas. Au sein de l'équipe TRACES à l'IRIT, nous cherchons à calculer une borne supérieure à ce temps d'exécution au pire cas qui soit la plus précise possible. Pour cela, nous travaillons sur le graphe de flot de contrôle d'un programme qui représente un sur-ensemble des ses exécutions possibles, que nous accompagnons d'annotations sur des comportements spécifiques du programme susceptibles de réduire la sur-approximation de notre estimation. Dans les outils destinés au calcul du temps d'exécution au pire cas des programmes, les annotations sont habituellement exprimées et intégrées grâce à des langages d'annotation spécifiques. Nous proposons d'utiliser des automates appelés automates d'annotation de flot en lieu et place de ces langages, afin de fonder non seulement l'expression, mais également l'intégration d'annotations dans l'analyse sur des bases formelles. Nous présentons ces automates enrichis de contraintes, de variables et d'une hiérarchie et nous montrons comment ils supportent les divers types d'annotations utilisés dans le domaine de l'analyse du temps d'exécution au pire cas. Par ailleurs, l'intégration des annotations dans une analyse se fait habituellement par l'association de contraintes numériques au graphe de flot de contrôle. Les automates que nous présentons supportent cette méthode mais leur expressivité offre également de nouvelles possibilités d'intégration basées sur le dépliage du graphe de flot de contrôle. Nous présentons des résultats expérimentaux issus de la comparaison de ces deux méthodes qui montrent comment le dépliage de graphe peut améliorer la précision de l'analyse. A terme, ce gain de précision dans l'estimation du temps d'exécution au pire cas permettra de mieux exploiter le matériel sans faire courir de risques à l'utilisateur ou au système. / In the domain of critical systems, the analysis of execution times of programs is needed to schedule various task at best and by extension to dimension the whole system. The execution time of a program depends on multiple factors such as entries of the program or the targeted hardware. Yet this time variation is an issue in real-time systems where the duration is required to allow correct processor time to each task, and in this purpose, we need to know their worst-case execution time. In the TRACES team at IRIT, we try to compute a safe upper bound of this worst-case execution time that would be as precise as possible. In order to do so, we work on the control flow graph of a program that represents an over-set of its possible executions and we combine this structure with annotations on specific behaviours of the program that might reduce the over-approximation of our estimation. Tools designed to compute worst-case execution times of programmes usually support the expression and the integration of annotations thanks to specific annotation languages. Our proposal is to replace these languages with a type of automata named flow fact automata so that not only the expression but also the integration of annotations in the analysis inherit from the formal basis of automata. Based on these automata enriched with constraints, variables and a hierarchy, we show how they support the various annotation types used in the worst-case execution time domain. Additionally, the integration of annotations in an analysis usually lead to associate numerical constraint to the control flow graph. The automata presented here support this method but their expressiveness offers new integration possibilities based on the partial unfolding of control flow graph. We present experimental results from the comparison of these two methods that show how the graph unfolding can improve the analysis precision. In the end, this precision gain in the worst-case execution time will ensure a better usage of the hardware as well as the absence of risks for the user or the system itself.

Les systèmes temps réel (STR) sont au coeur de machines souvent jugés critiques pour lasécurité : ils en contrôlent l’exécution afin que celles-ci se comportent de manière sûre dans le contexte d’un environnement dont l’évolution peut être imprévisible. Un STR n’a d’autre alternative que de s’adapter à son environnement : sa correction dépend des temps de réponses aux stimuli de ce dernier.Il est couramment admis que le formalisme des réseaux de Petri temporels (RdPT) est adapté àla description des STR. Cependant, la modélisation de systèmes simples, ne possédant que quelquestˆaches périodiques ordonnancées de façon basique se révèle être un exercice souvent complexe.En premier lieu, la modélisation efficace d’une gamme étendue de politiques d’ordonnancementsse heurte à l’incapacité des RdPT à imposer un ordre d’apparition à des évènements concurrentssurvenant au même instant. D’autre part, les STR ont une nette tendance à être constitués de caractéristiques récurrentes, autorisant une modélisation par composants. Or les RdPT ne sont guèreadaptés à une utilisation compositionnelle un tant soit peu générale. Afin de résoudre ces deuxproblèmes, nous proposons dans cette thèse Cifre – en partenariat entre Airbus et le Laas-Cnrs– d’étendre les RdPT à l’aide de deux nouvelles relations, les relations d’inhibition et de permission,permettant de spécifier de manière plus fine les contraintes de temps.Afin de cerner un périmètre clair d’adéquation de cette nouvelle extension à la modélisation dessystèmes temps réel, nous avons défini Pola, un langage spécifique poursuivant deux objectifs :déterminer un sous-ensemble des systèmes temps réel modélisables par les réseaux de Petri temporelsà inhibitions/permissions et fournir un langage simple à la communauté temps réel dont lavérification, idéalement automatique, est assurée par construction. Sa sémantique est donnée par traduction en réseaux de Petri temporels à inhibitions/permissions. L’explorateur d’espace d’états de laboite à outils Tina a été étendu afin de permettre la vérification des descriptions Pola / Real time systems (RTS) are at the core of safety critical devices : they control thedevices’ behavior in such a way that they remain safe with regard to an unpredictable environment. ARTS has no other choices than to adapt to its environment : its correctness depends upon its responsetime to the stimuli stemming from the environment.It is widely accepted that the Time Petri nets (TPN) formalism is adapted to the description ofRTS. However, the modeling of simple systems with only a few periodic tasks scheduled according toa basic policy remains a challenge in the worst case and can be very tedious in the most favorable one.First, we put forward some limitations of TPN regarding the modeling of a wide variety of schedulingpolicies, coming from the fact that this formalism is not always capable to impose a givenorder on events whenever they happen at the same time. Moreover, RTS are usually constituted of thesame recurring features, implying a compositional modeling, but TPN are not well adapted to sucha compositional use. To solve those problems we propose in this Cifre thesis – in partnership withAirbus and the Laas-Cnrs – to extend the formalism with two new dual relations, the forbid andallow relations so that time constraints can be finely tuned.Then, to assess this new extension for modeling of real time systems, we define Pola, a specificlanguage aimed at two goals : to determine a subset of RTS which can be modeled with forbid/allowtime Petri nets and to provide a simple language to the real time community which, ideally, can bechecked automatically. Its semantics is given by translation into forbid/allow Time Petri nets. Thestate space exploration tool of the Tina toolbox have been extended so that it can model check Poladescriptions.

Made available in DSpace on 2014-12-17T14:55:41Z (GMT). No. of bitstreams: 1 AlvaroMA_DISSERT.pdf: 1811875 bytes, checksum: d1a8b9710060f420383a8d715381bfb9 (MD5) Previous issue date: 2009-12-23 / Embedded systems are widely spread nowadays. An example is the Digital Signal Processor (DSP), which is a high processing power device. This work s contribution consist of exposing DSP implementation of the system logic for detecting leaks in real time. Among the various methods of leak detection available today this work uses a technique based on the pipe pressure analysis and usesWavelet Transform and Neural Networks. In this context, the DSP, in addition to do the pressure signal digital processing, also communicates to a Global Positioning System (GPS), which helps in situating the leak, and to a SCADA, sharing information. To ensure robustness and reliability in communication between DSP and SCADA the Modbus protocol is used. As it is a real time application, special attention is given to the response time of each of the tasks performed by the DSP. Tests and leak simulations were performed using the structure of Laboratory of Evaluation of Measurement in Oil (LAMP), at Federal University of Rio Grande do Norte (UFRN) / Os sistemas embarcados est?o amplamente difundidos atualmente. Um exemplo ? o Digital Signal Processor (DSP), que ? um dispositivo com alto poder de processamento. A contribui??o deste trabalho consiste na implementa??o em DSP da l?gica de um sistema de detec??o de vazamentos em tempo real. Dentre os v?rios m?todos de detec??o de vazamentos existentes atualmente este trabalho se desenvolve utilizando uma t?cnica baseada na an?lise da press?o no duto e que utiliza Transformada Wavelet e Redes Neurais. Nesse contexto o DSP, al?m de realizar o processamento digital do sinal de press?o, tamb?m comunica-se com um Global Positioning System (GPS), que auxilia na localiza??o do vazamento e com um sistema supervis?rio, disponibilizando informa??es para este. Para garantir robustez e confiabilidade na comunica??o entre DSP e sistema supervis?rio ? utilizado o protocolo Modbus. Como trata-se de uma aplica??o de tempo real, uma aten??o especial ? dada ao tempo de resposta de cada uma das tarefas realizadas pelo DSP. Os testes e simula??es de vazamentos foram realizados utilizando a estrutura do Laborat?rio de Avalia??o de Medi??o em Petr?leo (LAMP), da Universidade Federal do Rio Grande do Norte (UFRN)

Este trabalho apresenta um estudo sobre sistemas operacionais de tempo real (RTOS) utilizados na implementação da infraestrutura de controle digital para sistemas mecatrônicos, mas serve também como referência para outros sistemas que possuam restrições de tempo. Além de ter um caráter experimental, onde foram medidos e analisados dados como o pior tempo de resposta dos sistemas e a latência para tratamento de interrupções, este trabalho de pesquisa ainda contempla a implementação e uso de RTOS em situações práticas, bem como contempla a construção de uma plataforma geral de pesquisa que servirá de base para futuros trabalhos no laboratório de mecatrônica. Os sistemas analisados neste trabalho foram o VxWorks, QNX, Linux, RTAI, Windows XP, Windows CE e \'mü\'C/OS-II. Outro produto gerado durante este trabalho foi um Live CD para auxiliar na implementação e ensino de conceitos e sistemas de tempo real. / This work presents a study about real time operating systems (RTOS) that are utilized as infrastructure to create digital control systems for mechatronics systems, and also for systems that have critical time constraints. Parameters like worst case response time and interrupt latency were measured for each operating system. This research project also covers the implementation and use of RTOS in practical situations. A general research platform for robotics and real time research was also developed and will be used for future works in the Mechatronics Laboratory. The tested systems were VxWorks, QNX, Linux, RTAI, Windows XP, Windows CE and \'mü\'C/OS-II. Another product released during this work was a Live CD to aid the implementation and teaching of real time systems and concepts.

Orientadores: José Mario De Martino, Harlen Costa Batagelo / Dissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica e de Computação / Made available in DSpace on 2018-08-16T06:00:13Z (GMT). No. of bitstreams: 1 Reis_ClausiusDuqueGoncalves_M.pdf: 10846415 bytes, checksum: 37318c89ce60ddb5bce4efd57c86abd9 (MD5) Previous issue date: 2010 / Resumo: A modelagem e animação de rugas faciais têm sido tarefas desafiadoras, devido à variedade de conformações e sutilezas de detalhes que as rugas podem exibir. Neste trabalho, são descritos dois métodos de apresentação de rugas em tempo real, utilizando as modernas GPUs. Ambos os métodos são baseados no uso de shaders em GPU e em uma abordagem de normal mapping para aplicar rugas sobre modelos virtuais. O primeiro método utiliza áreas de influência descritas por mapas de textura para calcular a exibição de rugas sobre o modelo, controlados por um "Vetor de Ativação", que informa ao shader a visibilidade das rugas em cada uma das áreas de influência. O segundo método apresenta rugas nos modelos faciais, utilizando as informações de deslocamento dos vértices em direções pré-definidas, informadas através de um "Vetor Direção de Rugas", que informa o sentido que o deslocamento de um vértice causa o surgimento de rugas / Abstract: The modeling and animation of facial wrinkles have been challenging tasks, due to the variety of conformations and detail subtleness that the wrinkles can display. In this paper, we describe two methods to present wrinkles in real time, using modern GPUs. Both methods are based on the use of GPU shaders and a normal mapping approach to apply wrinkles on virtual models. The first method uses influence areas described by texture maps to calculate the display of wrinkles on the model, controlled by an "Activation Vector", which tells the shader the appearance of wrinkles in each area of influence. The second method presents wrinkles on facial models using the vertex displacement information in predetermined directions, informed by a "Wrinkles Direction Vector", informing the direction that the displacement of a vertex causes the presentation of wrinkles / Mestrado / Engenharia de Computação / Mestre em Engenharia Elétrica e de Computação

Orientador: Arnaldo Vieira Moura / Tese (doutorado) - Universidade Estadual de Campinas, Instituto de Computação / Made available in DSpace on 2018-08-15T05:28:23Z (GMT). No. of bitstreams: 1 Bonifacio_AdilsonLuiz_D.pdf: 1228504 bytes, checksum: 62db4b0286cfd1c735336e429629b3de (MD5) Previous issue date: 2009 / Resumo: O objetivo deste trabalho é prover métodos eficientes de geração de casos de teste para sistemas reativos críticos. Sistemas dessa natureza compreendem sistemas de tempo real e com transformações de contexto. Uma das técnicas mais usadas na geração de conjuntos de teste tem sido a abordagem baseada em modelos formais. Neste caso, os formalismos fornecem uma base sólida para que a atividade de teste seja efetuada de forma precisa e segura. Este trabalho propõe a construção de modelos formais, métodos e técnicas, bem como estratégias de teste, para dar suporte ao processo de geração automática de conjuntos de teste, aplicáveis a sistemas complexos. Porém, o processo de geração de testes baseado em modelos se torna, muitas vezes, impraticável em aplicações reais, devido ao problema da explosão combinatória de estados. Daí a necessidade de se encontrar modelos adequados que capturem o comportamento desejado dos sistemas a serem testados, bem como a importância de se construir métodos que contornem o problema da explosão do espaço de estado, de maneira razoável, permitindo que a geração de testes seja um processo aplicável a sistemas complexos. Entre os modelos abordados neste trabalho estão: (i) as tradicionais Máquinas de Estados Finito (FSM); (ii) uma extensão das FSMusando variáveis de contexto, as Máquinas de Estados Finito Estendida (EFSM); (iii) a extensão temporizada de EFSM (TEFSM), que possui, não apenas variáveis de contexto, mas também variáveis relógio; (iv) os modelos temporizados com entradas e saídas independentes, conhecidos como Timed I/O Automata (TIOA); e (v) uma extensão proposta para TIOA, denominado Timed I/O Context Automata (TIOCA), para compreender a evolução contínua de tempo e também as transformações de contexto. Com relação a geração de testes baseada em tais modelos, foi proposto, primeiramente, uma técnica de derivação de sequências de confirmação para TEFSM, usando model-checking. Em seguida, foi proposta uma generalização para um método de geração de conjuntos completos de teste usando FSM. Também foi desenvolvido um novo método de discretização do modelo TIOA, provendo a base necessária para a geração de casos de teste usando os conceitos de proposta de teste e produto síncrono. Por fim, foi desenvolvida uma extensão do método de discretização para TIOA também proposto neste trabalho, aplicado ao modelo TIOCA, permitindo a geração de testes em sistemas com evolução contínua de tempo e fluxo de dados, usando os conceitos de proposta de teste e produto de TIOCA / Abstract: This work aims to provide efficient test case generation methods for reactive and critical systems. In general, reactive and critical systems are real-time systems with context transformations. One of the most promising techniques for generating test suites is model-based testing. The formalisms supply the basis to perform a precise and dependable testing activity. In this scenery, our work proposes a construction of formal models, methods and techniques, as well as testing strategies, to support the process of automatically generating test suites for complex systems. However, the test generation process using formal models is usually infeasible in real applications, due to the state space explosion. Therefore, we need to find out suitable models to capture the system behaviors, and also to construct methods that can overcome the explosion problem, in a reasonable way, allowing the generation of test suites for complex systems. In this work we treat the following formal models: the conventional FSM; an extension of FSM using context variables (EFSM); the proposed extension of EFSM (TEFSM) to capture context variables and also clock variables; timed models, with disassociated input and output actions, called TIOA; and the proposed extension for TIOA, so-called TIOCA, to capture continuous time evolution and context transformations. In a first step of this work we proposed a technique to derive confirming sequences for TEFSM, using model-checking. Next, a classical method to generate complete test suites was generalized for FSM.We also proposed a new discretizationmethod for TIOA models, allowing the test case generation using test purpose and the synchronous product. Lastly, we extended the discretization method for TIOA to obtain more compact grid automata for TIOCA models, allowing the test case generation for systems with continuous time evolution and data flow transformations, using the notion of test purpose and the product of TIOCA / Doutorado / Teoria da Computação e Teste de Sistemas / Doutor em Ciência da Computação

Submitted by Lúcia Brandão (lucia.elaine@live.com) on 2015-12-11T18:22:47Z No. of bitstreams: 1 Dissertação - Rawlinson da Silva Gonçalves.pdf: 25918994 bytes, checksum: 31dbbcde9e265b8281faa9ef25a9b346 (MD5) / Approved for entry into archive by Divisão de Documentação/BC Biblioteca Central (ddbc@ufam.edu.br) on 2016-01-20T15:20:18Z (GMT) No. of bitstreams: 1 Dissertação - Rawlinson da Silva Gonçalves.pdf: 25918994 bytes, checksum: 31dbbcde9e265b8281faa9ef25a9b346 (MD5) / Approved for entry into archive by Divisão de Documentação/BC Biblioteca Central (ddbc@ufam.edu.br) on 2016-01-20T15:23:25Z (GMT) No. of bitstreams: 1 Dissertação - Rawlinson da Silva Gonçalves.pdf: 25918994 bytes, checksum: 31dbbcde9e265b8281faa9ef25a9b346 (MD5) / Made available in DSpace on 2016-01-20T15:23:25Z (GMT). No. of bitstreams: 1 Dissertação - Rawlinson da Silva Gonçalves.pdf: 25918994 bytes, checksum: 31dbbcde9e265b8281faa9ef25a9b346 (MD5) Previous issue date: 2015-07-10 / FAPEAM - Fundação de Amparo à Pesquisa do Estado do Amazonas / Embedded systems have evolved significantly in recent years,mainlyduetoadvances in technology, cost reduction of electronic equipment, and mainly the popularization of mobile devices. Many of these systems require energy resources from battery to maintain the operation of their various components. However, for these devices to have a good autonomy, several techniques and methodologies have been implemented to better manage energy consumption of the system as a whole. This need has contributed to the rise of various lines of research, mainly in the area of real-time systems, where the complicating factor is not only reducing energy consumptionbutalsorespectthetime constraints of all tasks running on the system. Thus, this work aims to maximize energy gains from the use of intra-task dynamic voltage and frequency scaling technique, also known as intra-task DVFS. The proposed online methodology aims to achieve better management of exchanging voltages and frequency of the processor, through a collaborative approach between real-time applications and the operating system. Therefore, both can work together, within the kernel of the system, to reduce the response times of the processor context switches, mainly after preemptions. The experimental results, using the C-Benchmarck, showed that it is possible to decrease about 6% processor power consumption even performing all tasks in the worst case. / Os sistemas embarcados têm evoluído significativamente nos últimos anos, principalmente devido aos avanços da tecnologia, a redução dos custos dos equipamentos eletrônicos e a popularização dos dispositivos móveis. Muitos desses sistemas dependem da energia provenientes de baterias para manter o funcionamento dos seus diversos componentes. No entanto, para que esses dispositivos tenham uma boa autonomia, várias técnicas e metodologias têm sido propostas para melhor gerenciar o consumo de energia do sistema como um todo. Essa necessidade tem contribuído para o surgimento de diversas linhas de pesquisa, principalmente na área de sistemas de tempo real, onde o fator complicante não está somente em reduzir o consumo de energia, mas também em respeitar as restrições temporais de todas as tarefas em execução no sistema. Sendo assim, este trabalho tem como objetivo diminuir o consumo de energia do processador utilizando a técnica de escalonamento dinâmicodetensõesefrequênciasdo processador intra-tarefa, também conhecido como DVFS intra-tarefa (em inglês, Dynamic Voltage and Frequency Scaling). A metodologia online proposta visa realizar ogerenciamentodastrocasdetensõesefrequênciasdoprocessador, através de uma abordagem colaborativa entre as aplicações de tempo real e o sistema operacional. Dessa forma, ambos podem trabalhar em conjunto, dentro do núcleo do sistema, para diminuir os tempos de resposta dos chaveamentos de tensões e frequências do processador, principalmente diante de sucessivas preempções entre as aplicações de tempo real em execução no sistema. Os resultados experimentais dessa metodologia, utilizando o C-Benchmarck, mostraram que é possível diminuircercade6%oconsumo de energia do processador, mesmo executando todas as tarefasnopiorcaso.