Les limites rencontrées par les dernières générations de mémoires Flash et DRAM (Dynamic Random Access Memory) nécessitent la recherche de nouvelles variables physiques (autres que la charge et la tension), de nouveaux dispositifs ainsi que de nouvelles architectures de circuits. Plusieurs dispositifs à résistance variable sont très prometteurs. Parmi eux, les OxRRAMs (Oxide Resistive Random Access Memory) et les CBRAMs (Conductive Bridge Random Access Memory) sont de sérieux candidats pour la prochaine génération de mémoire dense. Ce travail se concentre donc sur le rôle des mémoires résistives (OxRRAM et CBRAM) dans les mémoires embarquées et plus particulièrement dans les FPGAs. Pour cela, nous avons développé un modèle compact, outil indispensable à la conception de circuits intégrés. Ensuite, nous avons conçus de nouveaux circuits non volatiles tels que des flips-flops (NVFF), des tables de correspondance (NVLUT), des commutateurs 2x2 ainsi que des SRAMs (NVSRAM). Ces structures ont finalement été simulées dans le cas d’un FPGA, afin de vérifier l’impact de celles-ci sur la surface, le délai ainsi que la puissance. Nous avons comparé les résultats pour un FPGA à base de NVLUTs utilisant une structure 1T-2R composée de CBRAMs par rapport à un FPGA plus classique utilisant des SRAMs. Nous réduisons ainsi la taille de 5%, la consommation de 18% et améliorons la vitesse de fonctionnement de 24%. La thèse aborde la modélisation compacte, la conception des circuits, et l’évaluation de systèmes incluant des mémoires résistives. / The grave challenges to future of traditional memories (flash and DRAM) at 1X nm regime has resulted in increased quest for new physical state variables (other than charge or voltage), new devices and architectures offering memory and logic functions beyond traditional transistors. Many thin film devices with resistance change phenomena have been extensively reported as ’promising candidates’. Among them, Ox- ide Resistive Memory (OxRRAM) and Conductive Bridge Resistive Memory (CBRAM) are leading contenders for the next generation high density memories. In this work, we focus on the role of Resistive Memories in embedded memories and their impact on FPGAs in particular. We begin with the discussion on the compact modeling of resistive memory devices for design enabling, we have designed novel circuits of non- volatile flip-flop (NVFF), non-volatile look-up table (NVLUT), non-volatile 2x2 switch and non-volatile SRAM (NVSRAM) using Resistive Memories. We simulated the impact of these design structures on the FPGA system assessing the performance parameters of area, delay and power. By using the novel 1T-2R memory element concept of CBRAMs in FPGAs to implement Look-up Tables (NVLUT), we would scale down the area impact by 5%, enhance speed by 24% and reduce the power by 18% compared to SRAM based FPGAs. The thesis addresses aspects of compact modeling, circuit design and system evaluation using resistive memories.

Alors que les mémoires non-volatiles conventionnelles, telles que les mémoires flash à grille flottante, deviennent de plus en plus complexes à intégrer et souffrent de performances et d’une fiabilité de plus en plus réduite, les mémoires à variation de résistance (RRAM) telles que les OxRAM, CBRAM, MRAM ou PCM sont vues dans la communauté scientifique comme une alternative crédible. Cependant, les architectures de RRAM standard (telles que la 1Transistor-1RRAM) ne sont pas compétitives avec les mémoires flash sur le terrain de la densité. Ainsi, cette thèse se propose d’explorer le potentiel des architectures RRAM sans transistor que sont l’architecture Crosspoint et l’architecture VRRAM.Dans un premier temps, le positionnement des architectures Crosspoint et VRRAM dans la hiérarchie mémoire est étudié. De nouvelles problématiques, telles que les courant de sneakpath, la chute de tension dans les métaux ou la surface des circuits périphériques sont identifiées et modélisées. Dans un second temps, des solutions circuit répondant aux problématiques évoquées précédemment sont proposées. Finalement, cette thèse se propose d’explorer les opportunités ouvertes par l’utilisation de transistors innovants pour améliorer la densité ou les performances des architectures mémoires utilisant des RRAM. / While conventional non-volatiles memories, such as floating gate Flash memories, are becoming more and more difficult and costly to integrate and suffer of reduced performances and reliability, emerging resistive switching memories (RRAM), such as OxRAM, CBRAM, MRAM or PCM, are seen in the scientific community as a good way for tomorrow’s high-density memories. However, standard RRAM architectures (such as 1 Transistor-1 RRAM) are not competitive with flash technology in terms of density. Thereby, this thesis proposes to explore the opportunities opened by transistor-less RRAM architectures: Crosspoint and Vertical RRAM (VRRAM) architectures.First, the positioning of Crosspoint and VRRAM architectures in the memory hierarchy is studied. New constraints such as the sneakpath currents, the voltage drop through the metal lines or the periphery area overhead are identified and modeled. In a second time, circuit solutions answering to previously mentioned effects are proposed. Finally, this thesis proposes to explore new opportunities opened by the use of innovative transistors to improve the density or the performances of RRAM-based memory architectures.

Recently an effective usage of the chip area plays an essential role for System-on-Chip (SOC) designs. Nowadays on-chip memories take up more than 50%of the total die-area and are responsible for more than 40% of the total energy consumption. Cache memory alone occupies 30% of the on-chip area in the latest microprocessors. This thesis project “System Level Exploration of RRAM for SRAM Replacement” describes a Resistive Random Access Memory (RRAM) based memory organizationfor the Coarse Grained Reconfigurable Array (CGRA) processors. Thebenefit of the RRAM based memory organization, compared to the conventional Static-Random Access Memory (SRAM) based memory organization, is higher interms of energy and area requirement. Due to the ever-growing problems faced by conventional memories with Dynamic Voltage Scaling (DVS), emerging memory technologies gained more importance. RRAM is typically seen as a possible candidate to replace Non-volatilememory (NVM) as Flash approaches its scaling limits. The replacement of SRAMin the lowest layers of the memory hierarchies in embedded systems with RRAMis very attractive research topic; RRAM technology offers reduced energy and arearequirements, but it has limitations with regards to endurance and write latency. By reason of the technological limitations and restrictions to solve RRAM write related issues, it becomes beneficial to explore memory access schemes that tolerate the longer write times. Therefore, since RRAM write time cannot be reduced realistically speaking we have to derive instruction memory and data memory access schemes that tolerate the longer write times. We present an instruction memory access scheme to compromise with these problems. In addition to modified instruction memory architecture, we investigate the effect of the longer write times to the data memory. Experimental results provided show that the proposed architectural modifications can reduce read energy consumption by a significant frame without any performance penalty.

In first part, the supercritical CO2 (SCCO2) fluid technology is employed to improve the device properties of ZnO TFT. The SCCO2 fluid exhibits liquid-like property, which has excellent transport ability. Furthermore, the SCCO2 fluid has gas-like and high-pressure properties to diffuse into the nanoscale structures without damage. Hence, the SCCO2 fluid can carry the H2O molecule effectively into the ZnO films at low temperature and passivate traps by H2O molecule at low temperature. The experimental results show that the on current, sub-threshold slope, and threshold voltage of the device were improved significantly. Next, the electrical degradation behaviors and mechanisms under drain bias stress of a-IGZO TFTs were investigated. A current crowding effect and an obvious capacitance-voltage stretch-out were observed after stress. During the drain-bias stress, the oxygen would be absorbed on the back channel near the drain region of IGZO film. Therefore, the carrier transport is impeded by the additional energy barrier near drain region induced by the adsorbed oxygen, which forms a depletion layer to generate the parasitism resistance. We also investigated the RRAM device based on IGZO film, and proposed the related physical mechanism models. The IGZO RRAM will be very promising for integration with IGZO TFTs for advanced system-on-panel display applications to be a transparent embedded system. In this part, the transparent RRAM device with ITO/IGZO/ITO structure was fabricated. The proposed device presents an excellent bipolar resistive switching characteristic and good reliability. The bipolar switching mechanism of our device is dominated by the formation and rupture of the oxygen vacancies in a conduction path. The influence of electrode material on resistance switching characteristic is investigated through Pt/IGZO/TiN and Ti/IGZO/TiN structure. As the bias applied on the Ti or TiN, the Ti or TiN electrode can play the role of oxygen reservoir to absorb/discharge oxygen ions. Therefore, the device presents a bipolar resistive switching characteristic. However, as the bias applied on the Pt electrode, the device presents a unipolar resistive switching characteristic. Because the Pt electrode can¡¦t store the oxygen ion, the device should use the joule heating mode to rupture the conduction path and present the unipolar resistive switching characteristic. Finally, the resistive switching properties of IGZO film deposited at different oxygen content were investigated, since the resistance switching behaviors are related to the formation and rupture of filaments composed of oxygen vacancies in the IGZO matrix. Experiment results show that the HRS current decreases when the oxygen partial pressure gradually increases. Based on the XPS analysis, these phenomena are related to the non-lattice oxygen concentration. With increasing oxygen ratio, the filaments will rupture completely through the abundant non-lattice oxygen inducing oxidation, which leads to HRS current decrease and an increase in the memory window.

This study is focuses on the resistance switching physical mechanism in hafnium oxide (HfO2) of resistive random access memory (RRAM). HfO2 was taken as the resistance switching layer because HfO2 is extremely compatible with the prevalent complementary metal oxide semiconductor (CMOS) process. The detail physical mechanism is studied by the stable RRAM device (Ti/HfO2/TiN), which is offered from Industrial Technology Research Institute (ITRI). In this study, the resistance switching property of two different forming conductions are compared, including DC sweeping forming and AC pulse forming. In general, forming is a pivotal process in resistance random access memory (RRAM) to activate the resistance switching behavior. However, over forming would lead to device damage. The overshoot current has been considered as a degradation reason during the forming process. The circuit design is used to obtain the overshoot effect of DC sweeping forming by oscilloscope and semiconductor parameter analyzer system. The quantity of charge through the switching layer has been proven as the key element in the formation of the conduction path. Ultra-fast pulse forming can form a discontinuous conduction path to reduce the operation power.

The resistance random access memory (RRAM) is one of the most popular of the next generation memories with the high operating speed, reliability and the smallest miniature size. RRAM has metal-insulator-metal structure that can greatly reduce the difficulty of entry, but the biggest problem is how to choose the insulator. We selected silicon-based materials to match the intergrated circuits manufacturing process. In this work, sputtering titanium doping in the silicon oxide thin film has a stable characteristic of resistance switching. By material analyzing, we found that supercritical carbon dioxide fluid (SCCO2) treatment can passivate the silicon oxide defect and the self-reduction of titanium oxide, but it also brought OH group into our thin film. So we observed the interface type characteristic of resistance switching. Using constant voltage sampling experiment extract the reaction rate constant (k) and the active energy, prove that the reaction is caused by OH injection. Double-layer structure with titanium-doped and carbon-doped silicon oxide RRAM promote lower operating current by hopping conduction, which is caused by graphite oxide doping. The Space-Charge Limited Current mechanism for high limited current is proven by COMSOL electric field simulation.

abstract: The Programmable Metallization Cell (PMC) is a novel solid-state resistive switching technology. It has a simple metal-insulator-metal “MIM” structure with one metal being electrochemically active (Cu) and the other one being inert (Pt or W), an insulating film (silica) acts as solid electrolyte for ion transport is sandwiched between these two electrodes. PMC’s resistance can be altered by an external electrical stimulus. The change of resistance is attributed to the formation or dissolution of Cu metal filament(s) within the silica layer which is associated with electrochemical redox reactions and ion transportation. In this dissertation, a comprehensive study of microfabrication method and its impacts on performance of PMC device is demonstrated, gamma-ray total ionizing dose (TID) impacts on device reliability is investigated, and the materials properties of doped/undoped silica switching layers are illuminated by impedance spectroscopy (IS). Due to the inherent CMOS compatibility, Cu-silica PMCs have great potential to be adopted in many emerging technologies, such as non-volatile storage cells and selector cells in ultra-dense 3D crosspoint memories, as well as electronic synapses in brain-inspired neuromorphic computing. Cu-silica PMC device performance for these applications is also assessed in this dissertation. / Dissertation/Thesis / Doctoral Dissertation Electrical Engineering 2017

abstract: Chalcogenide glass (ChG) materials have gained wide attention because of their applications in conductive bridge random access memory (CBRAM), phase change memories (PC-RAM), optical rewritable disks (CD-RW and DVD-RW), microelectromechanical systems (MEMS), microfluidics, and optical communications. One of the significant properties of ChG materials is the change in the resistivity of the material when a metal such as Ag or Cu is added to it by diffusion. This study demonstrates the potential radiation-sensing capabilities of two metal/chalcogenide glass device configurations. Lateral and vertical device configurations sense the radiation-induced migration of Ag+ ions in germanium selenide glasses via changes in electrical resistance between electrodes on the ChG. Before irradiation, these devices exhibit a high-resistance `OFF-state' (in the order of 10E12) but following irradiation, with either 60-Co gamma-rays or UV light, their resistance drops to a low-resistance `ON-state' (around 10E3). Lateral devices have exhibited cyclical recovery with room temperature annealing of the Ag doped ChG, which suggests potential uses in reusable radiation sensor applications. The feasibility of producing inexpensive flexible radiation sensors has been demonstrated by studying the effects of mechanical strain and temperature stress on sensors formed on flexible polymer substrate. The mechanisms of radiation-induced Ag/Ag+ transport and reactions in ChG have been modeled using a finite element device simulator, ATLAS. The essential reactions captured by the simulator are radiation-induced carrier generation, combined with reduction/oxidation for Ag species in the chalcogenide film. Metal-doped ChGs are solid electrolytes that have both ionic and electronic conductivity. The ChG based Programmable Metallization Cell (PMC) is a technology platform that offers electric field dependent resistance switching mechanisms by formation and dissolution of nano sized conductive filaments in a ChG solid electrolyte between oxidizable and inert electrodes. This study identifies silver anode agglomeration in PMC devices following large radiation dose exposure and considers device failure mechanisms via electrical and material characterization. The results demonstrate that by changing device structural parameters, silver agglomeration in PMC devices can be suppressed and reliable resistance switching may be maintained for extremely high doses ranging from 4 Mrad(GeSe) to more than 10 Mrad (ChG). / Dissertation/Thesis / Ph.D. Electrical Engineering 2013

In recent years, neuromorphic architectures have been an increasingly effective tool used to solve big data problems. Hardware neural networks have not been able to fully exploit the power efficient properties of the neural paradigm, however, due to limitations in standard CMOS. One of the largest challenges is the quadratic scaling of the synapses in a neural network. There has been some work in using post CMOS technology as synapses to overcome this limitation, but systems to date have not been scalable due to the design of their neurons. This dissertation aims to design and build scalable neural network architectures that can use emerging resistive memory technology as synapses. Using analog computing techniques to build networks is promising, especially due to the development of dense, CMOS compatible analog resistive memories. Building functional analog networks in advanced technology nodes, however, is challenging due to the relatively poor performance of analog components in these nodes. This work explores oscillatory neural networks (ONNs), which use phase as the analog state variable instead of voltage or current, reducing the number of traditional analog components required and making the networks better-suited for advanced nodes. This thesis develops additional ONN theory with regard to hardware networks, since previous work did not consider the effect of transmission delay on network dynamics. Transmission delay is proven to cause desynchronization in unmodified ONNs, and the theoretical analysis suggests ways to build networks which do synchronize. Conclusions from the theoretical development are used to build a PLL-based ONN in hardware. The PLL-based ONN is more energy efficient than comparable systems implemented in digital CMOS, although the neuron area is somewhat larger. The measurement of the PLL-based ONN also reveals additional poorly-studied facets of ONN dynamics. Using the knowledge gained from the PLL-based ONN, a larger, PLL-free ONN is built in the same technology. Removing the PLL in each neuron reduces the power and area consumption without sacrificing any functionality.This dissertation demonstrates that ONNs are well-suited to take advantage of emerging resistive memory technology to build efficient hardware neural networks.

<div>Silicon based semiconductor technology is facing more and more challenges to continue the Moore's law due to its fundamental scaling limitations. To continue the pace of progress of device performance for both logic and memory devices, researchers are exploring new low-dimensional materials, e.g. nanowire, nanotube, graphene and hexagonal boron nitride. Transition metal dichalcogenides (TMDs) are attracted considerable attention due their atomically thin nature and proper bandgap at the initial study. Recently, more and more interesting properties are found in these materials, which will bring out more potential usefulness for electronic applications. Competing with the silicon device performance is not the only goal in the potential path finding of beyond silicon. Low-dimensional materials may have other outstanding performances as an alternative materials in many application realms. </div><div><br></div><div>This thesis explores the potential of TMD based devices in memory and logic applications. For the memory application, TMD based vertical devices are fully studied. Two-terminal vertical transition metal dichalcogenide (TMD) based memory selectors were firstly built and characterized, exhibiting better overall performance compared with some traditional selectors. Polymorphism is one of unique properties in TMD materials. 2D phase engineering in TMDs attracted great attention. While electric switching between semiconductor phase to metallic phase is the most desirable. In this thesis, electric field induced structural transition in MoTe₂ and Mo_1-xW_xTe₂ is firstly presented. Reproducible bipolar resistive random access (RRAM) behavior is observed in MoTe₂ and Mo_1-xW_xTe₂ based vertical devices. Direct confirmation of a phase transition from a 2H semiconductor to a distorted 2H_d metallic phase was obtained after applying an electric field. Set voltage is changed with flake thickness, and switching speed is less than 5 ns. Different from conventional RRAM devices based on ionic migration, the MoTe₂-based RRAMs offer intrinsically better reliability and control. In comparison to phase change memory (PCM)-based devices that operate based on a change between an amorphous and a crystalline structure, our MoTe₂-based RRAM devices allow faster switching due to a transition between two crystalline states. Moreover, utilization of atomically thin 2D materials allows for aggressive scaling and high-performance flexible electronics applications. Both of the studies shine lights on the new application in the memory field with two-dimensional materials.<br></div><div><br></div><div>For the logic application, the ultra thin body nature of TMDs allows for more aggressive scaling compared with bulk material - silicon. Two aspects of scaling properties in TMD based devices are discussed, channel length scaling and channel width scaling. A tunability of short channel effects in MoS₂ field effect transistor (FET) is reported. The electrical performance of MoS₂ flakes is governed by an unexpected dependence on the effective body thickness of the device which in turn depends on the amount of intercalated water molecules that exist in the layered structure. In particular, we observe that the doping stage of a MoS₂ FET strongly depends on the environment (air/vacuum). For the channel width scaling, the impact of edge states in three types of TMDs, metallic T_d-phase WTe₂ as well as semiconducting 2H-phase MoTe₂ and MoS₂ were explored, by patterning thin flakes into ribbons with varying channel widths. No obvious charge depletion at the edges is observed for any of these three materials, which is different from what has been observed in graphene nanoribbon devices. </div>