Thesis (M.App.Sc.) - Carleton University, 2005. / Includes bibliographical references (p. 109-112). Also available in electronic format on the Internet.

Thesis (Ph. D.)--Hong Kong University of Science and Technology, 2004. / Includes bibliographical references (leaves 91-101). Also available in electronic version. Access restricted to campus users.

Thesis (Ph.D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2009. / Committee Chair: Mark G. Allen; Committee Member: J. Stevenson Kenney; Committee Member: Joy Laskar; Committee Member: Oliver Brand; Committee Member: Peter Hesketh.

Thesis (Ph. D.)--University of Florida, 2004. / Title from title page of source document. Document formatted into pages; contains 186 pages. Includes vita. Includes bibliographical references.

Thesis (M. S.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2010. / Committee Chair: Cressler, John; Committee Member: Laskar, Joy; Committee Member: Papapolymerou, John. Part of the SMARTech Electronic Thesis and Dissertation Collection.

Thesis (Ph.D.)--Hong Kong University of Science and Technology, 2005. / Includes bibliographical references. Also available in electronic version.

Thesis (Ph.D.)--University of Florida, 2005. / Title from title page of source document. Document formatted into pages; contains 141 pages. Includes vita. Includes bibliographical references.

Compressed sensing (CS) is a new signal processing approach that has disrupted the Shannon-Nyquist limit based design methodology and has opened promising avenues for building energy-efficient radio frequency integrated circuits (RFICs) for detecting and estimating particular classes (i.e. sparse) of signals. Whether in application domains where naturally occurring signals are sparse or where representations of signals subject to the fidelity limits or configuration settings of the radio equipment are often found to be sparse, the emergence of CS has forced us to re-imagine the radio receiver. While realizing some of the potential benefits promised by theory, CS-RFIC architectures proposed in earlier research were not particularly suitable for mass-market applications. This thesis demonstrates how to take a new signal processing technique all the way to the hardware level. So far, the main focus in literature has been how CS offers a significant advantage for signal processing. This work will show how CS techniques drive novel architectures down to the integrated circuit level. This requires close collaboration between communication system developers, integrated circuit designers and signal processing experts. The trans-disciplinary approach presented here has led to the unification of CS-inspired architectures for wideband signal detection with robust, legacy architectures for high-sensitivity signal reception. The result is a functionally flexible and rapidly reconfigurable CMOS RFIC compactly implemented on silicon with the potential to achieve the cost, size and power targets in mass-market applications. While the focus of this thesis is RF signal finding and reception in frequency, the CS-based RFIC design approach presented here is applicable to a wide range of other applications like direction-of-arrival and range finding. We begin by developing a signal-model driven approach for optimizing the performance of CS RF frontends (RFFEs). We consider sparse multiband signals with supports contained within a frequency span extending from fMIN to fMAX. The resulting quadrature analog-to-information converter (QAIC) is a flexible-bandwidth, blind sub-Nyquist sampling architecture optimized for energy consumption and sensitivity performance. The QAIC addresses key drawbacks of earlier CS RFFE architectures like the modulated wideband converter (MWC) that implement frequency spans extending from 0 to fMAX. While these earlier architectures, a direct implementation of CS signal processing theory, have several beneficial properties, the true cost of their proposed analog frontend significantly diminishes the sensitivity performance and energy savings that CS methods have the potential to deliver. They use periodic pseudo-random bit sequence (PRBS) generators where the clock frequency fPRBS scales up with the maximum signal frequency fMAX. In contrast, fPRBS in the QAIC RFFE scales up with the instantaneous bandwidth IBW, where IBW = ( fMAX − fMIN ). This results in significant performance advantages in terms of energy consumption and sensitivity performance. The QAIC uncouples fPRBS from fMAX by performing wideband quadrature downconversion ahead of analog mixing with PRBSs at an intermediate frequency (IF). However, the dual heterodyne architecture of the QAIC suffers from spurious responses at IF caused by gain and phase imbalance in its wideband downconverter. We then show how the direct RF-to-information converter (DRF2IC) compactly adds CS wideband detection to a direct conversion frequency-translational noise-cancelling (FTNC) receiver by introducing pseudo-random modulation of the local oscillator (LO) signals and by consolidating multiple CS measurements into one hardware branch. The DRF2IC inherits benefits of the FTNC receiver in signal reception mode. In CS wideband detection mode, the DRF2IC inherits key advantages from both the earlier lowpass CS architectures and the QAIC while avoiding the drawbacks of both. It uncouples fPRBS from fMAX in contrast with the MWC. In contrast with the QAIC, the DRF2IC employs a direct conversion RF chain with narrow bandwidth analog components at baseband thereby avoiding frequency-dependent gain and phase imbalance. The DRF2IC chip occupies 0.56mm2 area in 65nm CMOS. In reception mode, it consumes 46.5mW from 1.15V and delivers 40MHz RF bandwidth, 41.5dB conversion gain, 3.6dB noise figure (NF) and -2dBm blocker 1dB compression point (B1dB). In CS wideband detection mode, 66dB operational dynamic range, 40dB instantaneous dynamic range and 1.43GHz instantaneous bandwidth are demonstrated and 6 interferers each 10MHz wide scattered over a 1.27GHz span are detected in 1.2us consuming 58.5mW.

This thesis proposes a multifaceted production test and post-silicon yield enhancement framework for RF systems. The three main components of the proposed framework are the design, production test, and post-test phase of the overall integrated circuit (IC) development cycle. First, a circuit-sizing method is presented for incorporating test considerations into algorithms for automatic circuit synthesis/device resizing. The sizing problem is solved by using a cost metric that can be incorporated at minimal computational cost into existing optimization tools for manufacturing yield enhancement. Along with the circuit-sizing method introduced in the design phase, a low-cost test and diagnosis method is presented for multi-parametric faults in wireless systems. This test and diagnosis method allows accurate prediction of the end-to-end specifications as well as for the specifications of all the embedded modules. The procedure is based on application of optimized test stimulus and the use of a simple diode-based envelope detector to extract the transient test response envelope at RF signal nodes. This eliminates the need to make RF measurements using expensive standard testers. To further improve the parametric yield of RF circuits, a performance drift-aware adaptation scheme is proposed that automatically compensates for the loss of circuit performance in the presence of process variations. This work includes a diagnosis algorithm to identify faulty circuits within the system and a compensation process that adjusts tunable components to reduce the effects of performance variations. As a result, all the mentioned components contribute to producing a low-cost production test and to enhancing post-silicon parametric yield.

For the first method, a novel linearization scheme for CMOS double-balanced mixer based on the use of multi-bias dual-gate transistors is presented. In this technique, two intermodulation distortion components with proper phase relationship, generated by devices operating at different bias conditions, are added together to cancel each other for the improvement of mixer's linearity. The measured performance of a fabricated CMOS mixer operating at RF frequency of 2.45GHz and LO frequency of 2.35GHz is demonstrated. Over 35dB of IMD reduction is achieved by the proposed method under optimal biasing condition. / In the second design, a novel linearization scheme for cascode amplifier based upon capacitive feedback is presented. This method involves the optimal design of the feedback network for IMD reduction. By using Volterra series analysis, expression for IMD products is derived and the corresponding circuit parameters for optimized linearity are obtained. For experimental verification, CMOS cascode amplifiers are designed and fabricated to operate at 2.45GHz with supply voltage of 2V. By measurement, IIP3 is improved of almost 7dB by using the proposed feedback technique. The performance dependency of the fabricated amplifiers under different bias conditions is also examined. The results indicate that the proposed technique can offer low sensitivity to the variation of process parameters. / Linearity is one of the major requirements in modern communication systems due to the limited channel spacing. In the past years, various linearization schemes have been studied extensively for RF circuit design such as low-noise amplifiers and power amplifiers. These techniques offer IMD reduction at the expense of circuit complexity. In the last decade, much effort has been devoted to the development of single-chip RF transceiver using sub-micron CMOS technology. This thesis presents three simple and effective linearization techniques for CMOS mixer and amplifier design. They are experimentally verified by circuit fabrication based on 0.35mum CMOS process. / The last approach combines the advantages of source degeneration and the capacitive feedback for cascode amplifier linearization. Experiments are performed on CMOS amplifiers operating at 2.45GHz, and more than 11dB of IIP3 enhancement is observed. / Au Yeung, Chung Fai. / "August 2007." / Adviser: Chang Kwok Keung. / Source: Dissertation Abstracts International, Volume: 69-02, Section: B, page: 1189. / Thesis (Ph.D.)--Chinese University of Hong Kong, 2007. / Includes bibliographical references (p. 153-161). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Electronic reproduction. [Ann Arbor, MI] : ProQuest Information and Learning, [200-] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstract in English and Chinese. / School code: 1307.