The major limiting factor of DRAM access time is the low transconductance of the MOSFET's which have only limited current drive capability. The bipolar junction transistor(BJT) has a collector current amplification factor, ��, times base current and is limited mostly by the willingness to supply this base current. This collector current is much larger than the MOSFET drain current under similar conditions. The requirements for low power and low power densities results in lower power supply voltages which are also inconsistent with the threshold voltage variations in CMOS technology, as a consequence at least pulsed body bias or synchronous body bias will probably be utilized. Given that of the CMOS body will be driven or the CMOS gate and body connected a BJT technique is proposed for ultra low voltages like Vdd=0.5. Utilizing present CMOS process technology good results can be achieved with ultra low power using gate-body connected transistors and a current sense amplifier. / Graduation date: 1999

Taiwan¡¦s DRAM has high technology, strong capital, and standardized products, but it still can not be escaped from economic fluctuations. With this impact, Taiwan¡¦s DRAM has faced the problem of cash flow imbalance; moreover, the problem is going from bad to worse. The study is based on the view of system dynamics and focuses on fixed assets and investment skills of the investment-cash flow, operating cash flow, and business cycles of Taiwan¡¦s DRAM. It considers the features of dynamic complex, including loop, time delay and nonlinear and constructs a system dynamics model. The model would apply key elements to suppose an investment strategy and then to mimic an investment situation. The aim of the study will figure out the suitable investment strategy to assistant Taiwan¡¦s DRAM making the most of its inputs. The study discovers: (1) the best investment strategy for 10 year is 5.0 (to invest three fixed asset sets); for 30 year is 6.0 (to invest manufacturing skills and one fixed asset set) and 7.0 (to invest manufacturing skills and two fixed asset sets), (2) the most effective element for investment strategy in the long run is to invest fixed asset sets rather than upgrading manufacturing skills, (3) to keep investing in semiconductor fabrications would endanger Taiwan¡¦s DRAM itself; hence the superior limit investment quantity for fixed assets are five to six sets,(4) the best investment timing for Taiwan¡¦s DRAM is the first two business cycle season, and (5)when Taiwan¡¦s DRAM faces economic downturn, the effective investment strategy for it is few. If Taiwan¡¦s DRAM doesn¡¦t change its industrial structure, it will face the high risk of loss.

In first part, the supercritical CO2 (SCCO2) fluid technology is employed to improve the device properties of ZnO TFT. The SCCO2 fluid exhibits liquid-like property, which has excellent transport ability. Furthermore, the SCCO2 fluid has gas-like and high-pressure properties to diffuse into the nanoscale structures without damage. Hence, the SCCO2 fluid can carry the H2O molecule effectively into the ZnO films at low temperature and passivate traps by H2O molecule at low temperature. The experimental results show that the on current, sub-threshold slope, and threshold voltage of the device were improved significantly. Next, the electrical degradation behaviors and mechanisms under drain bias stress of a-IGZO TFTs were investigated. A current crowding effect and an obvious capacitance-voltage stretch-out were observed after stress. During the drain-bias stress, the oxygen would be absorbed on the back channel near the drain region of IGZO film. Therefore, the carrier transport is impeded by the additional energy barrier near drain region induced by the adsorbed oxygen, which forms a depletion layer to generate the parasitism resistance. We also investigated the RRAM device based on IGZO film, and proposed the related physical mechanism models. The IGZO RRAM will be very promising for integration with IGZO TFTs for advanced system-on-panel display applications to be a transparent embedded system. In this part, the transparent RRAM device with ITO/IGZO/ITO structure was fabricated. The proposed device presents an excellent bipolar resistive switching characteristic and good reliability. The bipolar switching mechanism of our device is dominated by the formation and rupture of the oxygen vacancies in a conduction path. The influence of electrode material on resistance switching characteristic is investigated through Pt/IGZO/TiN and Ti/IGZO/TiN structure. As the bias applied on the Ti or TiN, the Ti or TiN electrode can play the role of oxygen reservoir to absorb/discharge oxygen ions. Therefore, the device presents a bipolar resistive switching characteristic. However, as the bias applied on the Pt electrode, the device presents a unipolar resistive switching characteristic. Because the Pt electrode can¡¦t store the oxygen ion, the device should use the joule heating mode to rupture the conduction path and present the unipolar resistive switching characteristic. Finally, the resistive switching properties of IGZO film deposited at different oxygen content were investigated, since the resistance switching behaviors are related to the formation and rupture of filaments composed of oxygen vacancies in the IGZO matrix. Experiment results show that the HRS current decreases when the oxygen partial pressure gradually increases. Based on the XPS analysis, these phenomena are related to the non-lattice oxygen concentration. With increasing oxygen ratio, the filaments will rupture completely through the abundant non-lattice oxygen inducing oxidation, which leads to HRS current decrease and an increase in the memory window.

With the progress of technology, large capacity and scalable are required for the future. Recent years, the physical limit is approached and a next-generation memory is needed in the future. In addition, non- volatile memory occupies more than 96% in the memory market, and RRAM has great advantages such as simple structure, high scalable, low operation voltage, high operation speed, high endurance and retention. That is the reason RRAM is the candidate in the next generation. In this experiment, multi-sputtering was used to deposit Zr:SiO 2 and Pt on TiN bottom electrode. The sandwich structure was metal/insulator/metal (MIM). With the different dielectric constant material, a different electrical field will be produced. And then I-V measurement and materials analysis were used to investigate the characteristic of the RRAM. At first, a forming process is required to the RRAM. The device was swept from negative to positive voltage and obtained the conduction mechanism from curve fitting. The different dielectric constant materials were used to fabricate the RRAM. High and low dielectric materials were HfO 2 and BN, respectively. The electric field distribution is centralized in low dielectric material so the electrons will drift to the direction of electric field. Hence, the Vset will be centralized and more stable. We also fabricated a Zr:SiO 2 /C:SiO 2 RRAM as an high K and low K material. The current fitting results that a hopping conduction occurs in low resistive state (LRS) and high resistive state (HRS). Both from Raman spectrum and FT-IR spectrum, a graphene oxide was existed in the C:SiO 2 thin film. While the filament was form, the tip of the filament will approach the graphene oxide because of the point effect. Hence, the resistance switching will happen in the grapheme oxide and set voltage will be more stable and lower the operated current. Next, an ICP treatment was used in order to "burn" the carbon in SiO 2 . The purpose is to make an extremely low K material and ignore the effect of the existence of carbon. From the FT-IR spectrum, the carbon signals were disappeared after the ICP oxygen plasma treatment. In the I-V fitting diagram, space char limit results in the high voltage region. The electrical field simulation was an auxiliary tool which shows a strong electrical field occurs in the extremely low K area. While the electrons flow through the conduction path, they will be confined in the porous area. The operation current will decrease because of the limited conduction area.

Main memory system performance is crucial for high performance microprocessors. Even though the peak bandwidth of main memory systems has increased through improvements in the microarchitecture of Dynamic Random Access Memory (DRAM) chips, conventional on-chip memory systems of microprocessors do not fully take advantage of it. This results in underutilization of the DRAM system, in other words, many idle cycles on the DRAM data bus. The main reason for this is that conventional on-chip memory system designs do not fully take into account important DRAM characteristics. Therefore, the high bandwidth of DRAM-based main memory systems cannot be realized and exploited by the processor. This dissertation identifies three major performance-related characteristics that can significantly affect DRAM performance and makes a case for DRAM characteristic-aware on-chip memory system design. We show that on-chip memory resource management policies (such as prefetching, buffer, and cache policies) that are aware of these DRAM characteristics can significantly enhance entire system performance. The key idea of the proposed mechanisms is to send out to the DRAM system useful memory requests that can be serviced with low latency or in parallel with other requests rather than requests that are serviced with high latency or serially. Our evaluations demonstrate that each of the proposed DRAM-aware mechanisms significantly improves performance by increasing DRAM utilization for useful data. We also show that when employed together, the performance benefit of each mechanism is achieved additively: they work synergistically and significantly improve the overall system performance of both single-core and Chip MultiProcessor (CMP) systems. / text

Bibliography: leaves 156-165. / xvi, 174 leaves : ill. ; 30 cm. / Title page, contents and abstract only. The complete thesis in print form is available from the University Library. / This thesis analyses the design of a Dynamic RAM in gallium arsenide for use as a buffer in an ATM switch. The causes of leakage are investigated and methods to overcome or compensate the leakage are devised, resulting in a memory cell with a large storage time, high speed and low power dissipation. A 14 kbit RAM array is designed and laid out in gallium arsenide. The RAM array is designed to operate over a -25oC to +125oC temperature range using process parameters which vary by up to 2 [sigma] from typical. / Thesis (M.Eng.Sc.)--University of Adelaide, Dept. of Electrical & Electronic Engineering, 1996?

Thesis (M. S. in Electrical Engineering)--Vanderbilt University, Aug. 2008. / Title from title screen. Includes bibliographical references.

Thesis--Auburn University, 2009. / Abstract. Vita. Includes bibliographical references (p. 112-113).

This thesis outlines the design and implementation of a single channel, dual polarization pulsar timing instrument for the Hartebeesthoek Radio Astronomy Observatory (HartRAO). The new timer is designed to be an improved, temporary replacement for the existing device which has been in operation for over 20 years. The existing device is no longer reliable and is di±cult to maintain. The new pulsar timer is designed to provide improved functional- ity, higher sampling speed, greater pulse resolution, more °exibility and easier maintenance over the existing device. The new device is also designed to keeping changes to the observation system to a minimum until a full de-dispersion timer can be implemented at theobservatory. The design makes use of an 8-bit Reduced Instruction Set Computer (RISC) micro-processor with external Random Access Memory (RAM). The instrument includes an IEEE-488 subsystem for interfacing the pulsar timer to the observation computer system. The microcontroller software is written in assembler code to ensure optimal loop execution speed and deterministic code execution for the system. The design path is discussed and problems encountered during the design process are highlighted. Final testing of the new instrument indicates an improvement in the sam- pling rate of 13.6 times and a significant reduction in 60Hz interference over the existing instrument.

Memory wall is becoming a more and more serious bottleneck of the processing speed of microprocessors. The mismatch between CPUs and memories has been increasing since three decades ago. SRAM was introduced as the bridge between the main memory and the CPU. SRAM is designed to be on the same die with CPU and stores temporary data and instructions that are to be processed by the CPU. Thus, the performance of SRAMs has a direct impact on the performance of CPUs. With the application of mass amount data to be processed nowadays, there is a great need for high-performance CPUs. Three dimensional CPUs and CPUs that are specifically designed for machine learning are gaining popularity. The objective of this work is to design high-performance SRAM for these two emerging applications. Firstly, a novel delay cell based on dummy TSV is proposed to replace traditional delay cells for better timing control. Secondly, a unique SRAM with novel architecture is custom designed for a high-performance machine learning processor. Post-layout simulation shows that the SRAM works well with the processing core and its design is optimized to work well with machine learning processors based on convolutional neural networks. A prototype of the SRAM is also tapped out to further verify our design.