Modern communication systems require high performance radio frequency (RF) and microwave circuits and devices. This is becoming increasingly challenging to realize in the content of cost/size constraints. Integrated circuits (ICs) satisfy the cost/size requirement, but performance is often sacri¯ced. For instance, high quality factor (Q factor) passive components are difficult to achieve in standard silicon-based IC processes.<p>In recent years, microelectromechanical systems (MEMS) devices have been receiving increasing attention as a possible replacement for various on-chip passive elements, offering potential improvement in performance while maintaining high levels of integration. Variable capacitors (varactor) are common elements used in various applications. One of the MEMS variable capacitors that has been recently developed is built using deep X-ray lithography (as part of the LIGA process). This type of capacitor exhibits high quality factor at microwave frequencies.<p>The complementary metal oxide semiconductor (CMOS) technology dominates the silicon IC process. CMOS becomes increasingly popular for RF applications due to its advantages in level of integration, cost and power consumption. This research demonstrates a CMOS voltage-controlled oscillator (VCO) design which is used to investigate methods, advantages and problems in integrating LIGA-MEMS devices to CMOS RF circuits, and to evaluate the performance of the LIGA-MEMS variable capacitor in comparison with the conventional on-chip CMOS varactor. The VCO was designed and fabricated using TSMC 0.18 micron CMOS technology. The core of the VCO, including transistors, resistors, and on-chip inductors was designed to connect to either an on-chip CMOS varactor or an off-chip LIGA-MEMS capacitor to oscillate between 2.6 GHz and 2.7 GHz. Oscillator phase noise analysis is used to compare the performance between the two capacitors. The fabricated VCO occupied an area of 1 mm^2.<p>This initial attempt at VCO fabrication did not produce a functional VCO, so the performance of the capacitors with the fabricated VCO could not be tested. However, the simulation results show that with this LIGA-MEMS capacitor, a 6.4 dB of phase noise improvement at 300 kHz offset from the carrier is possible in a CMOS-based VCO design.

The permeation of CMOS technology to radio frequencies and beyond has fuelled an urgent need for a diverse array of passive and active circuits that address the challenges of rapidly emerging wireless applications. While traditional analog based design approaches satisfy some applications, the stringent requirements of newly emerging applications cannot necessarily be addressed by existing design ideas and compel designers to pursue alternatives. One such alternative, an amalgamation of microwave and analog design techniques, is pursued in this work. A number of passive and active circuits have been designed using a combination of microwave and analog design techniques. For passives, the most crucial challenge to their CMOS implementation is identified as their large dimensions that are not compatible with CMOS technology. To address this issue, several design techniques – including multi-layered design and slow wave structures – are proposed and demonstrated through experimental results after being suitably tailored for CMOS technology. A number of novel passive structures - including a compact 10 GHz hairpin resonator, a broadband, low loss 25-35 GHz Lange coupler, a 25-35 GHz thin film microstrip (TFMS) ring hybrid, an array of 0.8 nH and 0.4 nH multi-layered high self resonant frequency (SRF) inductors are proposed, designed and experimentally verified. A number of active circuits are also designed and notable experimental results are presented. These include 3-10 GHz and DC-20 GHz distributed low noise amplifiers (LNA), a dual wideband Low noise amplifier and 15 GHz distributed voltage controlled oscillators (DVCO). Distributed amplifiers are identified as particularly effective in the development of wideband receiver front end sub-systems due to their gain flatness, excellent matching and high linearity. The most important challenge to the implementation of distributed amplifiers in CMOS RFICs is identified as the issue of their miniaturization. This problem is solved by using integrated multi-layered inductors instead of transmission lines to achieve over 90% size compression compared to earlier CMOS implementations. Finally, a dual wideband receiver front end sub-system is designed employing the miniaturized distributed amplifier with resonant loads and integrated with a double balanced Gilbert cell mixer to perform dual band operation. The receiver front end measured results show 15 dB conversion gain, and a 1-dB compression point of -4.1 dBm in the centre of band 1 (from 3.1 to 5.0 GHz) and -5.2 dBm in the centre of band 2 (from 5.8 to 8 GHz) with input return loss less than 10 dB throughout the two bands of operation.

Within the first decade of the 21st century, the aerospace community has seen many more opportunities to launch small spacecraft in the 10 to 100 kg mass class. Coupled with this has been consistent interest from the government in developing small-spacecraft platforms to expand civil and military mission possibilities. Small spacecraft have also given small organizations such as universities an increased access to space. Because small satellites are limited in size, power, and mass, new and often nontraditional capabilities must be explored and developed to make them viable and attractive when compared with larger and more proven spacecraft. Moreover, small organizations that wish to contribute technically are often limited by the small size of their teams and available resources, and need creative solutions for meeting mission requirements. A key need is in space-to-ground communications. Complex missions typically require large amounts of data transfer to the ground and in a timely fashion. Available options trade hardware cost, available ground stations or networks, available operating-frequency range, data-rate performance, and ease of use. A system for small spacecraft will be presented based upon Radio Frequency Integrated Circuits (RFIC) that minimizes development effort and maximizes interface control to meet typical small-spacecraft communications requirements. RFICs are low-cost components that feature pre-built radio hardware on a chip that can be expanded easily by developers with little or no radio experience. These devices are widespread in domestic applications for short-range connectivity. A preliminary design and prototype is presented that meets basic spaceflight requirements, offers data rates in the 55 to 85 kbps range, and has completed basic proof-of-concept testing. While there are higher-data-rate alternatives in existence, the solution presented here strikes a useful balance among data rate, parts cost, and ease of use for non experts, and gives the user operational control necessary to make air-to-ground communications time effective.

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Over the past decade there has been an explosion in the demand for wireless mobile personal communications systems (PCS), a trend that shows no signs of slowing down in the foreseeable future. This demand has created a greater need for low-cost, low-power, compact system solutions. As a result, "single-chip" implementations of wireless functions have received a significant amount of attention. A significant roadblock to complete integration of these functions is the requirement for high-Q resonators in RF filter and tank circuits. Current on-chip techniques being used to realize monolithic RF resonators based on planar inductors, capacitors and active circuits are accompanied by problems such as high loss, large chip area and high power consumption. An alternative to these on-chip solutions is the use of monolithically integrated electromechanical devices. This thesis describes the modeling, fabrication and characterization of nanoelectromechanical (NEM) single crystal silicon resonators. The potential advantages associated with these devices are high-Q, small die area and low power consumption. The development of such devices compatible with modern integrated circuit fabrication techniques offers the possibility for integration of high performance RF filters and resonators onto a single RFIC chip. The advantageous characteristics of these resonators could lead to mobile PCS devices with lower cost and increased battery life. The NEM resonator designs investigated in this work are fabricated using an electron-beam lithography based surface machining process in silicon-on-insulator technology. Various design, fabrication and testing issues are discussed. The feasibility of lateral capacitive actuation and detection in such structures is examined. / Master of Science

The rapid development of wireless applications has created a demand for low-cost, compact, low-power hardware solutions. This demand has driven efforts to realize fully integrated, "single-chip" systems. While substantial progress had been made in the integration of many RF and baseband processing elements through the development of new technologies and refinements of existing technologies, progress in the area of fully monolithic filters has been limited due to the losses (low Qs) associated with integrated passive elements in standard IC processes. The work in this thesis focuses on the development low-loss, Q-enhanced LC filters in GaAs E/D-SAGFET technology. This thesis presents a methodology for designing Q-enhanced LC resonators and low-loss, monolithic LC filters based on these resonators. The first phase of this work focused on the Q-enhancement of LC resonator structures using FET-based active negative resistance circuits. Three passive resonators were designed, fabricated, and measured to determine their loss and frequency response. Furthermore, six Q-enhanced resonators were designed, fabricated, and measured to compare the performance of various negative resistance circuit designs. In the second phase of this work, four of these Q-enhanced resonator designs were used to implement fully-integrated second-order Butterworth bandpass filters. Each filter was designed for a 60 MHz, -3 dB bandwidth centered at 1.88 GHz, corresponding to the North American PCS transmit band. The best filter design achieves 0 dB of passband insertion loss while consuming 16 mA of current from a 3 V source (48 mW). Passband gain (up to 15 dB) can be achieved with increased bias current before instability is encountered. The filter provides more than 30 dB of rejection at 1.7 and 2 GHz and more than 70 dB of rejection below 1.5 GHz. In the filter passband, the noise figure is 12 dB and the output 1 dB compression point is -18 dBm. These Q-enhanced LC filters have potential application as image-reject filters in GaAs integrated transceiver designs. / Master of Science

The explosive growth in wireless communications has led to an increased demand for wireless products that are cheaper, smaller, and lower power. Recently there has been an increased interest in using CMOS, a traditional digital and low frequency analog IC technology, to implement RF components such as mixers, voltage controlled oscillators (VCOs), and low noise amplifiers (LNAs). Future mass-market RF links, such as BlueTooth, will require the potentially low-cost single-chip solutions that CMOS can provide. In order for such single-chip solutions to be realized, RF circuits must be designed that can operate in the presence of noisy digital circuitry. The voltage controlled oscillator (VCO), an important building block for RF systems, is particularly sensitive when exposed to an electrically noisy environment. In addition, CMOS implementations of VCOs have been hampered by the lack of high-quality integrated inductors. This thesis focuses on the design of a fully integrated 2.5 GHz LC CMOS VCO. The circuit is intended as a vehicle for future mixed RF/digital noise characterization. The circuit was implemented in a 0.35 μm single poly, 4 metal, 3.3 V, CMOS process available through MOSIS. The oscillator uses a complementary negative transconductance topology. This oscillator circuit is analyzed as a negative-resistance oscillator. Monolithic inductors are designed using full-wave electromagnetic field solver software. The design of an "inversion-mode" MOS (I-MOS) tuning varactor is presented, along with a discussion of the effects of varactor nonlinearity on VCO performance. I-MOS varactors are shown to have substantially improved tuning range (and tuning curve linearity) over conventional MOS varactors. Practical issues pertaining to CMOS VCO circuit design, layout, and testing are also discussed. The characterization of the VCO and the integrated passives is presented. The VCO achieves a best-case phase noise of -106.7 dBc/Hz at 100 kHz offset from a center frequency of 2.73 GHz. The tuning range is 425 MHz (17%). The circuit consumes 9 mA from a 3.3 V supply. This represents excellent performance for CMOS oscillator designs reported at this frequency. Finally, several recommendations for improvements in oscillator performance and characterization are discussed. / Master of Science

Wireless communication serves as the foundation for a wide range of services that have become an integral part of human life in this day and age. Driven by the desire to have a single piece of hardware that can provide multiple wireless services, attention has been directed to SDRs due to their programmable nature and the flexibility they can offer in operating over multiple standards. In addition, they can provide effective solutions to current challenges in wireless communication, such as spectrum overcrowding and inter-standard operability, as well as future challenges to come due to their upgradeability. Although SDRs have been around in the research community for over a decade, they have not reached the point of transitioning to the mass consumer market, size being one of the major obstacles. Numerous SDR hardware platforms have been developed demonstrating successful functionality, yet to this day most of them remain trapped in desktop/benchtop form factors which are not suited for mobility. A main factor contributing to the size of SDR units is the RF front end. Using current technology, wide-band operation of SDR RF front-ends is achieved by aggregating multiple dedicated components, each covering a portion of the frequency range. Recent technology advances have enabled the integration of wide frequency functionality inside a single integrated package. One example is a prototype RFIC transceiver chip from Motorola Research Labs which contains a complete direct conversion RF transceiver in a single chip, with a frequency coverage range of 100MHz-2.4GHz. RFIC5, the latest version of the chip, has additionally integrated high speed ADC and DAC units, leading to a significant reduction in the component count and the overall size of the SDR hardware. This thesis describes the implementation of a highly compact, SDR PC plug-in card, known as PicoRF. PicoRF is based on the Motorola's RFIC chip for the RF front-end functionality, while the combined computational power of a V5 FPGA and a PC host is used for waveform signal processing. An overlay gird consisting of an interconnection of PR slots is reserved on the FPGA to host the components of a signal processing pipeline which can be modified during run-time. Through a high speed PCIe connection, partial bitstreams can be downloaded from the host PC to the FPGA at a very high speed making it possible for the radio to modify its function in very short time intervals and greatly reducing the service interruption time. Control software running on the PC host manages the overall system operation including the RFIC which is controlled through a custom developed API. The combination of the laptop host and the plug-in card form a small form factor, mobile SDR node that is one step towards satisfying both the performance and ergonomics demand of the consumer market. / Master of Science

The recent trend in the RF and microwave industry has been a move towards increasing the number of components realized on one radio frequency integrated circuit (RFIC) (or microwave integrated circuit (MIC)). This trend has resulted in complex RFICs which often require reactive as well as other circuit components to be supplied in the form of an external circuit. Because the manufacturer's suggested circuit is often developed with a specific application in mind, the same circuit may not satisfy the demands of another application. Provided the necessary functionality and connections are possible, the external circuit may be altered such that the requirements of the other application can be met, thus extending the flexibility of the RFIC. The work presented here is focused on investigating modifications to RF Microdevices' suggested external circuit for the RF29X5 family of low cost, half duplex, FM/AM/ASK/FSK RFIC transceivers originally intended for operation in the 433, 868, or 902-928 MHz industrial, scientific, and measurement (ISM) bands. Examinations of the operating principles of the transceiver components were performed which facilitated the identification of suitable modifications. Among the modifications identified were implementation of a phase locked detector, various methods for extending the FSK data rate limitations of the transmitter, improving the phase noise of the VCO, and the implementation of a fractional-N synthesizer using the RF2905 internal phase-locked loop (PLL) components and external inexpensive logic circuits. In addition to these modifications to the external circuit, the investigation of the oscillators of the RF2905 resulted in a potentially improved implementation of the VCO by modifying the internal active circuitry as well. / Master of Engineering