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Spektrální analyzátor do 500 MHz / Spectrum Analyzer up to 500 MHzČada, David January 2015 (has links)
This project deals with design and realization of the spectrum analyser using double superheterodyne topology with frequency range up to 500MHz. This work solves hardware blocks like phase lock loops, intermediate frequency filters, saw filter, crystal filter, logarithmic detector. Content of work is also design description and tuning of spectrum analyzer parts.
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PC- Based S-Band Down Converter / FM Telemetry ReceiversGirija, Satyanarayana, Girija, J. 10 1900 (has links)
International Telemetering Conference Proceedings / October 28-31, 1996 / Town and Country Hotel and Convention Center, San Diego, California / In this paper design and development of a PC- Based S- Band Down Converter/ FM Telemetry Receiver are discussed. With the advent of Direct Digital Synthesis (DDS) & Phase Locked Loop (PLL) technology, availability of GaAs & Silicon MMICs, Coaxial Resonator Oscillator (CRO), SAW Oscillator, SAW Filters and Ceramic Filters, realisation of single card PC- Based Down Converter and Telemetry Receiver has become a reality. With the availability of Direct Digital Synthesis and Phase Locked Loop devices having microprocessor bus compatibility, opens up many application in Telemetry and Telecommunications. In this paper design of local oscillator based on hybrid DDS & PLL technique, Coaxial Resonator Oscillator and Front-end are discussed in detail.
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Analyzátor signálu v televizních kabelových rozvodech / TV Distribution Network Signal AnalyzerMatyáš, Pavel January 2011 (has links)
Aim of this project is development of the analyser for cable distributed television signals. At the beginning is a block diagram of the suggested analyser with digitally controled wideband tuner, logarithmic detector, microcontroller and a graphical display module. For each block there is a theoretical analysis, features description and description of the electronic components that were used. In the next part of this project is introduced the design of circuit schematic and printed circuit board of prototyping kit, that was used for experiments and testing of its features and parametres. Last part of this thesis focuses on finishing of a prototyping kit, development of firmware and experimental verification of the prototype's parameters.
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New Generation 4-Channel GNSS Receiver : Design, Production, and TestingAntoja Lleonart, Guillem January 2018 (has links)
Due to the current research needs and the lack of commercial multi-channel, multi-constellation GNSS receivers, a two-board solution has been developed so it can be mated with and take advantage of the processing power of the FPGA board branded as MicroZed. In order to achieve the proposed goals, an initial phase for assessing and updating the older design, building, and testing of SiGe modules (including both the electronics and casings) has been carried out. The results included demonstrate performances at logging GPS-L1 data with similar C/N0 and AGC values as the previous versions of the modules and offering navigation solutions with accuracies of a few meters. Secondly, a first iteration and design proposal for the new generation receiver has been proposed for GPS and GLONASS L1 and L2, which has been manufactured and tested. Partial tests have been performed due to the flaws of the current revision of the MicroZed Board in regards to its communication peripherals, and the results have validated the receiver’s design provided certain modifications are considered for future iterations. Furthermore, voltage and frequency tests have provided results with an error of less than 7%, and signal tests have provided C/N0 values similar to those of the SiGe modules of around 47[dB-Hz] which will be a useful baseline for future iterations. Finally, a design proposal for an Interface Board used between the older NT1065_PMOD Board and other FPGA boards carrying the standardized FMC connectors has been added to the report and negotiations with manufacturers have been engaged.
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