This thesis explores means of mitigating the effects of silicon variation on SRAM by means of circuit techniques. This thesis also explores novel read and write techniques for MRAM that support a non-destructive read operation and power-saving write operations in the face of device and silicon variation. First, this thesis proposes the use of a cross-coupled bit line BL biasing scheme that retains an SRAM's fast access speed while reducing the read-access failures in the presence of Vt variation, without excessively increasing the SRAM cell size. It is shown, by extensive Monte-Carlo simulations using 22-nm predictive CMOS models, that the proposed scheme reduces the cell area by 6.5% compared to the conventional BL biasing schemes also analyzed. Second, this thesis proposes a 10T SRAM cell that supports lower voltage operation, achieves lower static power dissipation, and is similar in area to the 6T SRAM cell when the 3-sigma variation of Vt exceeds 40% of nominal Vt. The 10T cell achieves improved write functionality, in comparison to the 6T cell, by preemptively turning off the cell's power supply to the side of the cell that is being pulled low, while not disturbing any unselected cells. Write access time is not affected, as the positive-feedback required to quickly regenerate CMOS voltage levels remains intact. Finally, this thesis proposes a negative-resistance read scheme and write scheme for spin-torque-transfer (STT) MRAM. A negative resistance shunting an STT-MRAM cell guarantees a non-destructive read operation, and saves power during write operations compared with a conventional scheme. Measurements confirm an 7ns non-destructive read access time without the use of a typical sense amplifier and an average write power savings of 10.5% for a 16Kb STT-MRAM fabricated in 0.13um CMOS using a CoFeB/MgO/CoFeB MTJ.

During development and testing of the pacemaker and defibrillator device functionality, engineers in the cardiac rhythm management industry use a patient simulator to ensure device functionality properly before device is tested with an animal or a human. The patient simulator is also used in the formal device product testing. In St. Jude Medical, a patient simulator called Simulation Test Tool (STT) has been developed and used by engineers in the company. While the Heart Simulator (HS) feature based on physiological heart model in the STT has been served as a main cardiac rhythm simulation feature, there has been an increasing need of a new feature in the STT for engineers to create heart rhythm scenarios more easily and effectively. This thesis covers the design and implementation of the new STT feature, called Event Stream, which allows users to create heart rhythm scenarios using simple text string based syntax for testing device functionality.

<p>Modern computing platforms, from servers to mobile devices, demand ever-increasing amounts of memory to keep up with the growing amounts of data they process, and to bridge the widening processor-memory gap. A large and growing fraction of chip area and energy is expended in memories, which face challenges with technology scaling due to increased leakage, process variations, and unreliability. On the other hand, data intensive workloads such as machine learning and data analytics pose increasing demands on memory systems. Consequently, improving the energy-efficiency and performance of memory systems is an important challenge for computing system designers.</p> <p>Spintronic memories, which offer several desirable characteristics - near-zero leakage, high density, non-volatility and high endurance - are of great interest for designing future memory systems. However, these memories are not drop-in replacements for current memory technologies, viz. Static Random Access Memory (SRAM) and Dynamic Random Access Memory (DRAM). They pose unique challenges such as variable access times, and require higher write latency and write energy. This dissertation explores new approaches to improving the energy efficiency of spintronic memory systems.</p> <p>The dissertation first explores the design of approximate memories, in which the need to store and access data precisely is foregone in return for improvements in energy efficiency. This is of particular interest, since many emerging workloads exhibit an inherent ability to tolerate approximations to their underlying computations and data while still producing outputs of acceptable quality. The dissertation proposes that approximate spintronic memories can be realized either by reducing the amount of data that is written to/read from them, or by reducing the energy consumed per access. To reduce memory traffic, the dissertation proposes approximate memory compression, wherein a quality-aware memory controller transparently compresses/decompresses data written to or read from memory. For broader applicability, the quality-aware memory controller can be programmed to specify memory regions that can tolerate approximations, and conforms to a specified error constraint for each such region. To reduce the per-access energy, various mechanisms are identified at the circuit and architecture levels that yield substantial energy benefits at the cost of small probabilities of read, write or retention failures. Based on these mechanisms, a quality-configurable Spin Transfer Torque Magnetic RAM (STT-MRAM) array is designed in which read/write operations can be performed at varying levels of accuracy and energy at runtime, depending on the needs of applications. To illustrate the utility of the proposed quality-configurable memory array, it is evaluated as an L2 cache in the context of a general-purpose processor, and as a scratchpad memory for a domain-specific vector processor.</p> <p>The dissertation also explores the design of caches with Domain Wall Memory (DWM), a more advanced spintronic memory technology that offers unparalleled density arising from a unique tape-like structure. However, this structure also leads to serialized access to the bits in each bit-cell, resulting in increased access latency, thereby degrading overall performance. To mitigate the performance overheads, the dissertation proposes a reconfigurable DWM-based cache architecture that modulates the active bits per tape with minimal overheads depending on the application's memory access characteristics. The proposed cache is evaluated in a general purpose processor and improvements in performance are demonstrated over both CMOS and previously proposed spintronic caches.</p> <p>In summary, the dissertation suggests directions to improve the energy efficiency of spintronic memories and re-affirms their potential for the design of future memory systems.</p>

Computer memories now play a key role in our everyday life given the increase in the number of connected smart devices and wearables. Recently post-CMOS memory technologies are gaining significant research attention along with the regular ones. Spin Transfer Torque Magnetoresistive RAM (STT-MRAM) is one such post-CMOS memory technology with a rapidly growing commercial interest and potential across diverse application platforms. Research has shown the ability of STT-MRAM to replace different levels of memory hierarchy as well. In brief, STT-MRAM possesses all the favorable properties of a universal memory technology. In this dissertation we have explored the roles of this emerging memory technology beyond traditional storage. The purpose is to enhance the overall performance of the application platform that STT-MRAM is a part of. The roles that we explored are computation and security. We have discussed how the intrinsic properties of STT-MRAM can be used for computation and authentication. The two properties that we are interested in are the dipolar coupling between the magnetic memory cells and the variations in the geometries of the memory cell. Our contributions here are a 22nm CMOS integrated STT-MRAM based logic-in-memory architecture and a geometric variation based STT-MRAM signature generation. In addition we have explored the device physics and the dynamics of STT-MRAM cells to propose a STT based clocking mechanism that is friendlier with the logic-in-memory setup. By investigating the logic layouts and propagation style in the architecture, we have also proposed different techniques that can improve the logic density and performance of the architecture.

This thesis presents the design and implementation of a high-speed read-access STT MRAM. The proposed design includes a 2T1MTJ cell topology, along with two different read schemes: current-based and voltage-based. Compared to the conventional read scheme with 1T1MTJ cells, the proposed design is capable of reducing the loading on the read circuit to minimize the read access time. A complete STT MRAM test chip including the proposed and the conventional schemes was fabricated in 90nm CMOS technology. The 16kb test chip's measurement results confirm a read access time of 6ns and a write access time of 10ns. The read time is 25% faster than other works of similar array size published thus far, while the write time is able to match the fastest result.

This thesis presents the design and implementation of a high-speed read-access STT MRAM. The proposed design includes a 2T1MTJ cell topology, along with two different read schemes: current-based and voltage-based. Compared to the conventional read scheme with 1T1MTJ cells, the proposed design is capable of reducing the loading on the read circuit to minimize the read access time. A complete STT MRAM test chip including the proposed and the conventional schemes was fabricated in 90nm CMOS technology. The 16kb test chip's measurement results confirm a read access time of 6ns and a write access time of 10ns. The read time is 25% faster than other works of similar array size published thus far, while the write time is able to match the fastest result.

Dissertação de mestrado apresentada ao Programa de Pós-Graduação em Ciência e Engenharia de Materiais – PPGCEM da Universidade do Extremo Sul Catarinense – UNESC, como requisito à obtenção do título de Mestre em Ciência e Engenharia de Materiais. / A ligação soldada é de suma importância em estruturas de aço, necessitam de projetos estruturais e ajustes de processamento, para obter resistência mecânica e durabilidade. O processo de soldagem vem utilizando recursos eletrônicos para o controle das curvas de corrente e tensão, fato que faz surgir novos parâmetros de controle. Estes parâmetros possuem ranges limitados pela espessura das chapas a serem unidas, tipologia do aço utilizado e transferência metálica adotada. Assim, foram escolhidos para este estudo os aços ASTM A572 Gr50 e ASTM A36 com espessuras diferentes, pois possuem utilização expressiva em obras civis e industriais. O intuito deste estudo é otimizar a utilização do processo de soldagem GMAW (Gas Metal Arc Welding) MAG (Metal Active Gas) com curva controlada e transferência metálica por STT (Surface Tension Transfer). Para isto, foi proposto um planejamento experimental fatorial 2³ completo, com ponto central em réplica, avaliando a velocidade de alimentação (Va), o foco da coluna do arco elétrico (FC) e a amplitude entre a corrente de pico e a corrente de base (APB). Foram realizados testes experimentais, a fim de mensurar a energia de soldagem, a eficiência de deposição, a geometria do cordão de solda, a resistência mecânica, bem como analisar a microestrutura formada na região da solda, o potencial de corrosão e o perfil de dureza Vickers passando pelos metais de base (MB), zona termicamente afetada (ZTA), zona fundida (ZF) e metal de solda (MS). Todos os testes foram realizados em corpos de prova cruciformes, para evitar a interferência na interpretação dos resultados, por diferenças na transferência de calor. Os resultados obtidos apontam um valor ótimo de energia de soldagem, que promove baixa alteração microestrutural, com poucas alterações no perfil de microdureza e uma geometria de filete de solda sem defeitos e com previsão, através de modelo matemático, da área resistente.

Silicon manufacturers are experiencing shortages ofsemiconductors and the demand for cost-effective, power-efficientembedded memory solutions is increasing. For these issues, a newemerging memory technology called embedded magnetoresistiverandom access memory (eMRAM) and the development of thewrite mechanism called spin-transfer torque (STT-MRAM) havebeen proposed. The eMRAM has non-volatility, reduced totalenergy consumption, fast read/write operation and has a smallmacro size compared to the semiconductor-based memory typessuch as SRAM, Flash and EEPROM. The purpose of thisstudy is to investigate eMRAM and how it can be used in amicrocontroller to replace all three existing, semiconductor-basedmemory types. The focus will be on how solution can be createdwith smaller memory chip area, improved energy efficiency andfaster read/write operations. A literature review was established,to determine if eMRAM does indeed result in better memorycharacteristics and memory performance. As well as to determinethe requirements that is needed for a flash-type and SRAMtypeapplication. The study shows that eMRAM have a potentialto create many solutions for a microcontroller, such as it hasthe potential to simplify its memory architecture by providing aunified memory solution for its code and data storage as well asfor its working memory. / Halvedartillverkarna står inför svårigheter på grund av bristen på halvledare och att efterfrågan på kostnadseffektiva, strömsnåla inbyggda minneslösningar ökas. För att lösa dessa problem har en ny framväxande minnesteknik som kallas för inbyggd magnetoresistivt slumpmässigt åtkomstminne (eMRAM) och utvecklingen av skrivmekanismen som kallas för spinn-överföringsmoment (STT-MRAM) föreslagits. eMRAM har icke-flyktighet, en låg total energiförbrukning, snabba läsoch skrivfunktioner och har en liten makrostorlek jämfört med de halvledarbaserade minnestyperna såsom SRAM, Flash och EEPROM. Syftet med denna studie är att undersöka eMRAM och hur det kan användas i en mikrokontroller för att ersätta alla tre befintliga halvledarbaserade minnestyper. Fokuset kommer att ligga på hur en lösning kan skapas med mindre minneschipyta, bättre energieffektivitet och snabbare läsoch skrivoperationer. En litteraturgenomgång gjordes för att fastställa om eMRAM verkligen resulterar i bättre minnesegenskaper samt minnesprestanda och att fastställa de krav som krävs för en tillämpning av en flash-typ och en SRAM-typ applikation. Undersökningen visar att eMRAM har en potential att skapa många lösningar för en mikrokontroller, t.ex. har den som potential att förenkla dess minnesarkitektur genom att bidra med en enhetlig minneslösning för kod- och datalagring samt för arbetsminnet. / Kandidatexjobb i elektroteknik 2022, KTH, Stockholm

Afin de concurrencer les mémoires à accès aléatoire de type DRAM actuellement sur le marché, les mémoires magnétiques ont depuis quelques années fait l'objet de nombreuses études afin de les rendre aussi performantes que possible. Dans ce contexte, les jonctions tunnel magnétiques à double barrière pourraient présenter des avantages significatifs en termes de vitesse de lecture et de consommation électrique. Nous avons en effet fait la démonstration que les structures à double barrière permettent, pour une configuration antiparallèle des aimantations des polariseurs, d'accroître les effets de transfert de spin assurant ainsi des courants d'écriture faibles. Dans la configuration parallèle des polariseurs, le phénomène est inversé et le couple par transfert de spin résultant est considérablement réduit. Cela permettrait de lire l'information plus rapidement en utilisant des tensions du même ordre de grandeurs que celles utilisées pour l'écriture. Nous avons par ailleurs proposé une méthode d'analyse permettant de caractériser les deux barrières tunnel par des mesures électriques en pleine plaque, ce qui facilite le développement des matériaux et atteste des propriétés électriques attendues avant nanofabrication. / Since a few years, magnetic memories have been extensively studied in order to compete with already existing Random Access Memories such as DRAM. In this context, double barrier magnetic tunnel junctions may have significant assets in terms of reading speed and electrical consumption. In fact, we demonstrated that spin transfer torque is enhanced when polarizers magnetizations are antiparallel, thus yielding a decrease of the writing current. On the contrary, when polarizers are parallel, spin transfer torque is drastically shrinked, thus allowing fast reading of the storage layer state at a voltage as large as the writing voltage. Moreover, we proposed an analysis method to characterize both tunnel barriers by full-sheet electrical measurements, leading to considerable gain of time in material developpement.

Modern computing workloads such as machine learning and data analytics perform simple computations on large amounts of data. Traditional von Neumann computing systems, which consist of separate processor and memory subsystems, are inefficient in realizing modern computing workloads due to frequent data transfers between these subsystems that incur significant time and energy costs. In-memory computing embeds computational capabilities within the memory subsystem to alleviate the fundamental processor-memory bottleneck, thereby achieving substantial system-level performance and energy benefits. In this dissertation, we explore a new generation of in-memory computing architectures that are enabled by emerging memory technologies and new CMOS-based memory cells. The proposed designs realize Boolean and non-Boolean computations natively within memory arrays.<br><div><br></div><div>For Boolean computing, we leverage the unique characteristics of emerging memories that allow multiple word lines within an array to be simultaneously enabled, opening up the possibility of directly sensing functions of the values stored in multiple rows using single access. We propose Spin-Transfer Torque Compute-in-Memory (STT-CiM), a design for in-memory computing with modifications to peripheral circuits that leverage this principle to perform logic, arithmetic, and complex vector operations. We address the challenge of reliable in-memory computing under process variations utilizing error detecting and correcting codes to control errors during CiM operations. We demonstrate how STT-CiM can be integrated within a general-purpose computing system and propose architectural enhancements to processor instruction sets and on-chip buses for in-memory computing. <br></div><div><br></div><div>For non-Boolean computing, we explore crossbar arrays of resistive memory elements, which are known to compactly and efficiently realize a key primitive operation involved in machine learning algorithms, i.e., vector-matrix multiplication. We highlight a key challenge involved in this approach - the actual function computed by a resistive crossbar can deviate substantially from the desired vector-matrix multiplication operation due to a range of device and circuit level non-idealities. It is essential to evaluate the impact of the errors introduced by these non-idealities at the application level. There has been no study of the impact of non-idealities on the accuracy of large-scale workloads (e.g., Deep Neural Networks [DNNs] with millions of neurons and billions of synaptic connections), in part because existing device and circuit models are too slow to use in application-level evaluation. We propose a Fast Crossbar Model (FCM) to accurately capture the errors arising due to crossbar non-idealities while being four-to-five orders of magnitude faster than circuit simulation. We also develop RxNN, a software framework to evaluate DNN inference on resistive crossbar systems. Using RxNN, we evaluate a suite of large-scale DNNs developed for the ImageNet Challenge (ILSVRC). Our evaluations reveal that the errors due to resistive crossbar non-idealities can degrade the overall accuracy of DNNs considerably, motivating the need for compensation techniques. Subsequently, we propose CxDNN, a hardware-software methodology that enables the realization of large-scale DNNs on crossbar systems with minimal degradation in accuracy by compensating for errors due to non-idealities. CxDNN comprises of (i) an optimized mapping technique to convert floating-point weights and activations to crossbar conductances and input voltages, (ii) a fast re-training method to recover accuracy loss due to this conversion, and (iii) low-overhead compensation hardware to mitigate dynamic and hardware-instance-specific errors. Unlike previous efforts that are limited to small networks and require the training and deployment of hardware-instance-specific models, CxDNN presents a scalable compensation methodology that can address large DNNs (e.g., ResNet-50 on ImageNet), and enables a common model to be trained and deployed on many devices. <br></div><div><br></div><div>For non-Boolean computing, we also propose TiM-DNN, a programmable hardware accelerator that is specifically designed to execute ternary DNNs. TiM-DNN supports various ternary representations including unweighted (-1,0,1), symmetric weighted (-a,0,a), and asymmetric weighted (-a,0,b) ternary systems. TiM-DNN is an in-memory accelerator designed using TiM tiles --- specialized memory arrays that perform massively parallel signed vector-matrix multiplications on ternary values per access. TiM tiles are in turn composed of Ternary Processing Cells (TPCs), new CMOS-based memory cells that function as both ternary storage units and signed scalar multiplication units. We evaluate an implementation of TiM-DNN in 32nm technology using an architectural simulator calibrated with SPICE simulation and RTL synthesis. TiM-DNN achieves a peak performance of 114 TOPs/s, consumes 0.9W power, and occupies 1.96mm2 chip area, representing a 300X improvement in TOPS/W compared to a state-of-the-art NVIDIA Tesla V100 GPU. In comparison to popular quantized DNN accelerators, TiM-DNN achieves 55.2X-240X and 160X-291X improvement in TOPS/W and TOPS/mm2, respectively.<br></div><div><br></div><div>In summary, the dissertation proposes new in-memory computing architectures as well as addresses the need for scalable modeling frameworks and compensation techniques for resistive crossbar based in-memory computing fabrics. Our evaluations show that in-memory computing architectures are promising for realizing modern machine learning and data analytics workloads, and can attain orders-of-magnitude improvement in system-level energy and performance over traditional von Neumann computing systems. <br></div>