Since semiconductor fabrication processes require numerous steps, cost and yield are critical concerns. In-situ monitoring is therefore vital for process control. However, this goal is currently restricted by the shortage of available sensors capable of performing in this manner. The goal of this research therefore, was to investigate the use of acoustic signals for monitoring and control of semiconductor fabrication equipment and processes. Currently, most methods for process monitoring (such as optical emission or interferometric techniques) rely on "looking" at a process to monitor its status. What was investigated here involved "listening" to the process. Using acoustic methods for process monitoring enhances the amount and sensitivity of data collection to facilitate process diagnostics and control. A silicon acoustic sensor was designed, fabricated, and implemented as a process monitor. Silicon acoustic sensors are favorable because of their utilization of integrated circuit and micromachining processing techniques; thus, enabling miniature devices with precise dimensions, batch fabrication of sensors, good reproducibility, and low costs. The fabricated sensor was used for in-situ monitoring of nickel-iron electrochemical deposition processes. During this process, changes occur in its plating bath as the alloy is being deposited. It is known that changes in the process medium affect the acoustic response. Thus, the sensor was implemented in an electroplating set-up and its response was observed during depositions. By mapping the sensor response received to the film thickness measured at certain times, a predictive model of the plated alloy thickness was derived as a function of sensor output and plating time. Such a model can lead to real-time monitoring of nickel-iron thickness.

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Reconfigurable computing architectures combine the flexibility of software with the performance of custom hardware. Such architectures are of particular interest at the nanoscale level. We argue that a bottom-up self-assembled fabric of nodes will be easier and cheaper to manufacture, however, one has to make compromises with regards to the device regularity, homogeneity, and reliability. The goal of this thesis is to evaluate the performance and cost of a self-configurable computing architecture composed of simple reconfigurable nodes for unstructured and unknown fabrics. We built a software and hardware framework for this purpose. The framework enables creating an irregular network of compute nodes where each node can be configured as a simple 2-input, 4-bit logic gate. The compute nodes are organized hierarchically by sending a packet through a top anchor node that recruits compute nodes with a chemically-inspired algorithm. The nodes are then self-configured by means of a gate-level netlist describing any digital logic circuit. A topology-agnostic optimization algorithm inspired by simulated annealing is then initiated to self-optimize the circuit for latency. Latency comparisons between non-optimized, brute-force optimized and our optimization algorithm are made. We further implement the architecture in VHDL and evaluate hardware cost, area, and energy consumption. The simple on-chip topology-agnostic optimization algorithm we propose results in a significant (up to 50\%) performance improvement compared to the non-optimized circuits. Our findings are of particular interest for emerging nano and molecular-scale circuits.

In this dissertation, we implement efficient lock-based synchronization by a novel, high performance, simple and scalable hardware technique and associated software for a target shared-memory multiprocessor System-on-a-Chip (SoC). The custom hardware part of our solution is provided in the form of an intellectual property (IP) hardware unit which we call the SoC Lock Cache (SoCLC). SoCLC provides effective lock hand-off by reducing on-chip memory traffic and improving performance in terms of lock latency, lock delay and bandwidth consumption. The proposed solution is independent from the memory hierarchy, cache protocol and the processor architectures used in the SoC, which enables easily applicable implementations of the SoCLC (e.g., as a reconfigurable or partially/fully custom logic), and which distinguishes SoCLC from previous approaches. Furthermore, the SoCLC mechanism has been extended to support priority inheritance with an immediate priority ceiling protocol (IPCP) implemented in hardware, which enhances the hard real-time performance of the system. Our experimental results in a four-processor SoC indicate that SoCLC can achieve up to 37% overall speedup over spin-lock and up to 48% overall speedup over MCS for a microbenchmark with false sharing. The priority inheritance implemented as part of the SoCLC hardware, on the other hand, achieves 1.43X speedup in overall execution time of a robot application when compared to the priority inheritance implementation under the Atalanta real-time operating system. Furthermore, it has been shown that with the IPCP mechanism integrated into the SoCLC, all of the tasks of the robot application could meet their deadlines (e.g., a high priority task with 250us worst case response time could complete its execution in 93us with SoCLC, however the same task missed its deadline by completing its execution in 283us without SoCLC). Therefore, with IPCP support, our solution can provide better real-time guarantees for real-time systems. To automate SoCLC design, we have also developed an SoCLC-generator tool, PARLAK, that generates user specified configurations of a custom SoCLC. We used PARLAK to generate SoCLCs from a version for two processors with 32 lock variables occupying 2,520 gates up to a version for fourteen processors with 256 lock variables occupying 78,240 gates.

Since metal-oxide-semiconductor (MOS) devices have been adopted into integrated circuits, the endless demands for higher performance and lower power consumption have been a primary challenge and a technology-driver in the semiconductor electronics. The invention of complementary MOS (CMOS) technology in the 1980s, and the introduction of voltage and physical dimension scaling in the 1990s would be good examples to keep up with the everlasting demands. In the 2000s, technology continuously evolves and seeks for more power efficiency ways such as high-k dielectrics, metal gate electrodes, strained substrates, and high mobility channel materials. As a gate dielectric, silicon dioxide (SiO₂), most widely used in CMOS integrated circuits, has many prominent advantages, including a high quality interface (e.g. Dit ~ low 1010 cm-2eV-1), a good thermal stability in contact with silicon (Si), a large energy bandgap and the large energy band offsets in reference to Si, and a high quality dielectric itself. As the thickness of SiO₂ keeps shrinking, however, SiO₂ is facing its physical limitations from the viewpoint of gate dielectric leakage currents and reliability requirements. High-k dielectric materials have attracted extensive attention in the last decade due to their great potential for maintaining further down-scaling in equivalent oxide thickness (EOT) and a low dielectric leakage current. HfO₂ has been considered as one of the most promising candidates because of a high dielectric constant (k ~ 20-25), a large energy band gap (~ 6 eV) and the large band offsets (> 1.5 eV), and a good thermal stability. To enhance carrier mobility, strained substrates and high mobility channel materials have attracted a great deal of attention, thus III-V compound semiconductor substrates have emerged as one of possible candidates, in spite of several technical barriers, being believed as barriers so far. The absence of high quality and thermodynamically stable native oxide, like SiO₂ on Si, has been one such hurdle to implement MOS systems on III-V substrates. However, recently, there have been a number of remarkable improvements on MOS applications on them, inspiring more vigorous research activities. In this research, HfO2-based MOS capacitors and metal-oxidesemiconductor field effect transistors (MOSFETs) with a thin germanium (Ge) interfacial passivation layer (IPL) on III-V compound substrates were investigated. It was found that a thin Ge IPL could effectively passivate the surface of III-V substrate, consequently providing a high quality interface and an excellent gate oxide scalability. N-channel MOSFETs on GaAs, InGaAs, and InP substrates were successfully demonstrated and a minimum EOT of ~ 9 Å from MOS capacitors was achieved. This research has begun with GaAs substrate, and then expanded to InGaAs, InP, InAs, and InSb substrates, which eventually helped to understand the role of a Ge IPL and to guide future research direction. Overall, MOS devices on III-V substrates with an HfO₂ gate dielectric and a Ge IPL have demonstrated feasibility and potential for further investigations. / text

This dissertation is composed of three major parts, each studying a problem related to semiconductor manufacturing. The first part of the dissertation proposes a high-level scheduling model that serves as an intermediate stage between planning and detailed scheduling in the usual planning hierarchy. The high-level scheduling model explicitly controls the WIP over time in the system and provides a more specific guide to detailed scheduling. WIP control is used to balance the WIP (Work In Process) level and to keep the bottleneck station busy to maintain a high throughput rate. A mini-fab simulation model is used to evaluate the benefits of different approaches to implementing such a high-level scheduling model, and to compare different WIP control policies. Extensive numerical studies show that the proposed approaches can achieve much shorter cycle times than the traditional planning-scheduling approach, with only a small increase in inventory and backorder costs. With increasing worldwide competition, high technology product manufacturing companies have to pay great attention to lower their production costs and guarantee high quality at the same time. Advanced process control (APC) is widely used in semiconductor manufacturing to adjust machine parameters so as to achieve satisfactory product quality. The interaction between scheduling and APC motivates the second part of this dissertation. First, a single-machine makespan problem with APC constraints is proved to be NPcomplete. For some special cases, an optimal solution is obtained analytically. In more general cases, the structure of optimal solutions is explored. An efficient heuristic algorithm based on these structural results is proposed and compared to an integer programming approach. Another important issue in manufacturing system is maintenance, which affects cycle time and yield management. Although there is extensive literature regarding maintenance policies, the analysis in most papers is restricted to conventional preventive maintenance (PM) policies, i.e., calendar-based or jobbased PM policies. With the rapid development of new technology, predictive maintenance has become more feasible, and has attracted more and more attention from semiconductor manufacturing companies in recent years. Thus, the third problem considered in this dissertation is predictive maintenance in an M/G/1 queueing environment. One-recipe and two-recipe problems are studied through semi-Markov decision processes (SMDP), and structural properties are obtained. Discounted SMDP problems are solved by linear programming and expected machine availabilities are calculated to evaluate different PM policies. The optimal policy can maintain a high machine availability with low long-run cost. The structures of the optimal PM policies show that it is necessary to consider multiple recipes explicitly in predictive maintenance models. / text

In this doctoral dissertation, the author presents the theoretical foundation, the analysis and design of analog and RF circuits, the chip level implementation, and the experimental validation pertaining to a new radio frequency integrated circuit (RFIC) power amplifier (PA) architecture that is intended for wireless portable transceivers. / A method called Gated Envelope Feedback is proposed to allow the automatic hardware reconfiguration of a stand-alone RFIC PA in multiple states for power efficiency improvement purposes. The method uses self-operating and fully integrated circuitry comprising RF power detection, switching and sequential logic, and RF envelope feedback in conjunction with a hardware gating function for triggering and activating current reduction mechanisms as a function of the transmitted RF power level. Because of the critical role that RFIC PA components occupy in modern wireless transceivers, and given the major impact that these components have on the overall RF performances and energy consumption in wireless transceivers, very significant benefits stem from the underlying innovations. / The method has been validated through the successful design of a 1.88GHz COMA RFIC PA with automatic hardware reconfiguration capability, using an industry renowned state-of-the-art GaAs HBT semiconductor process developed and owned by Skyworks Solutions, Inc., USA. The circuit techniques that have enabled the successful and full on-chip embodiment of the technique are analyzed in details. The IC implementation is discussed, and experimental results showing significant current reduction upon automatic hardware reconfiguration, gain regulation performances, and compliance with the stringent linearity requirements for COMA transmission demonstrate that the gated envelope feedback method is a viable and promising approach to automatic hardware reconfiguration of RFIC PA's for current reduction purposes. Moreover, in regard to on-chip integration of advanced PA control functions, it is demonstrated that the method is better positioning GaAs HBT technologies, which are known to offer very competitive RF performances but inherently have limited integration capabilities. / Finally, an analytical approach for the evaluation of inter-modulation distortion (IMD) in envelope feedback architectures is introduced, and the proposed design equations and methodology for IMD analysis may prove very helpful for theoretical analyses, for simulation tasks, and for experimental work.

No description available.

Indiana University-Purdue University Indianapolis (IUPUI) / This thesis presents a converter topology for photovoltaic panels. This topology minimizes the number of switching devices used, thereby reducing power losses that arise from high frequency switching operations. The control strategy is implemented using a simple micro-controller that implements the proportional plus integral control. All the control loops are closed feedback loops hence minimizing error instantaneously and adjusting efficiently to system variations. The energy management between three components, namely, the photovoltaic panel, a battery and a DC link for a microgrid, is shown distributed over three modes. These modes are dependent on the irradiance from the sunlight. All three modes are simulated. The maximum power point tracking of the system plays a crucial role in this configuration, as it is one of the main challenges tackled by the control system. Various methods of MPPT are discussed, and the Perturb and Observe method is employed and is described in detail. Experimental results are shown for the maximum power point tracking of this system with a scaled down version of the panel's actual capability.