Cílem této práce bylo studium aktivního učení automatů, navržení a implementace softwarové architektury pro automatickou konstrukci hlídacího obvodu dané jednotky implementované v FPGA a ověření funkčnosti hlídacího obvodu pomocí injekce poruch. Hlídací obvod, tzv. online checker, má za úkol zabezpečovat danou jednotku proti poruchám. Checker je konstruován z modelu odvozeného pomocí aktivního učení automatů, které probíhá na základě komunikace se simulátorem. Pro implementaci učícího prostředí byla použita knihovna LearnLib, která poskytuje algoritmy aktivního učení automatů a jejich optimalizace. Byla navržena a implementována experimentální platforma umožňující řízenou injekci poruch do designu v FPGA, která slouží k otestování checkeru. Výsledky experimentů ukazují, že při použití checkeru a rekonfigurace je možné snížit chybovost designu o více než 98%.

SRAM-based FPGAs provide valuable computation resources and reconfigurability; however, ionizing radiation can cause designs operating on these devices to fail. The sensitivity of an FPGA design to configuration upsets, or its SEU sensitivity, is an indication of a design's failure rate. SEU mitigation techniques can reduce the SEU sensitivity of FPGA designs in harsh radiation environments. The reliability benefits of these techniques must be determined before they can be used in mission-critical applications and can be determined by comparing the SEU sensitivity of an FPGA design with and without these techniques applied to it. Many approaches can be taken to evaluate the SEU sensitivity of an FPGA design. This work describes a low-cost easier-to-implement approach for evaluating the SEU sensitivity of an FPGA design. This approach uses additional logic resources on the same FPGA as the design under test to determine when the design has failed, or deviated from its specified behavior. Three SEU mitigation techniques were evaluated using this approach: triple modular redundancy (TMR), configuration scrubbing, and user-memory scrubbing. Significant reduction in SEU sensitivity is demonstrated through fault injection and radiation testing. Two LEON3 processors operating in lockstep are compared against each other using on-chip error detection logic on the same FPGA. The design SEU sensitivity is reduced by 27x when TMR and configuration scrubbing are applied, and by approximately 50x when TMR, configuration scrubbing, and user-memory scrubbing are applied together. Using this approach, an SEU sensitivity comparison is made of designs implemented on both an Altera Stratix V FPGA and a Xilinx Kintex 7 FPGA. Several instances of a finite state machine are compared against each other and a set of golden output vectors, all on the same FPGA. Instances of an AES cryptography core are chained together and the output of two chains are compared using on-chip error detection. Fault injection and neutron radiation testing reveal several similarities between the two FPGA architectures. SEU mitigation techniques reduce the SEU sensitivity of the two designs between 4x and 728x. Protecting on-chip functional error detection logic with TMR and duplication with compare (DWC) is compared. Fault injection results suggest that it is more favorable to protect on-chip functional error detection logic with DWC than it is to protect it with TMR for error detection.

Made available in DSpace on 2014-12-17T15:08:35Z (GMT). No. of bitstreams: 1 MariaGCF_DISSERT.pdf: 1563382 bytes, checksum: 9e5bcfc73a3483582639c492a9c53f64 (MD5) Previous issue date: 2014-03-11 / Coordena??o de Aperfei?oamento de Pessoal de N?vel Superior / In this work, from the case of Mr. Lunga, a character of the brazilian northeastern culture whose stories circulated orally until they turned into verses of cordel (regional literature illustrated by xylographic printing images), we intend to understand that gender of leaflet, as significant cultural product, like media, with specific language features that act as means of construction and transmission of realities. To understand this phenomenon of meaning production in the cordel media, we used hermeneutics as a method and applied the general theory of interpretation in six chosen leaflets. We worked with a constructivist perspective that grounds the discussion of everyday reality and fiction, concepts that are raised around the essence of the character that is real, but it is also part of the creative activities of poets, how both are interrelated and constitute the understanding that individuals have the real. From the analyzes, we realize that each poet presents the fields of significance of Mr. Lunga in a different way, based on subjectivity, intention and mediations between each of them and the discourses they produce. Each cordelist contributes in his own way of significance for the construction of the imaginary Mr. Lunga. The speech of the cordelists contains a number of elements that aim to legitimize as truth the actions described. In this confrontation, our goal in this work is to understand the construction of the fields of signification, where these discourses are located, the production of meaning around a character who is not in a finite field, but transits through many of them, making the boundaries between reality and fiction dynamic / Neste trabalho pretendemos, a partir do caso de Seu Lunga, um personagem da cultura nordestina, cujas hist?rias circularam oralmente at? virarem versos de cordel, compreender o folheto, produto cultural t?o significativo, como m?dia, com caracter?sticas de linguagem espec?ficas, que atuam como formas de constru??o e transmiss?o de realidades. Para compreender este fen?meno de produ??o de sentidos na m?dia cordel, utilizamos a hermen?utica como m?todo e aplicamos a teoria geral da interpreta??o aos seis folhetos escolhidos. Trabalhamos com uma perspectiva construtivista, que nos embasa na discuss?o sobre realidade cotidiana e fic??o, conceitos que s?o levantados em torno da ess?ncia do personagem que ? real, mas que ? tamb?m parte das atividades criativas dos poetas, como ambos est?o interligados e constituem a compreens?o que os indiv?duos t?m do real. A partir das an?lises realizadas, percebemos que cada poeta apresenta os campos de significa??o de Seu Lunga de uma forma diferenciada, partindo da subjetividade, da intencionalidade e das media??es existentes entre cada um deles e os discursos que produzem. Cada cordelista contribui a seu modo de significa??o para a constru??o do imagin?rio em torno de Seu Lunga. O discurso dos cordelistas cont?m uma s?rie de elementos que buscam legitimar como verdade as a??es descritas. Neste embate, nosso objetivo neste trabalho ? o de compreender a constru??o dos campos de significa??o, onde esses discursos se localizam, a produ??o de sentidos em torno de um personagem que n?o est? em um campo finito, mas que transita por diversos deles, tornando din?micos os limites entre realidade e fic??o

The Xilinx Multiprocessor System-on-Chip (MPSoC) is a complex device that uses 16nm FinFET technology to combine multiple processors, a large amount of FPGA resources, and many I/O interfaces on a single chip die. These features make the MPSoC a high-performance and architecturally flexible device. The potential computing power makes the MPSoC ideal for many embedded applications including terrestrial and space applications. The MPSoC, however, does not have extensive radiation history as many other devices have. The extent of the effect that ionized particles may have on the MPSoC is not well established. To solve this problem, neutron radiation testing can be used to determine the device's susceptibility to single-event upsets (SEUs). Though this thesis is not intended to qualify the MPSoC for space, this work does provide useful neutron radiation test data that helps to characterize the susceptible nature of the device. This thesis summarizes the SEU results obtained from neutron testing on the UltraScale+ MPSoC ZU9EG device. A series of three neutron beam tests were performed on the MPSoC ZU9EG at Los Alamos National Laboratories (LANL). Testing was performed using a novel testing methodology to collect SEU counts on the programmable logic and the processing system simultaneously. These results show a 10.1× improvement of the programmable logic CRAM over the previous Xilinx UltraScale device series.

The Xilinx Multiprocessor System-on-Chip (MPSoC) is a complex device that uses 16nm FinFET technology to combine multiple processors, a large amount of FPGA resources, and many I/O interfaces on a single chip die. These features make the MPSoC a high-performance and architecturally flexible device. The potential computing power makes the MPSoC ideal for many embedded applications including terrestrial and space applications.The MPSoC, however, does not have extensive radiation history as many other devices have. The extent of the effect that ionized particles may have on the MPSoC is not well established. To solve this problem, neutron radiation testing can be used to determine the device's susceptibility to single-event upsets (SEUs). . Though this thesis is not intended to qualify the MPSoC for space, this work does provide useful neutron radiation test data that helps to characterize the susceptible nature of the device. This thesis summarizes the SEU results obtained from neutron testing on the UltraScale+ MPSoC ZU9EG device. A series of three neutron beam tests were performed on the MPSoC ZU9EG at Los Alamos National Laboratories (LANL). Testing was performed using a novel testing methodology to collect SEU counts on the programmable logic and the processing system simultaneously. These results show a $10.1 timess improvement of the programmable logic CRAM over the previous Xilinx UltraScale device series.

Les DRAMs sont des mémoires fréquemment utilisées dans les systèmes aéronautiques et spatiaux. Leur tenue aux radiations doit être connue pour satisfaire les exigences de fiabilité des applications critiques. Ces évaluations sont traditionnellement faites en accélérateur de particules. Cependant, les composants se complexifient avec l'intégration technologique. De nouveaux effets apparaissent, impliquant l'augmentation des temps et des coûts de test. Il existe une solution complémentaire, le laser impulsionnel, qui déclenche des effets similaires aux particules. Grâce à ces deux moyens de test, il s'est agi d'étudier les principaux modes de défaillance des DRAMs liés aux radiations : les SEUs (Single Event Upset) dans les plans mémoire, et les SEFIs (Single Event Functional Interrupt) dans les circuits périphériques. L'influence des motifs de test sur les sensibilités SEUs et SEFIs selon la technologie utilisée a ainsi été démontrée. L'étude a de plus identifié l'origine des SEFIs les plus fréquents. En outre, des techniques de test laser ont été développées pour quantifier les surfaces sensibles des différents effets. De ces travaux a pu être dégagée une nouvelle méthodologie de test destinée à l'industrie. Son objectif est d'optimiser l'efficacité et le coût des caractérisations, grâce à l'utilisation de l'outil laser de façon complémentaire aux accélérateurs de particules. Enfin, une nouvelle solution de tolérance aux fautes est proposée : basée sur la propriété des cellules DRAMs d'être immune aux radiations lorsqu'elles sont déchargées, cette technique permet la correction de tous les bits d'un mot logique.

La réduction des dimensions et paramètres électriques des transistors, fruit des progrès dans les technologies de fabrication de circuits intégrés, rend les composants présents et futurs de plus en plus sensibles aux perturbations appelées évènements singuliers S.E.E. (Single Event Effects). Ces événements sont la conséquence d'une impulsion de courant résultant de l'impact dans des zones sensibles du circuit, de particules énergétiques présentes dans l'environnement dans lequel ils fonctionnent. Parmi les différents types de SEE, peuvent être mentionnés les SEU (Single Event Upsets) qui consistent en l'inversion du contenu de cellules mémoires, les SEL (Single Event Latchups) qui donnent lieu à des courts-circuits masse-alimentation et peuvent donc conduire à la destruction du circuit par effet thermique. Cette thèse a pour but de décrire et valider les méthodologies nécessaires pour évaluer de manière précise la sensibilité face aux radiations de deux types de circuits numériques représentatifs, processeurs et mémoires, composants utilisés dans la plupart des systèmes embarqués.

<p>Nuclear particles hitting the silicon in a electronic device can cause a change in the data in a memory bit cell or in a flip-flop. The device is still working, but the data is corrupted and this is called a soft error. A soft error caused by a single nuclear particle is called a single event upset and is a growing problem. Research is ongoing at Saab aiming at how susceptible random access memories are to protons and neutrons.</p><p>This thesis describes the development of equipment for measuring cosmic-ray effects on DRAM in laboratories. The system is built on existing hardware with a FPGA as the core unit. A short history of soft errors is also given and what causes it. How a DRAM works and basic operation is explained and the difference between a SRAM. The result is a working system ready to be used.</p>

Field-effect transistor technologies have been critical building blocks for satellite systems since their introduction into the microelectronics industry. The extremely high cost of launching payloads into orbit necessitates systems to have small form factor, ultra low-power consumption, and reliable lifetime operation, while satisfying the performance requirements of a given application. Silicon-based complementary metal-oxide-semiconductors (Si CMOS) have traditionally been able to adequately meet these demands when coupled with radiation hardening techniques that have been developed over years of invested research. However, as customer demands increase, pushing the limits of system throughput, noise, and speed, alternative technologies must be employed. Silicon-germanium BiCMOS platforms have been identfied as a technology candidate for meeting the performance criteria of these pioneering satellite systems and deep space applications, contingent on their ability to be hardened to radiation-induced damage. Given that SiGe technology is a relative new- comer to terrestrial and extra-terrestrial applications in radiation-rich environments, the same wealth of knowledge of time-tested radiation hardening methodologies has not been established as it has for Si CMOS. Although SiGe BiCMOS technology has been experimentally proven to be inherently tolerant to total-ionizing dose damage mechanism, the single event susceptibility of this technology remains a primary concern. The objective of this research is to characterize the physical mechanisms that drive the origination of ion-induced transient terminal currents in SiGe HBTs that subsequently lead to a wide range of possible single event phenomena. Building upon this learning, a variety of device-level hardening methodologies are explored and tested for efficacy.

Nuclear particles hitting the silicon in a electronic device can cause a change in the data in a memory bit cell or in a flip-flop. The device is still working, but the data is corrupted and this is called a soft error. A soft error caused by a single nuclear particle is called a single event upset and is a growing problem. Research is ongoing at Saab aiming at how susceptible random access memories are to protons and neutrons. This thesis describes the development of equipment for measuring cosmic-ray effects on DRAM in laboratories. The system is built on existing hardware with a FPGA as the core unit. A short history of soft errors is also given and what causes it. How a DRAM works and basic operation is explained and the difference between a SRAM. The result is a working system ready to be used.