With a reference specification model in terms of 8 GS/s Sigma Delta Modulator in a 28 nm CMOS process consuming 890 mW, the purpose with this thesis is to construct a similar and simpler model but with higher specification demands. In a 22 nm SOI process with an input signal bandwidth of 500 MHz sampled at 16 GS/s with a power consumption below 2 W, the objective is to design a Continuous-Time Sigma Delta Modulator with verified simulated functionality on a transistor level basis. This specification is accomplished - with a power consumption in total of 75 mW. The design methodology is divided into an integrator part along with a quantizer and feedback DAC part. A top-down strategy is carried out starting with an ideal high level Verilog-A model for the complete system, followed by a hardware implementation on transistor level.

Recently short word-length (normally 1 bit or bits) processing has become a promising technique. However, there are unresolved issues in sigma-delta modulation, which is the basis for 1b/2b systems. These issues hindered the full adoption of single-bit techniues in industry. Among these problems is the stability of high-order modulators and the limit cycle behaviour. More importantly, there is no adaptive LMS structure of any kind in 1b/2b domain. The challenge in this problem is the harsh quantization that prevents straightforward LMS application. In this thesis, the focus has been made on three axes: designing new single-bit DSP applications, proposing novel approaches for stability analysis, and tacking the unresolved problems of 1b/2b adaptive filtering. Two structures for 1b digital comb filtering are proposed. A ternary DC blocker structure is also presented and performance is tested. We also proposed a single-bit multiplierless DC-blocking structure. The s tability of a single-bit high-order signma-delta modulator is studied under dc inputs. A new approach for stability analysis is proposed based on analogy with PLL analysis. Finally we succeeded in designing 1b/2b Wiener-like filtering and introduced (for the first time) three 1b/2b adaptive schemes.

<p>Today the frequency spectrum is full of wireless standards. The most common technique being used is the frequency modulation. To take advantage of this and the technology improvement a new wireless communication standard is being developed. This standard is using a low power impulse modulation method, allowing it to overlap with other standards. The proposed standard called IEEE802.15.3a is applied at an Ultra Wide Band and has potential to be used both in interchip and intrasystem communication, since it allows a very high data density. </p><p>In this thesis the analog to digital converter is designed, which is one part of a communication system. Although the signal bandwidth is very wide the converter is designed as a Sigma-Delta modulator, which is most suitable for low-speed applications. Its main advantages over high-speed converters are less area and less power consumption. The goal of this project is to investigate if the CMOS090 process technology will be sufficient for reaching a signal-to-noise ratio, SNR, of 30 dB in a signal band of 264 MHz. </p><p>The main limiting factor during the design of the modulator is the excess feedback delay. This delay degrades the SNR and can even make the system unstable. At a feedback delay of 83 ps and a sampling frequency of 6.336 GHz, the maximum SNR achieved was 27 dB. At this high frequency the modulator is close to instability. Hence, to ensure stability a maximum sampling frequency of 4.224 GHz is chosen, achieving a SNR of 19 dB. </p><p>The effect of the feedback delay can be reduced either by using a different structure or by using compensation methods, either of them would probably allow a SNR above 30 dB.</p>

Sigma-delta analog-to-digital converters are gaining in popularity in recent times because of their ability to trade-off resolutions in the time and voltage domains. In particular, continuous-time modulators are finding more acceptance at higher bandwidths due to the additional advantages they provide, such as better power efficiency and inherent anti-aliasing filtering, compared to their discrete-time counterparts. This thesis work presents the system level design of a continuous-time low-pass sigma-delta modulator targeting 11 bits of resolution over 100MHz signal bandwidth. The design considerations and tradeoffs involved at the system level are presented. The individual building blocks in the modulators are modeled with non-idealities and specifications for the various blocks are obtained in detail. Simulation results obtained from behavioral models of the system in MATLAB and Cadence environment show that a signal-to-noise-and-distortion-ratio (SNDR) of 69.6dB is achieved. A loop filter composed of passive LC sections is utilized in place of integrators or resonators used in traditional modulator implementations. Gain in the forward signal path is realized using active circuits based on simple transconductance stages. A novel method to compensate for excess delay in the loop without using an extra summing amplifier is proposed.

Today the frequency spectrum is full of wireless standards. The most common technique being used is the frequency modulation. To take advantage of this and the technology improvement a new wireless communication standard is being developed. This standard is using a low power impulse modulation method, allowing it to overlap with other standards. The proposed standard called IEEE802.15.3a is applied at an Ultra Wide Band and has potential to be used both in interchip and intrasystem communication, since it allows a very high data density. In this thesis the analog to digital converter is designed, which is one part of a communication system. Although the signal bandwidth is very wide the converter is designed as a Sigma-Delta modulator, which is most suitable for low-speed applications. Its main advantages over high-speed converters are less area and less power consumption. The goal of this project is to investigate if the CMOS090 process technology will be sufficient for reaching a signal-to-noise ratio, SNR, of 30 dB in a signal band of 264 MHz. The main limiting factor during the design of the modulator is the excess feedback delay. This delay degrades the SNR and can even make the system unstable. At a feedback delay of 83 ps and a sampling frequency of 6.336 GHz, the maximum SNR achieved was 27 dB. At this high frequency the modulator is close to instability. Hence, to ensure stability a maximum sampling frequency of 4.224 GHz is chosen, achieving a SNR of 19 dB. The effect of the feedback delay can be reduced either by using a different structure or by using compensation methods, either of them would probably allow a SNR above 30 dB.

The thesis proposes an integrator with an OPAMP in the feedback loop to fulfill 1MHz bandwidth SI Sigma Delta modulator. The OPAMP is used to pull down the input impedance and get high speed and high resolution. Oversampling and noise shaping are the two keys of Sigma Delta modulator. In structure, multistage is helpful for depressing noises and we use three stages to fulfill this 4-order proposed Sigma Delta modulator. The proposed Sigma Delta modulator uses TSMC 0.18£gm CMOS process and it is a 4-order and three stages SI Sigma Delta modulator. The sampling rate is 32MHz, bandwidth is 1MHz, and oversampling ratio is 16.

Continuous-time sigma-delta modulator can be applied to wireless communications, photography and MP3 player. Portable electronics products became mainstream the design of a low power consumption analog circuit become important. Therefore, this paper presents a low power consumption continuous-time sigma-delta modulator. The low-power continuous-time sigma-delta modulator includes one-bit quantizer and a third-order loop filter consisting of resistor-capacitor integrators. Through the modified Z-transform, the discrete time loop filter design is transformed to the continuous time loop filter design. The proposed sigma-delta modulator used TSMC 0.18£gm CMOS 1P6M standard process, and its supply voltage is 1V, oversampling ratio is 32, bandwidth is 200 KHz, effective number is 13bit, power consumption is 1.5mW. Keywords: GSM, low power consumption, low power supply, continuous-time, sigma-delta modulator.

Continuous-time sigma-delta modulators play an important role in the development of biomedical sensors. It is suitable for monitoring of basic human vital functions (i.e., heartbeat and respiration). However, the physiological signal is very weak and it belongs to low-frequency range, the observed signals are strongly inter&not;fered by the intrinsic flicker noise form CMOS transistors, which will cause a certain degree of difficulty in the identification. This thesis describes the implementation of loop filter using a differential chopper-stabilized configuration to reduce the influence of flicker noise on sigma-delta modulator within the signal bandwidth. The noise analysis of this sigma-delta modulator is calculated by the time-domain noise simulation. This method can take the noise factors into account when analyzing the overall performance. The proposed sigma-delta modulator is fabricated using TSMC 0.35£gm 2P4M CMOS technology. The chip area is 1.403 x 1.4 mm2. With a sampling rate of 20.8 kHz, the modulator achieves 84.4 dB of the peak SNDR and ENOB is 13.7-bit within signal band&not;width of 10Hz. It dissipates 3.46 mW under 3V supply voltage.

Sigma-delta analog-to-digital converters are gaining in popularity in recent times because of their ability to trade-off resolutions in the time and voltage domains. In particular, continuous-time modulators are finding more acceptance at higher bandwidths due to the additional advantages they provide, such as better power efficiency and inherent anti-aliasing filtering, compared to their discrete-time counterparts. This thesis work presents the system level design of a continuous-time low-pass sigma-delta modulator targeting 11 bits of resolution over 100MHz signal bandwidth. The design considerations and tradeoffs involved at the system level are presented. The individual building blocks in the modulators are modeled with non-idealities and specifications for the various blocks are obtained in detail. Simulation results obtained from behavioral models of the system in MATLAB and Cadence environment show that a signal-to-noise-and-distortion-ratio (SNDR) of 69.6dB is achieved. A loop filter composed of passive LC sections is utilized in place of integrators or resonators used in traditional modulator implementations. Gain in the forward signal path is realized using active circuits based on simple transconductance stages. A novel method to compensate for excess delay in the loop without using an extra summing amplifier is proposed.

A low voltage low power sigma¡Vdelta modulator for voice applications is presented. The implementation of proposed sigma-delta modulator is based on switched-capacitor circuit. Bootstrapped switches were used to replace CMOS transmission gates for increasing the insufficient driving of switched-capacitor circuit under the low voltage operation. To reduce the power dissipation, an improved current mirror OTA were designed with rail-to-rail output swing, which can also make the voltage gain enhance 10~20 dB and overcome the poor voltage gain shortage of traditional current mirror OTA. The post-simulation result shows that the modulator achieves a dynamic range of 77 dB, a peak signal-to-noise ratio of 82 dB, and the sigma-delta modulator dissipates 25£gW under 1.1-V voltage supply, using TSMC 0.18£gm 1P6M CMOS technology.